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Diffstat (limited to 'drivers/net/atl1/atl1_hw.c')
-rw-r--r--drivers/net/atl1/atl1_hw.c720
1 files changed, 0 insertions, 720 deletions
diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atl1/atl1_hw.c
deleted file mode 100644
index 9d3bd22e3a82..000000000000
--- a/drivers/net/atl1/atl1_hw.c
+++ /dev/null
@@ -1,720 +0,0 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 struct pci_dev *pdev = hw->back->pdev;
42 u32 icr;
43 int i;
44
45 /*
46 * Clear Interrupt mask to stop board from generating
47 * interrupts & Clear any pending interrupt events
48 */
49 /*
50 * iowrite32(0, hw->hw_addr + REG_IMR);
51 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
52 */
53
54 /*
55 * Issue Soft Reset to the MAC. This will reset the chip's
56 * transmit, receive, DMA. It will not effect
57 * the current PCI configuration. The global reset bit is self-
58 * clearing, and should clear within a microsecond.
59 */
60 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
61 ioread32(hw->hw_addr + REG_MASTER_CTRL);
62
63 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
64 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
65
66 msleep(1); /* delay about 1ms */
67
68 /* Wait at least 10ms for All module to be Idle */
69 for (i = 0; i < 10; i++) {
70 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
71 if (!icr)
72 break;
73 msleep(1); /* delay 1 ms */
74 cpu_relax(); /* FIXME: is this still the right way to do this? */
75 }
76
77 if (icr) {
78 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
79 return icr;
80 }
81
82 return ATL1_SUCCESS;
83}
84
85/* function about EEPROM
86 *
87 * check_eeprom_exist
88 * return 0 if eeprom exist
89 */
90static int atl1_check_eeprom_exist(struct atl1_hw *hw)
91{
92 u32 value;
93 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
94 if (value & SPI_FLASH_CTRL_EN_VPD) {
95 value &= ~SPI_FLASH_CTRL_EN_VPD;
96 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
97 }
98
99 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
100 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
101}
102
103static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
104{
105 int i;
106 u32 control;
107
108 if (offset & 3)
109 return false; /* address do not align */
110
111 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
112 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
113 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
114 ioread32(hw->hw_addr + REG_VPD_CAP);
115
116 for (i = 0; i < 10; i++) {
117 msleep(2);
118 control = ioread32(hw->hw_addr + REG_VPD_CAP);
119 if (control & VPD_CAP_VPD_FLAG)
120 break;
121 }
122 if (control & VPD_CAP_VPD_FLAG) {
123 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
124 return true;
125 }
126 return false; /* timeout */
127}
128
129/*
130 * Reads the value from a PHY register
131 * hw - Struct containing variables accessed by shared code
132 * reg_addr - address of the PHY register to read
133 */
134s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
135{
136 u32 val;
137 int i;
138
139 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
140 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
141 MDIO_CLK_SEL_SHIFT;
142 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
143 ioread32(hw->hw_addr + REG_MDIO_CTRL);
144
145 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
146 udelay(2);
147 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
148 if (!(val & (MDIO_START | MDIO_BUSY)))
149 break;
150 }
151 if (!(val & (MDIO_START | MDIO_BUSY))) {
152 *phy_data = (u16) val;
153 return ATL1_SUCCESS;
154 }
155 return ATL1_ERR_PHY;
156}
157
158#define CUSTOM_SPI_CS_SETUP 2
159#define CUSTOM_SPI_CLK_HI 2
160#define CUSTOM_SPI_CLK_LO 2
161#define CUSTOM_SPI_CS_HOLD 2
162#define CUSTOM_SPI_CS_HI 3
163
164static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
165{
166 int i;
167 u32 value;
168
169 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
170 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
171
172 value = SPI_FLASH_CTRL_WAIT_READY |
173 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
174 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
175 SPI_FLASH_CTRL_CLK_HI_MASK) <<
176 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
177 SPI_FLASH_CTRL_CLK_LO_MASK) <<
178 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
179 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
180 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
181 SPI_FLASH_CTRL_CS_HI_MASK) <<
182 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
183 SPI_FLASH_CTRL_INS_SHIFT;
184
185 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
186
187 value |= SPI_FLASH_CTRL_START;
188 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
189 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
190
191 for (i = 0; i < 10; i++) {
192 msleep(1); /* 1ms */
193 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
194 if (!(value & SPI_FLASH_CTRL_START))
195 break;
196 }
197
198 if (value & SPI_FLASH_CTRL_START)
199 return false;
200
201 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
202
203 return true;
204}
205
206/*
207 * get_permanent_address
208 * return 0 if get valid mac address,
209 */
210static int atl1_get_permanent_address(struct atl1_hw *hw)
211{
212 u32 addr[2];
213 u32 i, control;
214 u16 reg;
215 u8 eth_addr[ETH_ALEN];
216 bool key_valid;
217
218 if (is_valid_ether_addr(hw->perm_mac_addr))
219 return 0;
220
221 /* init */
222 addr[0] = addr[1] = 0;
223
224 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
225 reg = 0;
226 key_valid = false;
227 /* Read out all EEPROM content */
228 i = 0;
229 while (1) {
230 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
231 if (key_valid) {
232 if (reg == REG_MAC_STA_ADDR)
233 addr[0] = control;
234 else if (reg == (REG_MAC_STA_ADDR + 4))
235 addr[1] = control;
236 key_valid = false;
237 } else if ((control & 0xff) == 0x5A) {
238 key_valid = true;
239 reg = (u16) (control >> 16);
240 } else
241 break; /* assume data end while encount an invalid KEYWORD */
242 } else
243 break; /* read error */
244 i += 4;
245 }
246
247 *(u32 *) &eth_addr[2] = swab32(addr[0]);
248 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
249 if (is_valid_ether_addr(eth_addr)) {
250 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
251 return 0;
252 }
253 return 1;
254 }
255
256 /* see if SPI FLAGS exist ? */
257 addr[0] = addr[1] = 0;
258 reg = 0;
259 key_valid = false;
260 i = 0;
261 while (1) {
262 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
263 if (key_valid) {
264 if (reg == REG_MAC_STA_ADDR)
265 addr[0] = control;
266 else if (reg == (REG_MAC_STA_ADDR + 4))
267 addr[1] = control;
268 key_valid = false;
269 } else if ((control & 0xff) == 0x5A) {
270 key_valid = true;
271 reg = (u16) (control >> 16);
272 } else
273 break; /* data end */
274 } else
275 break; /* read error */
276 i += 4;
277 }
278
279 *(u32 *) &eth_addr[2] = swab32(addr[0]);
280 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
281 if (is_valid_ether_addr(eth_addr)) {
282 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
283 return 0;
284 }
285
286 /*
287 * On some motherboards, the MAC address is written by the
288 * BIOS directly to the MAC register during POST, and is
289 * not stored in eeprom. If all else thus far has failed
290 * to fetch the permanent MAC address, try reading it directly.
291 */
292 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
293 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
294 *(u32 *) &eth_addr[2] = swab32(addr[0]);
295 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
296 if (is_valid_ether_addr(eth_addr)) {
297 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
298 return 0;
299 }
300
301 return 1;
302}
303
304/*
305 * Reads the adapter's MAC address from the EEPROM
306 * hw - Struct containing variables accessed by shared code
307 */
308s32 atl1_read_mac_addr(struct atl1_hw *hw)
309{
310 u16 i;
311
312 if (atl1_get_permanent_address(hw))
313 random_ether_addr(hw->perm_mac_addr);
314
315 for (i = 0; i < ETH_ALEN; i++)
316 hw->mac_addr[i] = hw->perm_mac_addr[i];
317 return ATL1_SUCCESS;
318}
319
320/*
321 * Hashes an address to determine its location in the multicast table
322 * hw - Struct containing variables accessed by shared code
323 * mc_addr - the multicast address to hash
324 *
325 * atl1_hash_mc_addr
326 * purpose
327 * set hash value for a multicast address
328 * hash calcu processing :
329 * 1. calcu 32bit CRC for multicast address
330 * 2. reverse crc with MSB to LSB
331 */
332u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
333{
334 u32 crc32, value = 0;
335 int i;
336
337 crc32 = ether_crc_le(6, mc_addr);
338 for (i = 0; i < 32; i++)
339 value |= (((crc32 >> i) & 1) << (31 - i));
340
341 return value;
342}
343
344/*
345 * Sets the bit in the multicast table corresponding to the hash value.
346 * hw - Struct containing variables accessed by shared code
347 * hash_value - Multicast address hash value
348 */
349void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
350{
351 u32 hash_bit, hash_reg;
352 u32 mta;
353
354 /*
355 * The HASH Table is a register array of 2 32-bit registers.
356 * It is treated like an array of 64 bits. We want to set
357 * bit BitArray[hash_value]. So we figure out what register
358 * the bit is in, read it, OR in the new bit, then write
359 * back the new value. The register is determined by the
360 * upper 7 bits of the hash value and the bit within that
361 * register are determined by the lower 5 bits of the value.
362 */
363 hash_reg = (hash_value >> 31) & 0x1;
364 hash_bit = (hash_value >> 26) & 0x1F;
365 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
366 mta |= (1 << hash_bit);
367 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
368}
369
370/*
371 * Writes a value to a PHY register
372 * hw - Struct containing variables accessed by shared code
373 * reg_addr - address of the PHY register to write
374 * data - data to write to the PHY
375 */
376s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
377{
378 int i;
379 u32 val;
380
381 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
382 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
383 MDIO_SUP_PREAMBLE |
384 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
385 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
386 ioread32(hw->hw_addr + REG_MDIO_CTRL);
387
388 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
389 udelay(2);
390 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
391 if (!(val & (MDIO_START | MDIO_BUSY)))
392 break;
393 }
394
395 if (!(val & (MDIO_START | MDIO_BUSY)))
396 return ATL1_SUCCESS;
397
398 return ATL1_ERR_PHY;
399}
400
401/*
402 * Make L001's PHY out of Power Saving State (bug)
403 * hw - Struct containing variables accessed by shared code
404 * when power on, L001's PHY always on Power saving State
405 * (Gigabit Link forbidden)
406 */
407static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
408{
409 s32 ret;
410 ret = atl1_write_phy_reg(hw, 29, 0x0029);
411 if (ret)
412 return ret;
413 return atl1_write_phy_reg(hw, 30, 0);
414}
415
416/*
417 *TODO: do something or get rid of this
418 */
419s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
420{
421/* s32 ret_val;
422 * u16 phy_data;
423 */
424
425/*
426 ret_val = atl1_write_phy_reg(hw, ...);
427 ret_val = atl1_write_phy_reg(hw, ...);
428 ....
429*/
430 return ATL1_SUCCESS;
431}
432
433/*
434 * Resets the PHY and make all config validate
435 * hw - Struct containing variables accessed by shared code
436 *
437 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
438 */
439static s32 atl1_phy_reset(struct atl1_hw *hw)
440{
441 struct pci_dev *pdev = hw->back->pdev;
442 s32 ret_val;
443 u16 phy_data;
444
445 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
446 hw->media_type == MEDIA_TYPE_1000M_FULL)
447 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
448 else {
449 switch (hw->media_type) {
450 case MEDIA_TYPE_100M_FULL:
451 phy_data =
452 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
453 MII_CR_RESET;
454 break;
455 case MEDIA_TYPE_100M_HALF:
456 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
457 break;
458 case MEDIA_TYPE_10M_FULL:
459 phy_data =
460 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
461 break;
462 default: /* MEDIA_TYPE_10M_HALF: */
463 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
464 break;
465 }
466 }
467
468 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
469 if (ret_val) {
470 u32 val;
471 int i;
472 /* pcie serdes link may be down! */
473 dev_dbg(&pdev->dev, "pcie phy link down\n");
474
475 for (i = 0; i < 25; i++) {
476 msleep(1);
477 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
478 if (!(val & (MDIO_START | MDIO_BUSY)))
479 break;
480 }
481
482 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
483 dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
484 return ret_val;
485 }
486 }
487 return ATL1_SUCCESS;
488}
489
490/*
491 * Configures PHY autoneg and flow control advertisement settings
492 * hw - Struct containing variables accessed by shared code
493 */
494s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
495{
496 s32 ret_val;
497 s16 mii_autoneg_adv_reg;
498 s16 mii_1000t_ctrl_reg;
499
500 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
501 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
502
503 /* Read the MII 1000Base-T Control Register (Address 9). */
504 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
505
506 /*
507 * First we clear all the 10/100 mb speed bits in the Auto-Neg
508 * Advertisement Register (Address 4) and the 1000 mb speed bits in
509 * the 1000Base-T Control Register (Address 9).
510 */
511 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
512 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
513
514 /*
515 * Need to parse media_type and set up
516 * the appropriate PHY registers.
517 */
518 switch (hw->media_type) {
519 case MEDIA_TYPE_AUTO_SENSOR:
520 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
521 MII_AR_10T_FD_CAPS |
522 MII_AR_100TX_HD_CAPS |
523 MII_AR_100TX_FD_CAPS);
524 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
525 break;
526
527 case MEDIA_TYPE_1000M_FULL:
528 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
529 break;
530
531 case MEDIA_TYPE_100M_FULL:
532 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
533 break;
534
535 case MEDIA_TYPE_100M_HALF:
536 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
537 break;
538
539 case MEDIA_TYPE_10M_FULL:
540 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
541 break;
542
543 default:
544 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
545 break;
546 }
547
548 /* flow control fixed to enable all */
549 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
550
551 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
552 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
553
554 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
555 if (ret_val)
556 return ret_val;
557
558 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
559 if (ret_val)
560 return ret_val;
561
562 return ATL1_SUCCESS;
563}
564
565/*
566 * Configures link settings.
567 * hw - Struct containing variables accessed by shared code
568 * Assumes the hardware has previously been reset and the
569 * transmitter and receiver are not enabled.
570 */
571static s32 atl1_setup_link(struct atl1_hw *hw)
572{
573 struct pci_dev *pdev = hw->back->pdev;
574 s32 ret_val;
575
576 /*
577 * Options:
578 * PHY will advertise value(s) parsed from
579 * autoneg_advertised and fc
580 * no matter what autoneg is , We will not wait link result.
581 */
582 ret_val = atl1_phy_setup_autoneg_adv(hw);
583 if (ret_val) {
584 dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
585 return ret_val;
586 }
587 /* SW.Reset , En-Auto-Neg if needed */
588 ret_val = atl1_phy_reset(hw);
589 if (ret_val) {
590 dev_dbg(&pdev->dev, "error resetting phy\n");
591 return ret_val;
592 }
593 hw->phy_configured = true;
594 return ret_val;
595}
596
597static struct atl1_spi_flash_dev flash_table[] = {
598/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
599 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
600 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
601 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
602};
603
604static void atl1_init_flash_opcode(struct atl1_hw *hw)
605{
606 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
607 hw->flash_vendor = 0; /* ATMEL */
608
609 /* Init OP table */
610 iowrite8(flash_table[hw->flash_vendor].cmd_program,
611 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
612 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
613 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
614 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
615 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
616 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
617 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
618 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
619 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
620 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
621 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
622 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
623 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
624 iowrite8(flash_table[hw->flash_vendor].cmd_read,
625 hw->hw_addr + REG_SPI_FLASH_OP_READ);
626}
627
628/*
629 * Performs basic configuration of the adapter.
630 * hw - Struct containing variables accessed by shared code
631 * Assumes that the controller has previously been reset and is in a
632 * post-reset uninitialized state. Initializes multicast table,
633 * and Calls routines to setup link
634 * Leaves the transmit and receive units disabled and uninitialized.
635 */
636s32 atl1_init_hw(struct atl1_hw *hw)
637{
638 u32 ret_val = 0;
639
640 /* Zero out the Multicast HASH table */
641 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
642 /* clear the old settings from the multicast hash table */
643 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
644
645 atl1_init_flash_opcode(hw);
646
647 if (!hw->phy_configured) {
648 /* enable GPHY LinkChange Interrrupt */
649 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
650 if (ret_val)
651 return ret_val;
652 /* make PHY out of power-saving state */
653 ret_val = atl1_phy_leave_power_saving(hw);
654 if (ret_val)
655 return ret_val;
656 /* Call a subroutine to configure the link */
657 ret_val = atl1_setup_link(hw);
658 }
659 return ret_val;
660}
661
662/*
663 * Detects the current speed and duplex settings of the hardware.
664 * hw - Struct containing variables accessed by shared code
665 * speed - Speed of the connection
666 * duplex - Duplex setting of the connection
667 */
668s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
669{
670 struct pci_dev *pdev = hw->back->pdev;
671 s32 ret_val;
672 u16 phy_data;
673
674 /* ; --- Read PHY Specific Status Register (17) */
675 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
676 if (ret_val)
677 return ret_val;
678
679 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
680 return ATL1_ERR_PHY_RES;
681
682 switch (phy_data & MII_AT001_PSSR_SPEED) {
683 case MII_AT001_PSSR_1000MBS:
684 *speed = SPEED_1000;
685 break;
686 case MII_AT001_PSSR_100MBS:
687 *speed = SPEED_100;
688 break;
689 case MII_AT001_PSSR_10MBS:
690 *speed = SPEED_10;
691 break;
692 default:
693 dev_dbg(&pdev->dev, "error getting speed\n");
694 return ATL1_ERR_PHY_SPEED;
695 break;
696 }
697 if (phy_data & MII_AT001_PSSR_DPLX)
698 *duplex = FULL_DUPLEX;
699 else
700 *duplex = HALF_DUPLEX;
701
702 return ATL1_SUCCESS;
703}
704
705void atl1_set_mac_addr(struct atl1_hw *hw)
706{
707 u32 value;
708 /*
709 * 00-0B-6A-F6-00-DC
710 * 0: 6AF600DC 1: 000B
711 * low dword
712 */
713 value = (((u32) hw->mac_addr[2]) << 24) |
714 (((u32) hw->mac_addr[3]) << 16) |
715 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
716 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
717 /* high dword */
718 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
719 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
720}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 20:51:30 -0500