aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/acenic.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/acenic.c')
-rw-r--r--drivers/net/acenic.c3271
1 files changed, 3271 insertions, 0 deletions
diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c
new file mode 100644
index 000000000000..6eea3a8accb7
--- /dev/null
+++ b/drivers/net/acenic.c
@@ -0,0 +1,3271 @@
1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
53#include <linux/config.h>
54#include <linux/module.h>
55#include <linux/moduleparam.h>
56#include <linux/version.h>
57#include <linux/types.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/pci.h>
61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/mm.h>
68#include <linux/highmem.h>
69#include <linux/sockios.h>
70
71#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72#include <linux/if_vlan.h>
73#endif
74
75#ifdef SIOCETHTOOL
76#include <linux/ethtool.h>
77#endif
78
79#include <net/sock.h>
80#include <net/ip.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84#include <asm/irq.h>
85#include <asm/byteorder.h>
86#include <asm/uaccess.h>
87
88
89#define DRV_NAME "acenic"
90
91#undef INDEX_DEBUG
92
93#ifdef CONFIG_ACENIC_OMIT_TIGON_I
94#define ACE_IS_TIGON_I(ap) 0
95#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96#else
97#define ACE_IS_TIGON_I(ap) (ap->version == 1)
98#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99#endif
100
101#ifndef PCI_VENDOR_ID_ALTEON
102#define PCI_VENDOR_ID_ALTEON 0x12ae
103#endif
104#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107#endif
108#ifndef PCI_DEVICE_ID_3COM_3C985
109#define PCI_DEVICE_ID_3COM_3C985 0x0001
110#endif
111#ifndef PCI_VENDOR_ID_NETGEAR
112#define PCI_VENDOR_ID_NETGEAR 0x1385
113#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114#endif
115#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117#endif
118
119
120/*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126#endif
127#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129#endif
130#ifndef PCI_VENDOR_ID_SGI
131#define PCI_VENDOR_ID_SGI 0x10a9
132#endif
133#ifndef PCI_DEVICE_ID_SGI_ACENIC
134#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135#endif
136
137static struct pci_device_id acenic_pci_tbl[] = {
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159};
160MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
162#ifndef SET_NETDEV_DEV
163#define SET_NETDEV_DEV(net, pdev) do{} while(0)
164#endif
165
166#if LINUX_VERSION_CODE >= 0x2051c
167#define ace_sync_irq(irq) synchronize_irq(irq)
168#else
169#define ace_sync_irq(irq) synchronize_irq()
170#endif
171
172#ifndef offset_in_page
173#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
174#endif
175
176#define ACE_MAX_MOD_PARMS 8
177#define BOARD_IDX_STATIC 0
178#define BOARD_IDX_OVERFLOW -1
179
180#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
181 defined(NETIF_F_HW_VLAN_RX)
182#define ACENIC_DO_VLAN 1
183#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
184#else
185#define ACENIC_DO_VLAN 0
186#define ACE_RCB_VLAN_FLAG 0
187#endif
188
189#include "acenic.h"
190
191/*
192 * These must be defined before the firmware is included.
193 */
194#define MAX_TEXT_LEN 96*1024
195#define MAX_RODATA_LEN 8*1024
196#define MAX_DATA_LEN 2*1024
197
198#include "acenic_firmware.h"
199
200#ifndef tigon2FwReleaseLocal
201#define tigon2FwReleaseLocal 0
202#endif
203
204/*
205 * This driver currently supports Tigon I and Tigon II based cards
206 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
207 * GA620. The driver should also work on the SGI, DEC and Farallon
208 * versions of the card, however I have not been able to test that
209 * myself.
210 *
211 * This card is really neat, it supports receive hardware checksumming
212 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
213 * firmware. Also the programming interface is quite neat, except for
214 * the parts dealing with the i2c eeprom on the card ;-)
215 *
216 * Using jumbo frames:
217 *
218 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
219 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
220 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
221 * interface number and <MTU> being the MTU value.
222 *
223 * Module parameters:
224 *
225 * When compiled as a loadable module, the driver allows for a number
226 * of module parameters to be specified. The driver supports the
227 * following module parameters:
228 *
229 * trace=<val> - Firmware trace level. This requires special traced
230 * firmware to replace the firmware supplied with
231 * the driver - for debugging purposes only.
232 *
233 * link=<val> - Link state. Normally you want to use the default link
234 * parameters set by the driver. This can be used to
235 * override these in case your switch doesn't negotiate
236 * the link properly. Valid values are:
237 * 0x0001 - Force half duplex link.
238 * 0x0002 - Do not negotiate line speed with the other end.
239 * 0x0010 - 10Mbit/sec link.
240 * 0x0020 - 100Mbit/sec link.
241 * 0x0040 - 1000Mbit/sec link.
242 * 0x0100 - Do not negotiate flow control.
243 * 0x0200 - Enable RX flow control Y
244 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
245 * Default value is 0x0270, ie. enable link+flow
246 * control negotiation. Negotiating the highest
247 * possible link speed with RX flow control enabled.
248 *
249 * When disabling link speed negotiation, only one link
250 * speed is allowed to be specified!
251 *
252 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
253 * to wait for more packets to arive before
254 * interrupting the host, from the time the first
255 * packet arrives.
256 *
257 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
258 * to wait for more packets to arive in the transmit ring,
259 * before interrupting the host, after transmitting the
260 * first packet in the ring.
261 *
262 * max_tx_desc=<val> - maximum number of transmit descriptors
263 * (packets) transmitted before interrupting the host.
264 *
265 * max_rx_desc=<val> - maximum number of receive descriptors
266 * (packets) received before interrupting the host.
267 *
268 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
269 * increments of the NIC's on board memory to be used for
270 * transmit and receive buffers. For the 1MB NIC app. 800KB
271 * is available, on the 1/2MB NIC app. 300KB is available.
272 * 68KB will always be available as a minimum for both
273 * directions. The default value is a 50/50 split.
274 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
275 * operations, default (1) is to always disable this as
276 * that is what Alteon does on NT. I have not been able
277 * to measure any real performance differences with
278 * this on my systems. Set <val>=0 if you want to
279 * enable these operations.
280 *
281 * If you use more than one NIC, specify the parameters for the
282 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
283 * run tracing on NIC #2 but not on NIC #1 and #3.
284 *
285 * TODO:
286 *
287 * - Proper multicast support.
288 * - NIC dump support.
289 * - More tuning parameters.
290 *
291 * The mini ring is not used under Linux and I am not sure it makes sense
292 * to actually use it.
293 *
294 * New interrupt handler strategy:
295 *
296 * The old interrupt handler worked using the traditional method of
297 * replacing an skbuff with a new one when a packet arrives. However
298 * the rx rings do not need to contain a static number of buffer
299 * descriptors, thus it makes sense to move the memory allocation out
300 * of the main interrupt handler and do it in a bottom half handler
301 * and only allocate new buffers when the number of buffers in the
302 * ring is below a certain threshold. In order to avoid starving the
303 * NIC under heavy load it is however necessary to force allocation
304 * when hitting a minimum threshold. The strategy for alloction is as
305 * follows:
306 *
307 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
308 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
309 * the buffers in the interrupt handler
310 * RX_RING_THRES - maximum number of buffers in the rx ring
311 * RX_MINI_THRES - maximum number of buffers in the mini ring
312 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
313 *
314 * One advantagous side effect of this allocation approach is that the
315 * entire rx processing can be done without holding any spin lock
316 * since the rx rings and registers are totally independent of the tx
317 * ring and its registers. This of course includes the kmalloc's of
318 * new skb's. Thus start_xmit can run in parallel with rx processing
319 * and the memory allocation on SMP systems.
320 *
321 * Note that running the skb reallocation in a bottom half opens up
322 * another can of races which needs to be handled properly. In
323 * particular it can happen that the interrupt handler tries to run
324 * the reallocation while the bottom half is either running on another
325 * CPU or was interrupted on the same CPU. To get around this the
326 * driver uses bitops to prevent the reallocation routines from being
327 * reentered.
328 *
329 * TX handling can also be done without holding any spin lock, wheee
330 * this is fun! since tx_ret_csm is only written to by the interrupt
331 * handler. The case to be aware of is when shutting down the device
332 * and cleaning up where it is necessary to make sure that
333 * start_xmit() is not running while this is happening. Well DaveM
334 * informs me that this case is already protected against ... bye bye
335 * Mr. Spin Lock, it was nice to know you.
336 *
337 * TX interrupts are now partly disabled so the NIC will only generate
338 * TX interrupts for the number of coal ticks, not for the number of
339 * TX packets in the queue. This should reduce the number of TX only,
340 * ie. when no RX processing is done, interrupts seen.
341 */
342
343/*
344 * Threshold values for RX buffer allocation - the low water marks for
345 * when to start refilling the rings are set to 75% of the ring
346 * sizes. It seems to make sense to refill the rings entirely from the
347 * intrrupt handler once it gets below the panic threshold, that way
348 * we don't risk that the refilling is moved to another CPU when the
349 * one running the interrupt handler just got the slab code hot in its
350 * cache.
351 */
352#define RX_RING_SIZE 72
353#define RX_MINI_SIZE 64
354#define RX_JUMBO_SIZE 48
355
356#define RX_PANIC_STD_THRES 16
357#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
358#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
359#define RX_PANIC_MINI_THRES 12
360#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
361#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
362#define RX_PANIC_JUMBO_THRES 6
363#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
364#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
365
366
367/*
368 * Size of the mini ring entries, basically these just should be big
369 * enough to take TCP ACKs
370 */
371#define ACE_MINI_SIZE 100
372
373#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
374#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
375#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
376
377/*
378 * There seems to be a magic difference in the effect between 995 and 996
379 * but little difference between 900 and 995 ... no idea why.
380 *
381 * There is now a default set of tuning parameters which is set, depending
382 * on whether or not the user enables Jumbo frames. It's assumed that if
383 * Jumbo frames are enabled, the user wants optimal tuning for that case.
384 */
385#define DEF_TX_COAL 400 /* 996 */
386#define DEF_TX_MAX_DESC 60 /* was 40 */
387#define DEF_RX_COAL 120 /* 1000 */
388#define DEF_RX_MAX_DESC 25
389#define DEF_TX_RATIO 21 /* 24 */
390
391#define DEF_JUMBO_TX_COAL 20
392#define DEF_JUMBO_TX_MAX_DESC 60
393#define DEF_JUMBO_RX_COAL 30
394#define DEF_JUMBO_RX_MAX_DESC 6
395#define DEF_JUMBO_TX_RATIO 21
396
397#if tigon2FwReleaseLocal < 20001118
398/*
399 * Standard firmware and early modifications duplicate
400 * IRQ load without this flag (coal timer is never reset).
401 * Note that with this flag tx_coal should be less than
402 * time to xmit full tx ring.
403 * 400usec is not so bad for tx ring size of 128.
404 */
405#define TX_COAL_INTS_ONLY 1 /* worth it */
406#else
407/*
408 * With modified firmware, this is not necessary, but still useful.
409 */
410#define TX_COAL_INTS_ONLY 1
411#endif
412
413#define DEF_TRACE 0
414#define DEF_STAT (2 * TICKS_PER_SEC)
415
416
417static int link[ACE_MAX_MOD_PARMS];
418static int trace[ACE_MAX_MOD_PARMS];
419static int tx_coal_tick[ACE_MAX_MOD_PARMS];
420static int rx_coal_tick[ACE_MAX_MOD_PARMS];
421static int max_tx_desc[ACE_MAX_MOD_PARMS];
422static int max_rx_desc[ACE_MAX_MOD_PARMS];
423static int tx_ratio[ACE_MAX_MOD_PARMS];
424static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
425
426MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
427MODULE_LICENSE("GPL");
428MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
429
430module_param_array(link, int, NULL, 0);
431module_param_array(trace, int, NULL, 0);
432module_param_array(tx_coal_tick, int, NULL, 0);
433module_param_array(max_tx_desc, int, NULL, 0);
434module_param_array(rx_coal_tick, int, NULL, 0);
435module_param_array(max_rx_desc, int, NULL, 0);
436module_param_array(tx_ratio, int, NULL, 0);
437MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
438MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
439MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
440MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
441MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
442MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
443MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
444
445
446static char version[] __devinitdata =
447 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
448 " http://home.cern.ch/~jes/gige/acenic.html\n";
449
450static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
451static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
452static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
453
454static struct ethtool_ops ace_ethtool_ops = {
455 .get_settings = ace_get_settings,
456 .set_settings = ace_set_settings,
457 .get_drvinfo = ace_get_drvinfo,
458};
459
460static void ace_watchdog(struct net_device *dev);
461
462static int __devinit acenic_probe_one(struct pci_dev *pdev,
463 const struct pci_device_id *id)
464{
465 struct net_device *dev;
466 struct ace_private *ap;
467 static int boards_found;
468
469 dev = alloc_etherdev(sizeof(struct ace_private));
470 if (dev == NULL) {
471 printk(KERN_ERR "acenic: Unable to allocate "
472 "net_device structure!\n");
473 return -ENOMEM;
474 }
475
476 SET_MODULE_OWNER(dev);
477 SET_NETDEV_DEV(dev, &pdev->dev);
478
479 ap = dev->priv;
480 ap->pdev = pdev;
481 ap->name = pci_name(pdev);
482
483 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
484#if ACENIC_DO_VLAN
485 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
486 dev->vlan_rx_register = ace_vlan_rx_register;
487 dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
488#endif
489 if (1) {
490 dev->tx_timeout = &ace_watchdog;
491 dev->watchdog_timeo = 5*HZ;
492 }
493
494 dev->open = &ace_open;
495 dev->stop = &ace_close;
496 dev->hard_start_xmit = &ace_start_xmit;
497 dev->get_stats = &ace_get_stats;
498 dev->set_multicast_list = &ace_set_multicast_list;
499 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
500 dev->set_mac_address = &ace_set_mac_addr;
501 dev->change_mtu = &ace_change_mtu;
502
503 /* we only display this string ONCE */
504 if (!boards_found)
505 printk(version);
506
507 if (pci_enable_device(pdev))
508 goto fail_free_netdev;
509
510 /*
511 * Enable master mode before we start playing with the
512 * pci_command word since pci_set_master() will modify
513 * it.
514 */
515 pci_set_master(pdev);
516
517 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
518
519 /* OpenFirmware on Mac's does not set this - DOH.. */
520 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
521 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
522 "access - was not enabled by BIOS/Firmware\n",
523 ap->name);
524 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
525 pci_write_config_word(ap->pdev, PCI_COMMAND,
526 ap->pci_command);
527 wmb();
528 }
529
530 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
531 if (ap->pci_latency <= 0x40) {
532 ap->pci_latency = 0x40;
533 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
534 }
535
536 /*
537 * Remap the regs into kernel space - this is abuse of
538 * dev->base_addr since it was means for I/O port
539 * addresses but who gives a damn.
540 */
541 dev->base_addr = pci_resource_start(pdev, 0);
542 ap->regs = ioremap(dev->base_addr, 0x4000);
543 if (!ap->regs) {
544 printk(KERN_ERR "%s: Unable to map I/O register, "
545 "AceNIC %i will be disabled.\n",
546 ap->name, boards_found);
547 goto fail_free_netdev;
548 }
549
550 switch(pdev->vendor) {
551 case PCI_VENDOR_ID_ALTEON:
552 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
553 printk(KERN_INFO "%s: Farallon PN9100-T ",
554 ap->name);
555 } else {
556 printk(KERN_INFO "%s: Alteon AceNIC ",
557 ap->name);
558 }
559 break;
560 case PCI_VENDOR_ID_3COM:
561 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
562 break;
563 case PCI_VENDOR_ID_NETGEAR:
564 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
565 break;
566 case PCI_VENDOR_ID_DEC:
567 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
568 printk(KERN_INFO "%s: Farallon PN9000-SX ",
569 ap->name);
570 break;
571 }
572 case PCI_VENDOR_ID_SGI:
573 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
574 break;
575 default:
576 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
577 break;
578 }
579
580 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
581#ifdef __sparc__
582 printk("irq %s\n", __irq_itoa(pdev->irq));
583#else
584 printk("irq %i\n", pdev->irq);
585#endif
586
587#ifdef CONFIG_ACENIC_OMIT_TIGON_I
588 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
589 printk(KERN_ERR "%s: Driver compiled without Tigon I"
590 " support - NIC disabled\n", dev->name);
591 goto fail_uninit;
592 }
593#endif
594
595 if (ace_allocate_descriptors(dev))
596 goto fail_free_netdev;
597
598#ifdef MODULE
599 if (boards_found >= ACE_MAX_MOD_PARMS)
600 ap->board_idx = BOARD_IDX_OVERFLOW;
601 else
602 ap->board_idx = boards_found;
603#else
604 ap->board_idx = BOARD_IDX_STATIC;
605#endif
606
607 if (ace_init(dev))
608 goto fail_free_netdev;
609
610 if (register_netdev(dev)) {
611 printk(KERN_ERR "acenic: device registration failed\n");
612 goto fail_uninit;
613 }
614 ap->name = dev->name;
615
616 if (ap->pci_using_dac)
617 dev->features |= NETIF_F_HIGHDMA;
618
619 pci_set_drvdata(pdev, dev);
620
621 boards_found++;
622 return 0;
623
624 fail_uninit:
625 ace_init_cleanup(dev);
626 fail_free_netdev:
627 free_netdev(dev);
628 return -ENODEV;
629}
630
631static void __devexit acenic_remove_one(struct pci_dev *pdev)
632{
633 struct net_device *dev = pci_get_drvdata(pdev);
634 struct ace_private *ap = netdev_priv(dev);
635 struct ace_regs __iomem *regs = ap->regs;
636 short i;
637
638 unregister_netdev(dev);
639
640 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
641 if (ap->version >= 2)
642 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
643
644 /*
645 * This clears any pending interrupts
646 */
647 writel(1, &regs->Mb0Lo);
648 readl(&regs->CpuCtrl); /* flush */
649
650 /*
651 * Make sure no other CPUs are processing interrupts
652 * on the card before the buffers are being released.
653 * Otherwise one might experience some `interesting'
654 * effects.
655 *
656 * Then release the RX buffers - jumbo buffers were
657 * already released in ace_close().
658 */
659 ace_sync_irq(dev->irq);
660
661 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
662 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
663
664 if (skb) {
665 struct ring_info *ringp;
666 dma_addr_t mapping;
667
668 ringp = &ap->skb->rx_std_skbuff[i];
669 mapping = pci_unmap_addr(ringp, mapping);
670 pci_unmap_page(ap->pdev, mapping,
671 ACE_STD_BUFSIZE,
672 PCI_DMA_FROMDEVICE);
673
674 ap->rx_std_ring[i].size = 0;
675 ap->skb->rx_std_skbuff[i].skb = NULL;
676 dev_kfree_skb(skb);
677 }
678 }
679
680 if (ap->version >= 2) {
681 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
682 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
683
684 if (skb) {
685 struct ring_info *ringp;
686 dma_addr_t mapping;
687
688 ringp = &ap->skb->rx_mini_skbuff[i];
689 mapping = pci_unmap_addr(ringp,mapping);
690 pci_unmap_page(ap->pdev, mapping,
691 ACE_MINI_BUFSIZE,
692 PCI_DMA_FROMDEVICE);
693
694 ap->rx_mini_ring[i].size = 0;
695 ap->skb->rx_mini_skbuff[i].skb = NULL;
696 dev_kfree_skb(skb);
697 }
698 }
699 }
700
701 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
702 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
703 if (skb) {
704 struct ring_info *ringp;
705 dma_addr_t mapping;
706
707 ringp = &ap->skb->rx_jumbo_skbuff[i];
708 mapping = pci_unmap_addr(ringp, mapping);
709 pci_unmap_page(ap->pdev, mapping,
710 ACE_JUMBO_BUFSIZE,
711 PCI_DMA_FROMDEVICE);
712
713 ap->rx_jumbo_ring[i].size = 0;
714 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
715 dev_kfree_skb(skb);
716 }
717 }
718
719 ace_init_cleanup(dev);
720 free_netdev(dev);
721}
722
723static struct pci_driver acenic_pci_driver = {
724 .name = "acenic",
725 .id_table = acenic_pci_tbl,
726 .probe = acenic_probe_one,
727 .remove = __devexit_p(acenic_remove_one),
728};
729
730static int __init acenic_init(void)
731{
732 return pci_module_init(&acenic_pci_driver);
733}
734
735static void __exit acenic_exit(void)
736{
737 pci_unregister_driver(&acenic_pci_driver);
738}
739
740module_init(acenic_init);
741module_exit(acenic_exit);
742
743static void ace_free_descriptors(struct net_device *dev)
744{
745 struct ace_private *ap = netdev_priv(dev);
746 int size;
747
748 if (ap->rx_std_ring != NULL) {
749 size = (sizeof(struct rx_desc) *
750 (RX_STD_RING_ENTRIES +
751 RX_JUMBO_RING_ENTRIES +
752 RX_MINI_RING_ENTRIES +
753 RX_RETURN_RING_ENTRIES));
754 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
755 ap->rx_ring_base_dma);
756 ap->rx_std_ring = NULL;
757 ap->rx_jumbo_ring = NULL;
758 ap->rx_mini_ring = NULL;
759 ap->rx_return_ring = NULL;
760 }
761 if (ap->evt_ring != NULL) {
762 size = (sizeof(struct event) * EVT_RING_ENTRIES);
763 pci_free_consistent(ap->pdev, size, ap->evt_ring,
764 ap->evt_ring_dma);
765 ap->evt_ring = NULL;
766 }
767 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
768 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
769 pci_free_consistent(ap->pdev, size, ap->tx_ring,
770 ap->tx_ring_dma);
771 }
772 ap->tx_ring = NULL;
773
774 if (ap->evt_prd != NULL) {
775 pci_free_consistent(ap->pdev, sizeof(u32),
776 (void *)ap->evt_prd, ap->evt_prd_dma);
777 ap->evt_prd = NULL;
778 }
779 if (ap->rx_ret_prd != NULL) {
780 pci_free_consistent(ap->pdev, sizeof(u32),
781 (void *)ap->rx_ret_prd,
782 ap->rx_ret_prd_dma);
783 ap->rx_ret_prd = NULL;
784 }
785 if (ap->tx_csm != NULL) {
786 pci_free_consistent(ap->pdev, sizeof(u32),
787 (void *)ap->tx_csm, ap->tx_csm_dma);
788 ap->tx_csm = NULL;
789 }
790}
791
792
793static int ace_allocate_descriptors(struct net_device *dev)
794{
795 struct ace_private *ap = netdev_priv(dev);
796 int size;
797
798 size = (sizeof(struct rx_desc) *
799 (RX_STD_RING_ENTRIES +
800 RX_JUMBO_RING_ENTRIES +
801 RX_MINI_RING_ENTRIES +
802 RX_RETURN_RING_ENTRIES));
803
804 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
805 &ap->rx_ring_base_dma);
806 if (ap->rx_std_ring == NULL)
807 goto fail;
808
809 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
810 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
811 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
812
813 size = (sizeof(struct event) * EVT_RING_ENTRIES);
814
815 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
816
817 if (ap->evt_ring == NULL)
818 goto fail;
819
820 /*
821 * Only allocate a host TX ring for the Tigon II, the Tigon I
822 * has to use PCI registers for this ;-(
823 */
824 if (!ACE_IS_TIGON_I(ap)) {
825 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
826
827 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
828 &ap->tx_ring_dma);
829
830 if (ap->tx_ring == NULL)
831 goto fail;
832 }
833
834 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
835 &ap->evt_prd_dma);
836 if (ap->evt_prd == NULL)
837 goto fail;
838
839 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
840 &ap->rx_ret_prd_dma);
841 if (ap->rx_ret_prd == NULL)
842 goto fail;
843
844 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
845 &ap->tx_csm_dma);
846 if (ap->tx_csm == NULL)
847 goto fail;
848
849 return 0;
850
851fail:
852 /* Clean up. */
853 ace_init_cleanup(dev);
854 return 1;
855}
856
857
858/*
859 * Generic cleanup handling data allocated during init. Used when the
860 * module is unloaded or if an error occurs during initialization
861 */
862static void ace_init_cleanup(struct net_device *dev)
863{
864 struct ace_private *ap;
865
866 ap = netdev_priv(dev);
867
868 ace_free_descriptors(dev);
869
870 if (ap->info)
871 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
872 ap->info, ap->info_dma);
873 if (ap->skb)
874 kfree(ap->skb);
875 if (ap->trace_buf)
876 kfree(ap->trace_buf);
877
878 if (dev->irq)
879 free_irq(dev->irq, dev);
880
881 iounmap(ap->regs);
882}
883
884
885/*
886 * Commands are considered to be slow.
887 */
888static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
889{
890 u32 idx;
891
892 idx = readl(&regs->CmdPrd);
893
894 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
895 idx = (idx + 1) % CMD_RING_ENTRIES;
896
897 writel(idx, &regs->CmdPrd);
898}
899
900
901static int __devinit ace_init(struct net_device *dev)
902{
903 struct ace_private *ap;
904 struct ace_regs __iomem *regs;
905 struct ace_info *info = NULL;
906 struct pci_dev *pdev;
907 unsigned long myjif;
908 u64 tmp_ptr;
909 u32 tig_ver, mac1, mac2, tmp, pci_state;
910 int board_idx, ecode = 0;
911 short i;
912 unsigned char cache_size;
913
914 ap = netdev_priv(dev);
915 regs = ap->regs;
916
917 board_idx = ap->board_idx;
918
919 /*
920 * aman@sgi.com - its useful to do a NIC reset here to
921 * address the `Firmware not running' problem subsequent
922 * to any crashes involving the NIC
923 */
924 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
925 readl(&regs->HostCtrl); /* PCI write posting */
926 udelay(5);
927
928 /*
929 * Don't access any other registers before this point!
930 */
931#ifdef __BIG_ENDIAN
932 /*
933 * This will most likely need BYTE_SWAP once we switch
934 * to using __raw_writel()
935 */
936 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
937 &regs->HostCtrl);
938#else
939 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
940 &regs->HostCtrl);
941#endif
942 readl(&regs->HostCtrl); /* PCI write posting */
943
944 /*
945 * Stop the NIC CPU and clear pending interrupts
946 */
947 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
948 readl(&regs->CpuCtrl); /* PCI write posting */
949 writel(0, &regs->Mb0Lo);
950
951 tig_ver = readl(&regs->HostCtrl) >> 28;
952
953 switch(tig_ver){
954#ifndef CONFIG_ACENIC_OMIT_TIGON_I
955 case 4:
956 case 5:
957 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
958 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
959 tigonFwReleaseFix);
960 writel(0, &regs->LocalCtrl);
961 ap->version = 1;
962 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
963 break;
964#endif
965 case 6:
966 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
967 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
968 tigon2FwReleaseFix);
969 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
970 readl(&regs->CpuBCtrl); /* PCI write posting */
971 /*
972 * The SRAM bank size does _not_ indicate the amount
973 * of memory on the card, it controls the _bank_ size!
974 * Ie. a 1MB AceNIC will have two banks of 512KB.
975 */
976 writel(SRAM_BANK_512K, &regs->LocalCtrl);
977 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
978 ap->version = 2;
979 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
980 break;
981 default:
982 printk(KERN_WARNING " Unsupported Tigon version detected "
983 "(%i)\n", tig_ver);
984 ecode = -ENODEV;
985 goto init_error;
986 }
987
988 /*
989 * ModeStat _must_ be set after the SRAM settings as this change
990 * seems to corrupt the ModeStat and possible other registers.
991 * The SRAM settings survive resets and setting it to the same
992 * value a second time works as well. This is what caused the
993 * `Firmware not running' problem on the Tigon II.
994 */
995#ifdef __BIG_ENDIAN
996 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
997 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
998#else
999 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
1000 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
1001#endif
1002 readl(&regs->ModeStat); /* PCI write posting */
1003
1004 mac1 = 0;
1005 for(i = 0; i < 4; i++) {
1006 mac1 = mac1 << 8;
1007 tmp = read_eeprom_byte(dev, 0x8c+i);
1008 if (tmp < 0) {
1009 ecode = -EIO;
1010 goto init_error;
1011 } else
1012 mac1 |= (tmp & 0xff);
1013 }
1014 mac2 = 0;
1015 for(i = 4; i < 8; i++) {
1016 mac2 = mac2 << 8;
1017 tmp = read_eeprom_byte(dev, 0x8c+i);
1018 if (tmp < 0) {
1019 ecode = -EIO;
1020 goto init_error;
1021 } else
1022 mac2 |= (tmp & 0xff);
1023 }
1024
1025 writel(mac1, &regs->MacAddrHi);
1026 writel(mac2, &regs->MacAddrLo);
1027
1028 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
1029 (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
1030 (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
1031
1032 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1033 dev->dev_addr[1] = mac1 & 0xff;
1034 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1035 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1036 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1037 dev->dev_addr[5] = mac2 & 0xff;
1038
1039 /*
1040 * Looks like this is necessary to deal with on all architectures,
1041 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1042 * Ie. having two NICs in the machine, one will have the cache
1043 * line set at boot time, the other will not.
1044 */
1045 pdev = ap->pdev;
1046 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1047 cache_size <<= 2;
1048 if (cache_size != SMP_CACHE_BYTES) {
1049 printk(KERN_INFO " PCI cache line size set incorrectly "
1050 "(%i bytes) by BIOS/FW, ", cache_size);
1051 if (cache_size > SMP_CACHE_BYTES)
1052 printk("expecting %i\n", SMP_CACHE_BYTES);
1053 else {
1054 printk("correcting to %i\n", SMP_CACHE_BYTES);
1055 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1056 SMP_CACHE_BYTES >> 2);
1057 }
1058 }
1059
1060 pci_state = readl(&regs->PciState);
1061 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1062 "latency: %i clks\n",
1063 (pci_state & PCI_32BIT) ? 32 : 64,
1064 (pci_state & PCI_66MHZ) ? 66 : 33,
1065 ap->pci_latency);
1066
1067 /*
1068 * Set the max DMA transfer size. Seems that for most systems
1069 * the performance is better when no MAX parameter is
1070 * set. However for systems enabling PCI write and invalidate,
1071 * DMA writes must be set to the L1 cache line size to get
1072 * optimal performance.
1073 *
1074 * The default is now to turn the PCI write and invalidate off
1075 * - that is what Alteon does for NT.
1076 */
1077 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1078 if (ap->version >= 2) {
1079 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1080 /*
1081 * Tuning parameters only supported for 8 cards
1082 */
1083 if (board_idx == BOARD_IDX_OVERFLOW ||
1084 dis_pci_mem_inval[board_idx]) {
1085 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1086 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1087 pci_write_config_word(pdev, PCI_COMMAND,
1088 ap->pci_command);
1089 printk(KERN_INFO " Disabling PCI memory "
1090 "write and invalidate\n");
1091 }
1092 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1093 printk(KERN_INFO " PCI memory write & invalidate "
1094 "enabled by BIOS, enabling counter measures\n");
1095
1096 switch(SMP_CACHE_BYTES) {
1097 case 16:
1098 tmp |= DMA_WRITE_MAX_16;
1099 break;
1100 case 32:
1101 tmp |= DMA_WRITE_MAX_32;
1102 break;
1103 case 64:
1104 tmp |= DMA_WRITE_MAX_64;
1105 break;
1106 case 128:
1107 tmp |= DMA_WRITE_MAX_128;
1108 break;
1109 default:
1110 printk(KERN_INFO " Cache line size %i not "
1111 "supported, PCI write and invalidate "
1112 "disabled\n", SMP_CACHE_BYTES);
1113 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1114 pci_write_config_word(pdev, PCI_COMMAND,
1115 ap->pci_command);
1116 }
1117 }
1118 }
1119
1120#ifdef __sparc__
1121 /*
1122 * On this platform, we know what the best dma settings
1123 * are. We use 64-byte maximum bursts, because if we
1124 * burst larger than the cache line size (or even cross
1125 * a 64byte boundary in a single burst) the UltraSparc
1126 * PCI controller will disconnect at 64-byte multiples.
1127 *
1128 * Read-multiple will be properly enabled above, and when
1129 * set will give the PCI controller proper hints about
1130 * prefetching.
1131 */
1132 tmp &= ~DMA_READ_WRITE_MASK;
1133 tmp |= DMA_READ_MAX_64;
1134 tmp |= DMA_WRITE_MAX_64;
1135#endif
1136#ifdef __alpha__
1137 tmp &= ~DMA_READ_WRITE_MASK;
1138 tmp |= DMA_READ_MAX_128;
1139 /*
1140 * All the docs say MUST NOT. Well, I did.
1141 * Nothing terrible happens, if we load wrong size.
1142 * Bit w&i still works better!
1143 */
1144 tmp |= DMA_WRITE_MAX_128;
1145#endif
1146 writel(tmp, &regs->PciState);
1147
1148#if 0
1149 /*
1150 * The Host PCI bus controller driver has to set FBB.
1151 * If all devices on that PCI bus support FBB, then the controller
1152 * can enable FBB support in the Host PCI Bus controller (or on
1153 * the PCI-PCI bridge if that applies).
1154 * -ggg
1155 */
1156 /*
1157 * I have received reports from people having problems when this
1158 * bit is enabled.
1159 */
1160 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1161 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1162 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1163 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1164 }
1165#endif
1166
1167 /*
1168 * Configure DMA attributes.
1169 */
1170 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1171 ap->pci_using_dac = 1;
1172 } else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
1173 ap->pci_using_dac = 0;
1174 } else {
1175 ecode = -ENODEV;
1176 goto init_error;
1177 }
1178
1179 /*
1180 * Initialize the generic info block and the command+event rings
1181 * and the control blocks for the transmit and receive rings
1182 * as they need to be setup once and for all.
1183 */
1184 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1185 &ap->info_dma))) {
1186 ecode = -EAGAIN;
1187 goto init_error;
1188 }
1189 ap->info = info;
1190
1191 /*
1192 * Get the memory for the skb rings.
1193 */
1194 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1195 ecode = -EAGAIN;
1196 goto init_error;
1197 }
1198
1199 ecode = request_irq(pdev->irq, ace_interrupt, SA_SHIRQ,
1200 DRV_NAME, dev);
1201 if (ecode) {
1202 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1203 DRV_NAME, pdev->irq);
1204 goto init_error;
1205 } else
1206 dev->irq = pdev->irq;
1207
1208#ifdef INDEX_DEBUG
1209 spin_lock_init(&ap->debug_lock);
1210 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1211 ap->last_std_rx = 0;
1212 ap->last_mini_rx = 0;
1213#endif
1214
1215 memset(ap->info, 0, sizeof(struct ace_info));
1216 memset(ap->skb, 0, sizeof(struct ace_skb));
1217
1218 ace_load_firmware(dev);
1219 ap->fw_running = 0;
1220
1221 tmp_ptr = ap->info_dma;
1222 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1223 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1224
1225 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1226
1227 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1228 info->evt_ctrl.flags = 0;
1229
1230 *(ap->evt_prd) = 0;
1231 wmb();
1232 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1233 writel(0, &regs->EvtCsm);
1234
1235 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1236 info->cmd_ctrl.flags = 0;
1237 info->cmd_ctrl.max_len = 0;
1238
1239 for (i = 0; i < CMD_RING_ENTRIES; i++)
1240 writel(0, &regs->CmdRng[i]);
1241
1242 writel(0, &regs->CmdPrd);
1243 writel(0, &regs->CmdCsm);
1244
1245 tmp_ptr = ap->info_dma;
1246 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1247 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1248
1249 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1250 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1251 info->rx_std_ctrl.flags =
1252 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1253
1254 memset(ap->rx_std_ring, 0,
1255 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1256
1257 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1258 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1259
1260 ap->rx_std_skbprd = 0;
1261 atomic_set(&ap->cur_rx_bufs, 0);
1262
1263 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1264 (ap->rx_ring_base_dma +
1265 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1266 info->rx_jumbo_ctrl.max_len = 0;
1267 info->rx_jumbo_ctrl.flags =
1268 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1269
1270 memset(ap->rx_jumbo_ring, 0,
1271 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1272
1273 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1274 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1275
1276 ap->rx_jumbo_skbprd = 0;
1277 atomic_set(&ap->cur_jumbo_bufs, 0);
1278
1279 memset(ap->rx_mini_ring, 0,
1280 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1281
1282 if (ap->version >= 2) {
1283 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1284 (ap->rx_ring_base_dma +
1285 (sizeof(struct rx_desc) *
1286 (RX_STD_RING_ENTRIES +
1287 RX_JUMBO_RING_ENTRIES))));
1288 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1289 info->rx_mini_ctrl.flags =
1290 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1291
1292 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1293 ap->rx_mini_ring[i].flags =
1294 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1295 } else {
1296 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1297 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1298 info->rx_mini_ctrl.max_len = 0;
1299 }
1300
1301 ap->rx_mini_skbprd = 0;
1302 atomic_set(&ap->cur_mini_bufs, 0);
1303
1304 set_aceaddr(&info->rx_return_ctrl.rngptr,
1305 (ap->rx_ring_base_dma +
1306 (sizeof(struct rx_desc) *
1307 (RX_STD_RING_ENTRIES +
1308 RX_JUMBO_RING_ENTRIES +
1309 RX_MINI_RING_ENTRIES))));
1310 info->rx_return_ctrl.flags = 0;
1311 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1312
1313 memset(ap->rx_return_ring, 0,
1314 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1315
1316 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1317 *(ap->rx_ret_prd) = 0;
1318
1319 writel(TX_RING_BASE, &regs->WinBase);
1320
1321 if (ACE_IS_TIGON_I(ap)) {
1322 ap->tx_ring = (struct tx_desc *) regs->Window;
1323 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1324 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1325 writel(0, (void __iomem *)ap->tx_ring + i * 4);
1326
1327 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1328 } else {
1329 memset(ap->tx_ring, 0,
1330 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1331
1332 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1333 }
1334
1335 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1336 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1337
1338 /*
1339 * The Tigon I does not like having the TX ring in host memory ;-(
1340 */
1341 if (!ACE_IS_TIGON_I(ap))
1342 tmp |= RCB_FLG_TX_HOST_RING;
1343#if TX_COAL_INTS_ONLY
1344 tmp |= RCB_FLG_COAL_INT_ONLY;
1345#endif
1346 info->tx_ctrl.flags = tmp;
1347
1348 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1349
1350 /*
1351 * Potential item for tuning parameter
1352 */
1353#if 0 /* NO */
1354 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1355 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1356#else
1357 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1358 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1359#endif
1360
1361 writel(0, &regs->MaskInt);
1362 writel(1, &regs->IfIdx);
1363#if 0
1364 /*
1365 * McKinley boxes do not like us fiddling with AssistState
1366 * this early
1367 */
1368 writel(1, &regs->AssistState);
1369#endif
1370
1371 writel(DEF_STAT, &regs->TuneStatTicks);
1372 writel(DEF_TRACE, &regs->TuneTrace);
1373
1374 ace_set_rxtx_parms(dev, 0);
1375
1376 if (board_idx == BOARD_IDX_OVERFLOW) {
1377 printk(KERN_WARNING "%s: more than %i NICs detected, "
1378 "ignoring module parameters!\n",
1379 ap->name, ACE_MAX_MOD_PARMS);
1380 } else if (board_idx >= 0) {
1381 if (tx_coal_tick[board_idx])
1382 writel(tx_coal_tick[board_idx],
1383 &regs->TuneTxCoalTicks);
1384 if (max_tx_desc[board_idx])
1385 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1386
1387 if (rx_coal_tick[board_idx])
1388 writel(rx_coal_tick[board_idx],
1389 &regs->TuneRxCoalTicks);
1390 if (max_rx_desc[board_idx])
1391 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1392
1393 if (trace[board_idx])
1394 writel(trace[board_idx], &regs->TuneTrace);
1395
1396 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1397 writel(tx_ratio[board_idx], &regs->TxBufRat);
1398 }
1399
1400 /*
1401 * Default link parameters
1402 */
1403 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1404 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1405 if(ap->version >= 2)
1406 tmp |= LNK_TX_FLOW_CTL_Y;
1407
1408 /*
1409 * Override link default parameters
1410 */
1411 if ((board_idx >= 0) && link[board_idx]) {
1412 int option = link[board_idx];
1413
1414 tmp = LNK_ENABLE;
1415
1416 if (option & 0x01) {
1417 printk(KERN_INFO "%s: Setting half duplex link\n",
1418 ap->name);
1419 tmp &= ~LNK_FULL_DUPLEX;
1420 }
1421 if (option & 0x02)
1422 tmp &= ~LNK_NEGOTIATE;
1423 if (option & 0x10)
1424 tmp |= LNK_10MB;
1425 if (option & 0x20)
1426 tmp |= LNK_100MB;
1427 if (option & 0x40)
1428 tmp |= LNK_1000MB;
1429 if ((option & 0x70) == 0) {
1430 printk(KERN_WARNING "%s: No media speed specified, "
1431 "forcing auto negotiation\n", ap->name);
1432 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1433 LNK_100MB | LNK_10MB;
1434 }
1435 if ((option & 0x100) == 0)
1436 tmp |= LNK_NEG_FCTL;
1437 else
1438 printk(KERN_INFO "%s: Disabling flow control "
1439 "negotiation\n", ap->name);
1440 if (option & 0x200)
1441 tmp |= LNK_RX_FLOW_CTL_Y;
1442 if ((option & 0x400) && (ap->version >= 2)) {
1443 printk(KERN_INFO "%s: Enabling TX flow control\n",
1444 ap->name);
1445 tmp |= LNK_TX_FLOW_CTL_Y;
1446 }
1447 }
1448
1449 ap->link = tmp;
1450 writel(tmp, &regs->TuneLink);
1451 if (ap->version >= 2)
1452 writel(tmp, &regs->TuneFastLink);
1453
1454 if (ACE_IS_TIGON_I(ap))
1455 writel(tigonFwStartAddr, &regs->Pc);
1456 if (ap->version == 2)
1457 writel(tigon2FwStartAddr, &regs->Pc);
1458
1459 writel(0, &regs->Mb0Lo);
1460
1461 /*
1462 * Set tx_csm before we start receiving interrupts, otherwise
1463 * the interrupt handler might think it is supposed to process
1464 * tx ints before we are up and running, which may cause a null
1465 * pointer access in the int handler.
1466 */
1467 ap->cur_rx = 0;
1468 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1469
1470 wmb();
1471 ace_set_txprd(regs, ap, 0);
1472 writel(0, &regs->RxRetCsm);
1473
1474 /*
1475 * Zero the stats before starting the interface
1476 */
1477 memset(&ap->stats, 0, sizeof(ap->stats));
1478
1479 /*
1480 * Enable DMA engine now.
1481 * If we do this sooner, Mckinley box pukes.
1482 * I assume it's because Tigon II DMA engine wants to check
1483 * *something* even before the CPU is started.
1484 */
1485 writel(1, &regs->AssistState); /* enable DMA */
1486
1487 /*
1488 * Start the NIC CPU
1489 */
1490 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1491 readl(&regs->CpuCtrl);
1492
1493 /*
1494 * Wait for the firmware to spin up - max 3 seconds.
1495 */
1496 myjif = jiffies + 3 * HZ;
1497 while (time_before(jiffies, myjif) && !ap->fw_running)
1498 cpu_relax();
1499
1500 if (!ap->fw_running) {
1501 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1502
1503 ace_dump_trace(ap);
1504 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1505 readl(&regs->CpuCtrl);
1506
1507 /* aman@sgi.com - account for badly behaving firmware/NIC:
1508 * - have observed that the NIC may continue to generate
1509 * interrupts for some reason; attempt to stop it - halt
1510 * second CPU for Tigon II cards, and also clear Mb0
1511 * - if we're a module, we'll fail to load if this was
1512 * the only GbE card in the system => if the kernel does
1513 * see an interrupt from the NIC, code to handle it is
1514 * gone and OOps! - so free_irq also
1515 */
1516 if (ap->version >= 2)
1517 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1518 &regs->CpuBCtrl);
1519 writel(0, &regs->Mb0Lo);
1520 readl(&regs->Mb0Lo);
1521
1522 ecode = -EBUSY;
1523 goto init_error;
1524 }
1525
1526 /*
1527 * We load the ring here as there seem to be no way to tell the
1528 * firmware to wipe the ring without re-initializing it.
1529 */
1530 if (!test_and_set_bit(0, &ap->std_refill_busy))
1531 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1532 else
1533 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1534 ap->name);
1535 if (ap->version >= 2) {
1536 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1537 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1538 else
1539 printk(KERN_ERR "%s: Someone is busy refilling "
1540 "the RX mini ring\n", ap->name);
1541 }
1542 return 0;
1543
1544 init_error:
1545 ace_init_cleanup(dev);
1546 return ecode;
1547}
1548
1549
1550static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1551{
1552 struct ace_private *ap = netdev_priv(dev);
1553 struct ace_regs __iomem *regs = ap->regs;
1554 int board_idx = ap->board_idx;
1555
1556 if (board_idx >= 0) {
1557 if (!jumbo) {
1558 if (!tx_coal_tick[board_idx])
1559 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1560 if (!max_tx_desc[board_idx])
1561 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1562 if (!rx_coal_tick[board_idx])
1563 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1564 if (!max_rx_desc[board_idx])
1565 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1566 if (!tx_ratio[board_idx])
1567 writel(DEF_TX_RATIO, &regs->TxBufRat);
1568 } else {
1569 if (!tx_coal_tick[board_idx])
1570 writel(DEF_JUMBO_TX_COAL,
1571 &regs->TuneTxCoalTicks);
1572 if (!max_tx_desc[board_idx])
1573 writel(DEF_JUMBO_TX_MAX_DESC,
1574 &regs->TuneMaxTxDesc);
1575 if (!rx_coal_tick[board_idx])
1576 writel(DEF_JUMBO_RX_COAL,
1577 &regs->TuneRxCoalTicks);
1578 if (!max_rx_desc[board_idx])
1579 writel(DEF_JUMBO_RX_MAX_DESC,
1580 &regs->TuneMaxRxDesc);
1581 if (!tx_ratio[board_idx])
1582 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1583 }
1584 }
1585}
1586
1587
1588static void ace_watchdog(struct net_device *data)
1589{
1590 struct net_device *dev = data;
1591 struct ace_private *ap = netdev_priv(dev);
1592 struct ace_regs __iomem *regs = ap->regs;
1593
1594 /*
1595 * We haven't received a stats update event for more than 2.5
1596 * seconds and there is data in the transmit queue, thus we
1597 * asume the card is stuck.
1598 */
1599 if (*ap->tx_csm != ap->tx_ret_csm) {
1600 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1601 dev->name, (unsigned int)readl(&regs->HostCtrl));
1602 /* This can happen due to ieee flow control. */
1603 } else {
1604 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1605 dev->name);
1606#if 0
1607 netif_wake_queue(dev);
1608#endif
1609 }
1610}
1611
1612
1613static void ace_tasklet(unsigned long dev)
1614{
1615 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1616 int cur_size;
1617
1618 cur_size = atomic_read(&ap->cur_rx_bufs);
1619 if ((cur_size < RX_LOW_STD_THRES) &&
1620 !test_and_set_bit(0, &ap->std_refill_busy)) {
1621#ifdef DEBUG
1622 printk("refilling buffers (current %i)\n", cur_size);
1623#endif
1624 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1625 }
1626
1627 if (ap->version >= 2) {
1628 cur_size = atomic_read(&ap->cur_mini_bufs);
1629 if ((cur_size < RX_LOW_MINI_THRES) &&
1630 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1631#ifdef DEBUG
1632 printk("refilling mini buffers (current %i)\n",
1633 cur_size);
1634#endif
1635 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1636 }
1637 }
1638
1639 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1640 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1641 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1642#ifdef DEBUG
1643 printk("refilling jumbo buffers (current %i)\n", cur_size);
1644#endif
1645 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1646 }
1647 ap->tasklet_pending = 0;
1648}
1649
1650
1651/*
1652 * Copy the contents of the NIC's trace buffer to kernel memory.
1653 */
1654static void ace_dump_trace(struct ace_private *ap)
1655{
1656#if 0
1657 if (!ap->trace_buf)
1658 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1659 return;
1660#endif
1661}
1662
1663
1664/*
1665 * Load the standard rx ring.
1666 *
1667 * Loading rings is safe without holding the spin lock since this is
1668 * done only before the device is enabled, thus no interrupts are
1669 * generated and by the interrupt handler/tasklet handler.
1670 */
1671static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1672{
1673 struct ace_regs __iomem *regs = ap->regs;
1674 short i, idx;
1675
1676
1677 prefetchw(&ap->cur_rx_bufs);
1678
1679 idx = ap->rx_std_skbprd;
1680
1681 for (i = 0; i < nr_bufs; i++) {
1682 struct sk_buff *skb;
1683 struct rx_desc *rd;
1684 dma_addr_t mapping;
1685
1686 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1687 if (!skb)
1688 break;
1689
1690 skb_reserve(skb, NET_IP_ALIGN);
1691 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1692 offset_in_page(skb->data),
1693 ACE_STD_BUFSIZE,
1694 PCI_DMA_FROMDEVICE);
1695 ap->skb->rx_std_skbuff[idx].skb = skb;
1696 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1697 mapping, mapping);
1698
1699 rd = &ap->rx_std_ring[idx];
1700 set_aceaddr(&rd->addr, mapping);
1701 rd->size = ACE_STD_BUFSIZE;
1702 rd->idx = idx;
1703 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1704 }
1705
1706 if (!i)
1707 goto error_out;
1708
1709 atomic_add(i, &ap->cur_rx_bufs);
1710 ap->rx_std_skbprd = idx;
1711
1712 if (ACE_IS_TIGON_I(ap)) {
1713 struct cmd cmd;
1714 cmd.evt = C_SET_RX_PRD_IDX;
1715 cmd.code = 0;
1716 cmd.idx = ap->rx_std_skbprd;
1717 ace_issue_cmd(regs, &cmd);
1718 } else {
1719 writel(idx, &regs->RxStdPrd);
1720 wmb();
1721 }
1722
1723 out:
1724 clear_bit(0, &ap->std_refill_busy);
1725 return;
1726
1727 error_out:
1728 printk(KERN_INFO "Out of memory when allocating "
1729 "standard receive buffers\n");
1730 goto out;
1731}
1732
1733
1734static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1735{
1736 struct ace_regs __iomem *regs = ap->regs;
1737 short i, idx;
1738
1739 prefetchw(&ap->cur_mini_bufs);
1740
1741 idx = ap->rx_mini_skbprd;
1742 for (i = 0; i < nr_bufs; i++) {
1743 struct sk_buff *skb;
1744 struct rx_desc *rd;
1745 dma_addr_t mapping;
1746
1747 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1748 if (!skb)
1749 break;
1750
1751 skb_reserve(skb, NET_IP_ALIGN);
1752 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1753 offset_in_page(skb->data),
1754 ACE_MINI_BUFSIZE,
1755 PCI_DMA_FROMDEVICE);
1756 ap->skb->rx_mini_skbuff[idx].skb = skb;
1757 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1758 mapping, mapping);
1759
1760 rd = &ap->rx_mini_ring[idx];
1761 set_aceaddr(&rd->addr, mapping);
1762 rd->size = ACE_MINI_BUFSIZE;
1763 rd->idx = idx;
1764 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1765 }
1766
1767 if (!i)
1768 goto error_out;
1769
1770 atomic_add(i, &ap->cur_mini_bufs);
1771
1772 ap->rx_mini_skbprd = idx;
1773
1774 writel(idx, &regs->RxMiniPrd);
1775 wmb();
1776
1777 out:
1778 clear_bit(0, &ap->mini_refill_busy);
1779 return;
1780 error_out:
1781 printk(KERN_INFO "Out of memory when allocating "
1782 "mini receive buffers\n");
1783 goto out;
1784}
1785
1786
1787/*
1788 * Load the jumbo rx ring, this may happen at any time if the MTU
1789 * is changed to a value > 1500.
1790 */
1791static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1792{
1793 struct ace_regs __iomem *regs = ap->regs;
1794 short i, idx;
1795
1796 idx = ap->rx_jumbo_skbprd;
1797
1798 for (i = 0; i < nr_bufs; i++) {
1799 struct sk_buff *skb;
1800 struct rx_desc *rd;
1801 dma_addr_t mapping;
1802
1803 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1804 if (!skb)
1805 break;
1806
1807 skb_reserve(skb, NET_IP_ALIGN);
1808 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1809 offset_in_page(skb->data),
1810 ACE_JUMBO_BUFSIZE,
1811 PCI_DMA_FROMDEVICE);
1812 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1813 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1814 mapping, mapping);
1815
1816 rd = &ap->rx_jumbo_ring[idx];
1817 set_aceaddr(&rd->addr, mapping);
1818 rd->size = ACE_JUMBO_BUFSIZE;
1819 rd->idx = idx;
1820 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1821 }
1822
1823 if (!i)
1824 goto error_out;
1825
1826 atomic_add(i, &ap->cur_jumbo_bufs);
1827 ap->rx_jumbo_skbprd = idx;
1828
1829 if (ACE_IS_TIGON_I(ap)) {
1830 struct cmd cmd;
1831 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1832 cmd.code = 0;
1833 cmd.idx = ap->rx_jumbo_skbprd;
1834 ace_issue_cmd(regs, &cmd);
1835 } else {
1836 writel(idx, &regs->RxJumboPrd);
1837 wmb();
1838 }
1839
1840 out:
1841 clear_bit(0, &ap->jumbo_refill_busy);
1842 return;
1843 error_out:
1844 if (net_ratelimit())
1845 printk(KERN_INFO "Out of memory when allocating "
1846 "jumbo receive buffers\n");
1847 goto out;
1848}
1849
1850
1851/*
1852 * All events are considered to be slow (RX/TX ints do not generate
1853 * events) and are handled here, outside the main interrupt handler,
1854 * to reduce the size of the handler.
1855 */
1856static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1857{
1858 struct ace_private *ap;
1859
1860 ap = netdev_priv(dev);
1861
1862 while (evtcsm != evtprd) {
1863 switch (ap->evt_ring[evtcsm].evt) {
1864 case E_FW_RUNNING:
1865 printk(KERN_INFO "%s: Firmware up and running\n",
1866 ap->name);
1867 ap->fw_running = 1;
1868 wmb();
1869 break;
1870 case E_STATS_UPDATED:
1871 break;
1872 case E_LNK_STATE:
1873 {
1874 u16 code = ap->evt_ring[evtcsm].code;
1875 switch (code) {
1876 case E_C_LINK_UP:
1877 {
1878 u32 state = readl(&ap->regs->GigLnkState);
1879 printk(KERN_WARNING "%s: Optical link UP "
1880 "(%s Duplex, Flow Control: %s%s)\n",
1881 ap->name,
1882 state & LNK_FULL_DUPLEX ? "Full":"Half",
1883 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1884 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1885 break;
1886 }
1887 case E_C_LINK_DOWN:
1888 printk(KERN_WARNING "%s: Optical link DOWN\n",
1889 ap->name);
1890 break;
1891 case E_C_LINK_10_100:
1892 printk(KERN_WARNING "%s: 10/100BaseT link "
1893 "UP\n", ap->name);
1894 break;
1895 default:
1896 printk(KERN_ERR "%s: Unknown optical link "
1897 "state %02x\n", ap->name, code);
1898 }
1899 break;
1900 }
1901 case E_ERROR:
1902 switch(ap->evt_ring[evtcsm].code) {
1903 case E_C_ERR_INVAL_CMD:
1904 printk(KERN_ERR "%s: invalid command error\n",
1905 ap->name);
1906 break;
1907 case E_C_ERR_UNIMP_CMD:
1908 printk(KERN_ERR "%s: unimplemented command "
1909 "error\n", ap->name);
1910 break;
1911 case E_C_ERR_BAD_CFG:
1912 printk(KERN_ERR "%s: bad config error\n",
1913 ap->name);
1914 break;
1915 default:
1916 printk(KERN_ERR "%s: unknown error %02x\n",
1917 ap->name, ap->evt_ring[evtcsm].code);
1918 }
1919 break;
1920 case E_RESET_JUMBO_RNG:
1921 {
1922 int i;
1923 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1924 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1925 ap->rx_jumbo_ring[i].size = 0;
1926 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1927 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1928 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1929 }
1930 }
1931
1932 if (ACE_IS_TIGON_I(ap)) {
1933 struct cmd cmd;
1934 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1935 cmd.code = 0;
1936 cmd.idx = 0;
1937 ace_issue_cmd(ap->regs, &cmd);
1938 } else {
1939 writel(0, &((ap->regs)->RxJumboPrd));
1940 wmb();
1941 }
1942
1943 ap->jumbo = 0;
1944 ap->rx_jumbo_skbprd = 0;
1945 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1946 ap->name);
1947 clear_bit(0, &ap->jumbo_refill_busy);
1948 break;
1949 }
1950 default:
1951 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1952 ap->name, ap->evt_ring[evtcsm].evt);
1953 }
1954 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1955 }
1956
1957 return evtcsm;
1958}
1959
1960
1961static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1962{
1963 struct ace_private *ap = netdev_priv(dev);
1964 u32 idx;
1965 int mini_count = 0, std_count = 0;
1966
1967 idx = rxretcsm;
1968
1969 prefetchw(&ap->cur_rx_bufs);
1970 prefetchw(&ap->cur_mini_bufs);
1971
1972 while (idx != rxretprd) {
1973 struct ring_info *rip;
1974 struct sk_buff *skb;
1975 struct rx_desc *rxdesc, *retdesc;
1976 u32 skbidx;
1977 int bd_flags, desc_type, mapsize;
1978 u16 csum;
1979
1980
1981 /* make sure the rx descriptor isn't read before rxretprd */
1982 if (idx == rxretcsm)
1983 rmb();
1984
1985 retdesc = &ap->rx_return_ring[idx];
1986 skbidx = retdesc->idx;
1987 bd_flags = retdesc->flags;
1988 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1989
1990 switch(desc_type) {
1991 /*
1992 * Normal frames do not have any flags set
1993 *
1994 * Mini and normal frames arrive frequently,
1995 * so use a local counter to avoid doing
1996 * atomic operations for each packet arriving.
1997 */
1998 case 0:
1999 rip = &ap->skb->rx_std_skbuff[skbidx];
2000 mapsize = ACE_STD_BUFSIZE;
2001 rxdesc = &ap->rx_std_ring[skbidx];
2002 std_count++;
2003 break;
2004 case BD_FLG_JUMBO:
2005 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
2006 mapsize = ACE_JUMBO_BUFSIZE;
2007 rxdesc = &ap->rx_jumbo_ring[skbidx];
2008 atomic_dec(&ap->cur_jumbo_bufs);
2009 break;
2010 case BD_FLG_MINI:
2011 rip = &ap->skb->rx_mini_skbuff[skbidx];
2012 mapsize = ACE_MINI_BUFSIZE;
2013 rxdesc = &ap->rx_mini_ring[skbidx];
2014 mini_count++;
2015 break;
2016 default:
2017 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2018 "returned by NIC\n", dev->name,
2019 retdesc->flags);
2020 goto error;
2021 }
2022
2023 skb = rip->skb;
2024 rip->skb = NULL;
2025 pci_unmap_page(ap->pdev,
2026 pci_unmap_addr(rip, mapping),
2027 mapsize,
2028 PCI_DMA_FROMDEVICE);
2029 skb_put(skb, retdesc->size);
2030
2031 /*
2032 * Fly baby, fly!
2033 */
2034 csum = retdesc->tcp_udp_csum;
2035
2036 skb->dev = dev;
2037 skb->protocol = eth_type_trans(skb, dev);
2038
2039 /*
2040 * Instead of forcing the poor tigon mips cpu to calculate
2041 * pseudo hdr checksum, we do this ourselves.
2042 */
2043 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2044 skb->csum = htons(csum);
2045 skb->ip_summed = CHECKSUM_HW;
2046 } else {
2047 skb->ip_summed = CHECKSUM_NONE;
2048 }
2049
2050 /* send it up */
2051#if ACENIC_DO_VLAN
2052 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2053 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2054 } else
2055#endif
2056 netif_rx(skb);
2057
2058 dev->last_rx = jiffies;
2059 ap->stats.rx_packets++;
2060 ap->stats.rx_bytes += retdesc->size;
2061
2062 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2063 }
2064
2065 atomic_sub(std_count, &ap->cur_rx_bufs);
2066 if (!ACE_IS_TIGON_I(ap))
2067 atomic_sub(mini_count, &ap->cur_mini_bufs);
2068
2069 out:
2070 /*
2071 * According to the documentation RxRetCsm is obsolete with
2072 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2073 */
2074 if (ACE_IS_TIGON_I(ap)) {
2075 writel(idx, &ap->regs->RxRetCsm);
2076 }
2077 ap->cur_rx = idx;
2078
2079 return;
2080 error:
2081 idx = rxretprd;
2082 goto out;
2083}
2084
2085
2086static inline void ace_tx_int(struct net_device *dev,
2087 u32 txcsm, u32 idx)
2088{
2089 struct ace_private *ap = netdev_priv(dev);
2090
2091 do {
2092 struct sk_buff *skb;
2093 dma_addr_t mapping;
2094 struct tx_ring_info *info;
2095
2096 info = ap->skb->tx_skbuff + idx;
2097 skb = info->skb;
2098 mapping = pci_unmap_addr(info, mapping);
2099
2100 if (mapping) {
2101 pci_unmap_page(ap->pdev, mapping,
2102 pci_unmap_len(info, maplen),
2103 PCI_DMA_TODEVICE);
2104 pci_unmap_addr_set(info, mapping, 0);
2105 }
2106
2107 if (skb) {
2108 ap->stats.tx_packets++;
2109 ap->stats.tx_bytes += skb->len;
2110 dev_kfree_skb_irq(skb);
2111 info->skb = NULL;
2112 }
2113
2114 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2115 } while (idx != txcsm);
2116
2117 if (netif_queue_stopped(dev))
2118 netif_wake_queue(dev);
2119
2120 wmb();
2121 ap->tx_ret_csm = txcsm;
2122
2123 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2124 *
2125 * We could try to make it before. In this case we would get
2126 * the following race condition: hard_start_xmit on other cpu
2127 * enters after we advanced tx_ret_csm and fills space,
2128 * which we have just freed, so that we make illegal device wakeup.
2129 * There is no good way to workaround this (at entry
2130 * to ace_start_xmit detects this condition and prevents
2131 * ring corruption, but it is not a good workaround.)
2132 *
2133 * When tx_ret_csm is advanced after, we wake up device _only_
2134 * if we really have some space in ring (though the core doing
2135 * hard_start_xmit can see full ring for some period and has to
2136 * synchronize.) Superb.
2137 * BUT! We get another subtle race condition. hard_start_xmit
2138 * may think that ring is full between wakeup and advancing
2139 * tx_ret_csm and will stop device instantly! It is not so bad.
2140 * We are guaranteed that there is something in ring, so that
2141 * the next irq will resume transmission. To speedup this we could
2142 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2143 * (see ace_start_xmit).
2144 *
2145 * Well, this dilemma exists in all lock-free devices.
2146 * We, following scheme used in drivers by Donald Becker,
2147 * select the least dangerous.
2148 * --ANK
2149 */
2150}
2151
2152
2153static irqreturn_t ace_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2154{
2155 struct net_device *dev = (struct net_device *)dev_id;
2156 struct ace_private *ap = netdev_priv(dev);
2157 struct ace_regs __iomem *regs = ap->regs;
2158 u32 idx;
2159 u32 txcsm, rxretcsm, rxretprd;
2160 u32 evtcsm, evtprd;
2161
2162 /*
2163 * In case of PCI shared interrupts or spurious interrupts,
2164 * we want to make sure it is actually our interrupt before
2165 * spending any time in here.
2166 */
2167 if (!(readl(&regs->HostCtrl) & IN_INT))
2168 return IRQ_NONE;
2169
2170 /*
2171 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2172 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2173 * writel(0, &regs->Mb0Lo).
2174 *
2175 * "IRQ avoidance" recommended in docs applies to IRQs served
2176 * threads and it is wrong even for that case.
2177 */
2178 writel(0, &regs->Mb0Lo);
2179 readl(&regs->Mb0Lo);
2180
2181 /*
2182 * There is no conflict between transmit handling in
2183 * start_xmit and receive processing, thus there is no reason
2184 * to take a spin lock for RX handling. Wait until we start
2185 * working on the other stuff - hey we don't need a spin lock
2186 * anymore.
2187 */
2188 rxretprd = *ap->rx_ret_prd;
2189 rxretcsm = ap->cur_rx;
2190
2191 if (rxretprd != rxretcsm)
2192 ace_rx_int(dev, rxretprd, rxretcsm);
2193
2194 txcsm = *ap->tx_csm;
2195 idx = ap->tx_ret_csm;
2196
2197 if (txcsm != idx) {
2198 /*
2199 * If each skb takes only one descriptor this check degenerates
2200 * to identity, because new space has just been opened.
2201 * But if skbs are fragmented we must check that this index
2202 * update releases enough of space, otherwise we just
2203 * wait for device to make more work.
2204 */
2205 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2206 ace_tx_int(dev, txcsm, idx);
2207 }
2208
2209 evtcsm = readl(&regs->EvtCsm);
2210 evtprd = *ap->evt_prd;
2211
2212 if (evtcsm != evtprd) {
2213 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2214 writel(evtcsm, &regs->EvtCsm);
2215 }
2216
2217 /*
2218 * This has to go last in the interrupt handler and run with
2219 * the spin lock released ... what lock?
2220 */
2221 if (netif_running(dev)) {
2222 int cur_size;
2223 int run_tasklet = 0;
2224
2225 cur_size = atomic_read(&ap->cur_rx_bufs);
2226 if (cur_size < RX_LOW_STD_THRES) {
2227 if ((cur_size < RX_PANIC_STD_THRES) &&
2228 !test_and_set_bit(0, &ap->std_refill_busy)) {
2229#ifdef DEBUG
2230 printk("low on std buffers %i\n", cur_size);
2231#endif
2232 ace_load_std_rx_ring(ap,
2233 RX_RING_SIZE - cur_size);
2234 } else
2235 run_tasklet = 1;
2236 }
2237
2238 if (!ACE_IS_TIGON_I(ap)) {
2239 cur_size = atomic_read(&ap->cur_mini_bufs);
2240 if (cur_size < RX_LOW_MINI_THRES) {
2241 if ((cur_size < RX_PANIC_MINI_THRES) &&
2242 !test_and_set_bit(0,
2243 &ap->mini_refill_busy)) {
2244#ifdef DEBUG
2245 printk("low on mini buffers %i\n",
2246 cur_size);
2247#endif
2248 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2249 } else
2250 run_tasklet = 1;
2251 }
2252 }
2253
2254 if (ap->jumbo) {
2255 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2256 if (cur_size < RX_LOW_JUMBO_THRES) {
2257 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2258 !test_and_set_bit(0,
2259 &ap->jumbo_refill_busy)){
2260#ifdef DEBUG
2261 printk("low on jumbo buffers %i\n",
2262 cur_size);
2263#endif
2264 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2265 } else
2266 run_tasklet = 1;
2267 }
2268 }
2269 if (run_tasklet && !ap->tasklet_pending) {
2270 ap->tasklet_pending = 1;
2271 tasklet_schedule(&ap->ace_tasklet);
2272 }
2273 }
2274
2275 return IRQ_HANDLED;
2276}
2277
2278
2279#if ACENIC_DO_VLAN
2280static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2281{
2282 struct ace_private *ap = netdev_priv(dev);
2283 unsigned long flags;
2284
2285 local_irq_save(flags);
2286 ace_mask_irq(dev);
2287
2288 ap->vlgrp = grp;
2289
2290 ace_unmask_irq(dev);
2291 local_irq_restore(flags);
2292}
2293
2294
2295static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2296{
2297 struct ace_private *ap = netdev_priv(dev);
2298 unsigned long flags;
2299
2300 local_irq_save(flags);
2301 ace_mask_irq(dev);
2302
2303 if (ap->vlgrp)
2304 ap->vlgrp->vlan_devices[vid] = NULL;
2305
2306 ace_unmask_irq(dev);
2307 local_irq_restore(flags);
2308}
2309#endif /* ACENIC_DO_VLAN */
2310
2311
2312static int ace_open(struct net_device *dev)
2313{
2314 struct ace_private *ap = netdev_priv(dev);
2315 struct ace_regs __iomem *regs = ap->regs;
2316 struct cmd cmd;
2317
2318 if (!(ap->fw_running)) {
2319 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2320 return -EBUSY;
2321 }
2322
2323 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2324
2325 cmd.evt = C_CLEAR_STATS;
2326 cmd.code = 0;
2327 cmd.idx = 0;
2328 ace_issue_cmd(regs, &cmd);
2329
2330 cmd.evt = C_HOST_STATE;
2331 cmd.code = C_C_STACK_UP;
2332 cmd.idx = 0;
2333 ace_issue_cmd(regs, &cmd);
2334
2335 if (ap->jumbo &&
2336 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2337 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2338
2339 if (dev->flags & IFF_PROMISC) {
2340 cmd.evt = C_SET_PROMISC_MODE;
2341 cmd.code = C_C_PROMISC_ENABLE;
2342 cmd.idx = 0;
2343 ace_issue_cmd(regs, &cmd);
2344
2345 ap->promisc = 1;
2346 }else
2347 ap->promisc = 0;
2348 ap->mcast_all = 0;
2349
2350#if 0
2351 cmd.evt = C_LNK_NEGOTIATION;
2352 cmd.code = 0;
2353 cmd.idx = 0;
2354 ace_issue_cmd(regs, &cmd);
2355#endif
2356
2357 netif_start_queue(dev);
2358
2359 /*
2360 * Setup the bottom half rx ring refill handler
2361 */
2362 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2363 return 0;
2364}
2365
2366
2367static int ace_close(struct net_device *dev)
2368{
2369 struct ace_private *ap = netdev_priv(dev);
2370 struct ace_regs __iomem *regs = ap->regs;
2371 struct cmd cmd;
2372 unsigned long flags;
2373 short i;
2374
2375 /*
2376 * Without (or before) releasing irq and stopping hardware, this
2377 * is an absolute non-sense, by the way. It will be reset instantly
2378 * by the first irq.
2379 */
2380 netif_stop_queue(dev);
2381
2382
2383 if (ap->promisc) {
2384 cmd.evt = C_SET_PROMISC_MODE;
2385 cmd.code = C_C_PROMISC_DISABLE;
2386 cmd.idx = 0;
2387 ace_issue_cmd(regs, &cmd);
2388 ap->promisc = 0;
2389 }
2390
2391 cmd.evt = C_HOST_STATE;
2392 cmd.code = C_C_STACK_DOWN;
2393 cmd.idx = 0;
2394 ace_issue_cmd(regs, &cmd);
2395
2396 tasklet_kill(&ap->ace_tasklet);
2397
2398 /*
2399 * Make sure one CPU is not processing packets while
2400 * buffers are being released by another.
2401 */
2402
2403 local_irq_save(flags);
2404 ace_mask_irq(dev);
2405
2406 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2407 struct sk_buff *skb;
2408 dma_addr_t mapping;
2409 struct tx_ring_info *info;
2410
2411 info = ap->skb->tx_skbuff + i;
2412 skb = info->skb;
2413 mapping = pci_unmap_addr(info, mapping);
2414
2415 if (mapping) {
2416 if (ACE_IS_TIGON_I(ap)) {
2417 struct tx_desc __iomem *tx
2418 = (struct tx_desc __iomem *) &ap->tx_ring[i];
2419 writel(0, &tx->addr.addrhi);
2420 writel(0, &tx->addr.addrlo);
2421 writel(0, &tx->flagsize);
2422 } else
2423 memset(ap->tx_ring + i, 0,
2424 sizeof(struct tx_desc));
2425 pci_unmap_page(ap->pdev, mapping,
2426 pci_unmap_len(info, maplen),
2427 PCI_DMA_TODEVICE);
2428 pci_unmap_addr_set(info, mapping, 0);
2429 }
2430 if (skb) {
2431 dev_kfree_skb(skb);
2432 info->skb = NULL;
2433 }
2434 }
2435
2436 if (ap->jumbo) {
2437 cmd.evt = C_RESET_JUMBO_RNG;
2438 cmd.code = 0;
2439 cmd.idx = 0;
2440 ace_issue_cmd(regs, &cmd);
2441 }
2442
2443 ace_unmask_irq(dev);
2444 local_irq_restore(flags);
2445
2446 return 0;
2447}
2448
2449
2450static inline dma_addr_t
2451ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2452 struct sk_buff *tail, u32 idx)
2453{
2454 dma_addr_t mapping;
2455 struct tx_ring_info *info;
2456
2457 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2458 offset_in_page(skb->data),
2459 skb->len, PCI_DMA_TODEVICE);
2460
2461 info = ap->skb->tx_skbuff + idx;
2462 info->skb = tail;
2463 pci_unmap_addr_set(info, mapping, mapping);
2464 pci_unmap_len_set(info, maplen, skb->len);
2465 return mapping;
2466}
2467
2468
2469static inline void
2470ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2471 u32 flagsize, u32 vlan_tag)
2472{
2473#if !USE_TX_COAL_NOW
2474 flagsize &= ~BD_FLG_COAL_NOW;
2475#endif
2476
2477 if (ACE_IS_TIGON_I(ap)) {
2478 struct tx_desc __iomem *io = (struct tx_desc __iomem *) desc;
2479 writel(addr >> 32, &io->addr.addrhi);
2480 writel(addr & 0xffffffff, &io->addr.addrlo);
2481 writel(flagsize, &io->flagsize);
2482#if ACENIC_DO_VLAN
2483 writel(vlan_tag, &io->vlanres);
2484#endif
2485 } else {
2486 desc->addr.addrhi = addr >> 32;
2487 desc->addr.addrlo = addr;
2488 desc->flagsize = flagsize;
2489#if ACENIC_DO_VLAN
2490 desc->vlanres = vlan_tag;
2491#endif
2492 }
2493}
2494
2495
2496static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2497{
2498 struct ace_private *ap = netdev_priv(dev);
2499 struct ace_regs __iomem *regs = ap->regs;
2500 struct tx_desc *desc;
2501 u32 idx, flagsize;
2502 unsigned long maxjiff = jiffies + 3*HZ;
2503
2504restart:
2505 idx = ap->tx_prd;
2506
2507 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2508 goto overflow;
2509
2510 if (!skb_shinfo(skb)->nr_frags) {
2511 dma_addr_t mapping;
2512 u32 vlan_tag = 0;
2513
2514 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2515 flagsize = (skb->len << 16) | (BD_FLG_END);
2516 if (skb->ip_summed == CHECKSUM_HW)
2517 flagsize |= BD_FLG_TCP_UDP_SUM;
2518#if ACENIC_DO_VLAN
2519 if (vlan_tx_tag_present(skb)) {
2520 flagsize |= BD_FLG_VLAN_TAG;
2521 vlan_tag = vlan_tx_tag_get(skb);
2522 }
2523#endif
2524 desc = ap->tx_ring + idx;
2525 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2526
2527 /* Look at ace_tx_int for explanations. */
2528 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2529 flagsize |= BD_FLG_COAL_NOW;
2530
2531 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2532 } else {
2533 dma_addr_t mapping;
2534 u32 vlan_tag = 0;
2535 int i, len = 0;
2536
2537 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2538 flagsize = (skb_headlen(skb) << 16);
2539 if (skb->ip_summed == CHECKSUM_HW)
2540 flagsize |= BD_FLG_TCP_UDP_SUM;
2541#if ACENIC_DO_VLAN
2542 if (vlan_tx_tag_present(skb)) {
2543 flagsize |= BD_FLG_VLAN_TAG;
2544 vlan_tag = vlan_tx_tag_get(skb);
2545 }
2546#endif
2547
2548 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2549
2550 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2551
2552 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2553 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2554 struct tx_ring_info *info;
2555
2556 len += frag->size;
2557 info = ap->skb->tx_skbuff + idx;
2558 desc = ap->tx_ring + idx;
2559
2560 mapping = pci_map_page(ap->pdev, frag->page,
2561 frag->page_offset, frag->size,
2562 PCI_DMA_TODEVICE);
2563
2564 flagsize = (frag->size << 16);
2565 if (skb->ip_summed == CHECKSUM_HW)
2566 flagsize |= BD_FLG_TCP_UDP_SUM;
2567 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2568
2569 if (i == skb_shinfo(skb)->nr_frags - 1) {
2570 flagsize |= BD_FLG_END;
2571 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2572 flagsize |= BD_FLG_COAL_NOW;
2573
2574 /*
2575 * Only the last fragment frees
2576 * the skb!
2577 */
2578 info->skb = skb;
2579 } else {
2580 info->skb = NULL;
2581 }
2582 pci_unmap_addr_set(info, mapping, mapping);
2583 pci_unmap_len_set(info, maplen, frag->size);
2584 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2585 }
2586 }
2587
2588 wmb();
2589 ap->tx_prd = idx;
2590 ace_set_txprd(regs, ap, idx);
2591
2592 if (flagsize & BD_FLG_COAL_NOW) {
2593 netif_stop_queue(dev);
2594
2595 /*
2596 * A TX-descriptor producer (an IRQ) might have gotten
2597 * inbetween, making the ring free again. Since xmit is
2598 * serialized, this is the only situation we have to
2599 * re-test.
2600 */
2601 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2602 netif_wake_queue(dev);
2603 }
2604
2605 dev->trans_start = jiffies;
2606 return NETDEV_TX_OK;
2607
2608overflow:
2609 /*
2610 * This race condition is unavoidable with lock-free drivers.
2611 * We wake up the queue _before_ tx_prd is advanced, so that we can
2612 * enter hard_start_xmit too early, while tx ring still looks closed.
2613 * This happens ~1-4 times per 100000 packets, so that we can allow
2614 * to loop syncing to other CPU. Probably, we need an additional
2615 * wmb() in ace_tx_intr as well.
2616 *
2617 * Note that this race is relieved by reserving one more entry
2618 * in tx ring than it is necessary (see original non-SG driver).
2619 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2620 * is already overkill.
2621 *
2622 * Alternative is to return with 1 not throttling queue. In this
2623 * case loop becomes longer, no more useful effects.
2624 */
2625 if (time_before(jiffies, maxjiff)) {
2626 barrier();
2627 cpu_relax();
2628 goto restart;
2629 }
2630
2631 /* The ring is stuck full. */
2632 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2633 return NETDEV_TX_BUSY;
2634}
2635
2636
2637static int ace_change_mtu(struct net_device *dev, int new_mtu)
2638{
2639 struct ace_private *ap = netdev_priv(dev);
2640 struct ace_regs __iomem *regs = ap->regs;
2641
2642 if (new_mtu > ACE_JUMBO_MTU)
2643 return -EINVAL;
2644
2645 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2646 dev->mtu = new_mtu;
2647
2648 if (new_mtu > ACE_STD_MTU) {
2649 if (!(ap->jumbo)) {
2650 printk(KERN_INFO "%s: Enabling Jumbo frame "
2651 "support\n", dev->name);
2652 ap->jumbo = 1;
2653 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2654 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2655 ace_set_rxtx_parms(dev, 1);
2656 }
2657 } else {
2658 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2659 ace_sync_irq(dev->irq);
2660 ace_set_rxtx_parms(dev, 0);
2661 if (ap->jumbo) {
2662 struct cmd cmd;
2663
2664 cmd.evt = C_RESET_JUMBO_RNG;
2665 cmd.code = 0;
2666 cmd.idx = 0;
2667 ace_issue_cmd(regs, &cmd);
2668 }
2669 }
2670
2671 return 0;
2672}
2673
2674static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2675{
2676 struct ace_private *ap = netdev_priv(dev);
2677 struct ace_regs __iomem *regs = ap->regs;
2678 u32 link;
2679
2680 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2681 ecmd->supported =
2682 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2683 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2684 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2685 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2686
2687 ecmd->port = PORT_FIBRE;
2688 ecmd->transceiver = XCVR_INTERNAL;
2689
2690 link = readl(&regs->GigLnkState);
2691 if (link & LNK_1000MB)
2692 ecmd->speed = SPEED_1000;
2693 else {
2694 link = readl(&regs->FastLnkState);
2695 if (link & LNK_100MB)
2696 ecmd->speed = SPEED_100;
2697 else if (link & LNK_10MB)
2698 ecmd->speed = SPEED_10;
2699 else
2700 ecmd->speed = 0;
2701 }
2702 if (link & LNK_FULL_DUPLEX)
2703 ecmd->duplex = DUPLEX_FULL;
2704 else
2705 ecmd->duplex = DUPLEX_HALF;
2706
2707 if (link & LNK_NEGOTIATE)
2708 ecmd->autoneg = AUTONEG_ENABLE;
2709 else
2710 ecmd->autoneg = AUTONEG_DISABLE;
2711
2712#if 0
2713 /*
2714 * Current struct ethtool_cmd is insufficient
2715 */
2716 ecmd->trace = readl(&regs->TuneTrace);
2717
2718 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2719 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2720#endif
2721 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2722 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2723
2724 return 0;
2725}
2726
2727static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2728{
2729 struct ace_private *ap = netdev_priv(dev);
2730 struct ace_regs __iomem *regs = ap->regs;
2731 u32 link, speed;
2732
2733 link = readl(&regs->GigLnkState);
2734 if (link & LNK_1000MB)
2735 speed = SPEED_1000;
2736 else {
2737 link = readl(&regs->FastLnkState);
2738 if (link & LNK_100MB)
2739 speed = SPEED_100;
2740 else if (link & LNK_10MB)
2741 speed = SPEED_10;
2742 else
2743 speed = SPEED_100;
2744 }
2745
2746 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2747 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2748 if (!ACE_IS_TIGON_I(ap))
2749 link |= LNK_TX_FLOW_CTL_Y;
2750 if (ecmd->autoneg == AUTONEG_ENABLE)
2751 link |= LNK_NEGOTIATE;
2752 if (ecmd->speed != speed) {
2753 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2754 switch (speed) {
2755 case SPEED_1000:
2756 link |= LNK_1000MB;
2757 break;
2758 case SPEED_100:
2759 link |= LNK_100MB;
2760 break;
2761 case SPEED_10:
2762 link |= LNK_10MB;
2763 break;
2764 }
2765 }
2766
2767 if (ecmd->duplex == DUPLEX_FULL)
2768 link |= LNK_FULL_DUPLEX;
2769
2770 if (link != ap->link) {
2771 struct cmd cmd;
2772 printk(KERN_INFO "%s: Renegotiating link state\n",
2773 dev->name);
2774
2775 ap->link = link;
2776 writel(link, &regs->TuneLink);
2777 if (!ACE_IS_TIGON_I(ap))
2778 writel(link, &regs->TuneFastLink);
2779 wmb();
2780
2781 cmd.evt = C_LNK_NEGOTIATION;
2782 cmd.code = 0;
2783 cmd.idx = 0;
2784 ace_issue_cmd(regs, &cmd);
2785 }
2786 return 0;
2787}
2788
2789static void ace_get_drvinfo(struct net_device *dev,
2790 struct ethtool_drvinfo *info)
2791{
2792 struct ace_private *ap = netdev_priv(dev);
2793
2794 strlcpy(info->driver, "acenic", sizeof(info->driver));
2795 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2796 tigonFwReleaseMajor, tigonFwReleaseMinor,
2797 tigonFwReleaseFix);
2798
2799 if (ap->pdev)
2800 strlcpy(info->bus_info, pci_name(ap->pdev),
2801 sizeof(info->bus_info));
2802
2803}
2804
2805/*
2806 * Set the hardware MAC address.
2807 */
2808static int ace_set_mac_addr(struct net_device *dev, void *p)
2809{
2810 struct ace_private *ap = netdev_priv(dev);
2811 struct ace_regs __iomem *regs = ap->regs;
2812 struct sockaddr *addr=p;
2813 u8 *da;
2814 struct cmd cmd;
2815
2816 if(netif_running(dev))
2817 return -EBUSY;
2818
2819 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2820
2821 da = (u8 *)dev->dev_addr;
2822
2823 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2824 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2825 &regs->MacAddrLo);
2826
2827 cmd.evt = C_SET_MAC_ADDR;
2828 cmd.code = 0;
2829 cmd.idx = 0;
2830 ace_issue_cmd(regs, &cmd);
2831
2832 return 0;
2833}
2834
2835
2836static void ace_set_multicast_list(struct net_device *dev)
2837{
2838 struct ace_private *ap = netdev_priv(dev);
2839 struct ace_regs __iomem *regs = ap->regs;
2840 struct cmd cmd;
2841
2842 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2843 cmd.evt = C_SET_MULTICAST_MODE;
2844 cmd.code = C_C_MCAST_ENABLE;
2845 cmd.idx = 0;
2846 ace_issue_cmd(regs, &cmd);
2847 ap->mcast_all = 1;
2848 } else if (ap->mcast_all) {
2849 cmd.evt = C_SET_MULTICAST_MODE;
2850 cmd.code = C_C_MCAST_DISABLE;
2851 cmd.idx = 0;
2852 ace_issue_cmd(regs, &cmd);
2853 ap->mcast_all = 0;
2854 }
2855
2856 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2857 cmd.evt = C_SET_PROMISC_MODE;
2858 cmd.code = C_C_PROMISC_ENABLE;
2859 cmd.idx = 0;
2860 ace_issue_cmd(regs, &cmd);
2861 ap->promisc = 1;
2862 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2863 cmd.evt = C_SET_PROMISC_MODE;
2864 cmd.code = C_C_PROMISC_DISABLE;
2865 cmd.idx = 0;
2866 ace_issue_cmd(regs, &cmd);
2867 ap->promisc = 0;
2868 }
2869
2870 /*
2871 * For the time being multicast relies on the upper layers
2872 * filtering it properly. The Firmware does not allow one to
2873 * set the entire multicast list at a time and keeping track of
2874 * it here is going to be messy.
2875 */
2876 if ((dev->mc_count) && !(ap->mcast_all)) {
2877 cmd.evt = C_SET_MULTICAST_MODE;
2878 cmd.code = C_C_MCAST_ENABLE;
2879 cmd.idx = 0;
2880 ace_issue_cmd(regs, &cmd);
2881 }else if (!ap->mcast_all) {
2882 cmd.evt = C_SET_MULTICAST_MODE;
2883 cmd.code = C_C_MCAST_DISABLE;
2884 cmd.idx = 0;
2885 ace_issue_cmd(regs, &cmd);
2886 }
2887}
2888
2889
2890static struct net_device_stats *ace_get_stats(struct net_device *dev)
2891{
2892 struct ace_private *ap = netdev_priv(dev);
2893 struct ace_mac_stats __iomem *mac_stats =
2894 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2895
2896 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2897 ap->stats.multicast = readl(&mac_stats->kept_mc);
2898 ap->stats.collisions = readl(&mac_stats->coll);
2899
2900 return &ap->stats;
2901}
2902
2903
2904static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2905 u32 dest, int size)
2906{
2907 void __iomem *tdest;
2908 u32 *wsrc;
2909 short tsize, i;
2910
2911 if (size <= 0)
2912 return;
2913
2914 while (size > 0) {
2915 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2916 min_t(u32, size, ACE_WINDOW_SIZE));
2917 tdest = (void __iomem *) &regs->Window +
2918 (dest & (ACE_WINDOW_SIZE - 1));
2919 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2920 /*
2921 * This requires byte swapping on big endian, however
2922 * writel does that for us
2923 */
2924 wsrc = src;
2925 for (i = 0; i < (tsize / 4); i++) {
2926 writel(wsrc[i], tdest + i*4);
2927 }
2928 dest += tsize;
2929 src += tsize;
2930 size -= tsize;
2931 }
2932
2933 return;
2934}
2935
2936
2937static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2938{
2939 void __iomem *tdest;
2940 short tsize = 0, i;
2941
2942 if (size <= 0)
2943 return;
2944
2945 while (size > 0) {
2946 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2947 min_t(u32, size, ACE_WINDOW_SIZE));
2948 tdest = (void __iomem *) &regs->Window +
2949 (dest & (ACE_WINDOW_SIZE - 1));
2950 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2951
2952 for (i = 0; i < (tsize / 4); i++) {
2953 writel(0, tdest + i*4);
2954 }
2955
2956 dest += tsize;
2957 size -= tsize;
2958 }
2959
2960 return;
2961}
2962
2963
2964/*
2965 * Download the firmware into the SRAM on the NIC
2966 *
2967 * This operation requires the NIC to be halted and is performed with
2968 * interrupts disabled and with the spinlock hold.
2969 */
2970int __devinit ace_load_firmware(struct net_device *dev)
2971{
2972 struct ace_private *ap = netdev_priv(dev);
2973 struct ace_regs __iomem *regs = ap->regs;
2974
2975 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2976 printk(KERN_ERR "%s: trying to download firmware while the "
2977 "CPU is running!\n", ap->name);
2978 return -EFAULT;
2979 }
2980
2981 /*
2982 * Do not try to clear more than 512KB or we end up seeing
2983 * funny things on NICs with only 512KB SRAM
2984 */
2985 ace_clear(regs, 0x2000, 0x80000-0x2000);
2986 if (ACE_IS_TIGON_I(ap)) {
2987 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2988 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2989 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2990 tigonFwRodataLen);
2991 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2992 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2993 }else if (ap->version == 2) {
2994 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2995 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2996 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
2997 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
2998 tigon2FwRodataLen);
2999 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
3000 }
3001
3002 return 0;
3003}
3004
3005
3006/*
3007 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3008 *
3009 * Accessing the EEPROM is `interesting' to say the least - don't read
3010 * this code right after dinner.
3011 *
3012 * This is all about black magic and bit-banging the device .... I
3013 * wonder in what hospital they have put the guy who designed the i2c
3014 * specs.
3015 *
3016 * Oh yes, this is only the beginning!
3017 *
3018 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3019 * code i2c readout code by beta testing all my hacks.
3020 */
3021static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3022{
3023 u32 local;
3024
3025 readl(&regs->LocalCtrl);
3026 udelay(ACE_SHORT_DELAY);
3027 local = readl(&regs->LocalCtrl);
3028 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3029 writel(local, &regs->LocalCtrl);
3030 readl(&regs->LocalCtrl);
3031 mb();
3032 udelay(ACE_SHORT_DELAY);
3033 local |= EEPROM_CLK_OUT;
3034 writel(local, &regs->LocalCtrl);
3035 readl(&regs->LocalCtrl);
3036 mb();
3037 udelay(ACE_SHORT_DELAY);
3038 local &= ~EEPROM_DATA_OUT;
3039 writel(local, &regs->LocalCtrl);
3040 readl(&regs->LocalCtrl);
3041 mb();
3042 udelay(ACE_SHORT_DELAY);
3043 local &= ~EEPROM_CLK_OUT;
3044 writel(local, &regs->LocalCtrl);
3045 readl(&regs->LocalCtrl);
3046 mb();
3047}
3048
3049
3050static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3051{
3052 short i;
3053 u32 local;
3054
3055 udelay(ACE_SHORT_DELAY);
3056 local = readl(&regs->LocalCtrl);
3057 local &= ~EEPROM_DATA_OUT;
3058 local |= EEPROM_WRITE_ENABLE;
3059 writel(local, &regs->LocalCtrl);
3060 readl(&regs->LocalCtrl);
3061 mb();
3062
3063 for (i = 0; i < 8; i++, magic <<= 1) {
3064 udelay(ACE_SHORT_DELAY);
3065 if (magic & 0x80)
3066 local |= EEPROM_DATA_OUT;
3067 else
3068 local &= ~EEPROM_DATA_OUT;
3069 writel(local, &regs->LocalCtrl);
3070 readl(&regs->LocalCtrl);
3071 mb();
3072
3073 udelay(ACE_SHORT_DELAY);
3074 local |= EEPROM_CLK_OUT;
3075 writel(local, &regs->LocalCtrl);
3076 readl(&regs->LocalCtrl);
3077 mb();
3078 udelay(ACE_SHORT_DELAY);
3079 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3080 writel(local, &regs->LocalCtrl);
3081 readl(&regs->LocalCtrl);
3082 mb();
3083 }
3084}
3085
3086
3087static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3088{
3089 int state;
3090 u32 local;
3091
3092 local = readl(&regs->LocalCtrl);
3093 local &= ~EEPROM_WRITE_ENABLE;
3094 writel(local, &regs->LocalCtrl);
3095 readl(&regs->LocalCtrl);
3096 mb();
3097 udelay(ACE_LONG_DELAY);
3098 local |= EEPROM_CLK_OUT;
3099 writel(local, &regs->LocalCtrl);
3100 readl(&regs->LocalCtrl);
3101 mb();
3102 udelay(ACE_SHORT_DELAY);
3103 /* sample data in middle of high clk */
3104 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3105 udelay(ACE_SHORT_DELAY);
3106 mb();
3107 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3108 readl(&regs->LocalCtrl);
3109 mb();
3110
3111 return state;
3112}
3113
3114
3115static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3116{
3117 u32 local;
3118
3119 udelay(ACE_SHORT_DELAY);
3120 local = readl(&regs->LocalCtrl);
3121 local |= EEPROM_WRITE_ENABLE;
3122 writel(local, &regs->LocalCtrl);
3123 readl(&regs->LocalCtrl);
3124 mb();
3125 udelay(ACE_SHORT_DELAY);
3126 local &= ~EEPROM_DATA_OUT;
3127 writel(local, &regs->LocalCtrl);
3128 readl(&regs->LocalCtrl);
3129 mb();
3130 udelay(ACE_SHORT_DELAY);
3131 local |= EEPROM_CLK_OUT;
3132 writel(local, &regs->LocalCtrl);
3133 readl(&regs->LocalCtrl);
3134 mb();
3135 udelay(ACE_SHORT_DELAY);
3136 local |= EEPROM_DATA_OUT;
3137 writel(local, &regs->LocalCtrl);
3138 readl(&regs->LocalCtrl);
3139 mb();
3140 udelay(ACE_LONG_DELAY);
3141 local &= ~EEPROM_CLK_OUT;
3142 writel(local, &regs->LocalCtrl);
3143 mb();
3144}
3145
3146
3147/*
3148 * Read a whole byte from the EEPROM.
3149 */
3150static int __devinit read_eeprom_byte(struct net_device *dev,
3151 unsigned long offset)
3152{
3153 struct ace_private *ap = netdev_priv(dev);
3154 struct ace_regs __iomem *regs = ap->regs;
3155 unsigned long flags;
3156 u32 local;
3157 int result = 0;
3158 short i;
3159
3160 if (!dev) {
3161 printk(KERN_ERR "No device!\n");
3162 result = -ENODEV;
3163 goto out;
3164 }
3165
3166 /*
3167 * Don't take interrupts on this CPU will bit banging
3168 * the %#%#@$ I2C device
3169 */
3170 local_irq_save(flags);
3171
3172 eeprom_start(regs);
3173
3174 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3175 if (eeprom_check_ack(regs)) {
3176 local_irq_restore(flags);
3177 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3178 result = -EIO;
3179 goto eeprom_read_error;
3180 }
3181
3182 eeprom_prep(regs, (offset >> 8) & 0xff);
3183 if (eeprom_check_ack(regs)) {
3184 local_irq_restore(flags);
3185 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3186 ap->name);
3187 result = -EIO;
3188 goto eeprom_read_error;
3189 }
3190
3191 eeprom_prep(regs, offset & 0xff);
3192 if (eeprom_check_ack(regs)) {
3193 local_irq_restore(flags);
3194 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3195 ap->name);
3196 result = -EIO;
3197 goto eeprom_read_error;
3198 }
3199
3200 eeprom_start(regs);
3201 eeprom_prep(regs, EEPROM_READ_SELECT);
3202 if (eeprom_check_ack(regs)) {
3203 local_irq_restore(flags);
3204 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3205 ap->name);
3206 result = -EIO;
3207 goto eeprom_read_error;
3208 }
3209
3210 for (i = 0; i < 8; i++) {
3211 local = readl(&regs->LocalCtrl);
3212 local &= ~EEPROM_WRITE_ENABLE;
3213 writel(local, &regs->LocalCtrl);
3214 readl(&regs->LocalCtrl);
3215 udelay(ACE_LONG_DELAY);
3216 mb();
3217 local |= EEPROM_CLK_OUT;
3218 writel(local, &regs->LocalCtrl);
3219 readl(&regs->LocalCtrl);
3220 mb();
3221 udelay(ACE_SHORT_DELAY);
3222 /* sample data mid high clk */
3223 result = (result << 1) |
3224 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3225 udelay(ACE_SHORT_DELAY);
3226 mb();
3227 local = readl(&regs->LocalCtrl);
3228 local &= ~EEPROM_CLK_OUT;
3229 writel(local, &regs->LocalCtrl);
3230 readl(&regs->LocalCtrl);
3231 udelay(ACE_SHORT_DELAY);
3232 mb();
3233 if (i == 7) {
3234 local |= EEPROM_WRITE_ENABLE;
3235 writel(local, &regs->LocalCtrl);
3236 readl(&regs->LocalCtrl);
3237 mb();
3238 udelay(ACE_SHORT_DELAY);
3239 }
3240 }
3241
3242 local |= EEPROM_DATA_OUT;
3243 writel(local, &regs->LocalCtrl);
3244 readl(&regs->LocalCtrl);
3245 mb();
3246 udelay(ACE_SHORT_DELAY);
3247 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3248 readl(&regs->LocalCtrl);
3249 udelay(ACE_LONG_DELAY);
3250 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3251 readl(&regs->LocalCtrl);
3252 mb();
3253 udelay(ACE_SHORT_DELAY);
3254 eeprom_stop(regs);
3255
3256 local_irq_restore(flags);
3257 out:
3258 return result;
3259
3260 eeprom_read_error:
3261 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3262 ap->name, offset);
3263 goto out;
3264}
3265
3266
3267/*
3268 * Local variables:
3269 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3270 * End:
3271 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 03:18:12 -0500