4 files changed, 57 insertions, 10 deletions

diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 6ae9ca01388b..9a9ce71a71fc 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -119,7 +119,7 @@ static int mtd_cls_suspend(struct device *dev, pm_message_t state)
 {
         struct mtd_info *mtd = dev_get_drvdata(dev);
 
-        return mtd_suspend(mtd);
+        return mtd ? mtd_suspend(mtd) : 0;
 }
 
 static int mtd_cls_resume(struct device *dev)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 4dd056e2e16a..35b4fb55dbd6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -161,6 +161,37 @@ static int atmel_nand_device_ready(struct mtd_info *mtd)
                 !!host->board->rdy_pin_active_low;
 }
 
+/*
+ * Minimal-overhead PIO for data access.
+ */
+static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
+{
+        struct nand_chip        *nand_chip = mtd->priv;
+
+        __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
+}
+
+static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
+{
+        struct nand_chip        *nand_chip = mtd->priv;
+
+        __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
+}
+
+static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
+{
+        struct nand_chip        *nand_chip = mtd->priv;
+
+        __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
+}
+
+static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
+{
+        struct nand_chip        *nand_chip = mtd->priv;
+
+        __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
+}
+
 static void dma_complete_func(void *completion)
 {
         complete(completion);
@@ -235,27 +266,33 @@ err_buf:
 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
         struct nand_chip *chip = mtd->priv;
+        struct atmel_nand_host *host = chip->priv;
 
         if (use_dma && len > mtd->oobsize)
                 /* only use DMA for bigger than oob size: better performances */
                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
                         return;
 
-        /* if no DMA operation possible, use PIO */
-        memcpy_fromio(buf, chip->IO_ADDR_R, len);
+        if (host->board->bus_width_16)
+                atmel_read_buf16(mtd, buf, len);
+        else
+                atmel_read_buf8(mtd, buf, len);
 }
 
 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
         struct nand_chip *chip = mtd->priv;
+        struct atmel_nand_host *host = chip->priv;
 
         if (use_dma && len > mtd->oobsize)
                 /* only use DMA for bigger than oob size: better performances */
                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
                         return;
 
-        /* if no DMA operation possible, use PIO */
-        memcpy_toio(chip->IO_ADDR_W, buf, len);
+        if (host->board->bus_width_16)
+                atmel_write_buf16(mtd, buf, len);
+        else
+                atmel_write_buf8(mtd, buf, len);
 }
 
 /*
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 7f680420bfab..7db6555ed3ba 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -69,17 +69,19 @@ static int clear_poll_bit(void __iomem *addr, u32 mask)
  *  [1] enable the module.
  *  [2] reset the module.
  *
- * In most of the cases, it's ok. But there is a hardware bug in the BCH block.
+ * In most of the cases, it's ok.
+ * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
  * If you try to soft reset the BCH block, it becomes unusable until
  * the next hard reset. This case occurs in the NAND boot mode. When the board
  * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
  * So If the driver tries to reset the BCH again, the BCH will not work anymore.
- * You will see a DMA timeout in this case.
+ * You will see a DMA timeout in this case. The bug has been fixed
+ * in the following chips, such as MX28.
  *
  * To avoid this bug, just add a new parameter `just_enable` for
  * the mxs_reset_block(), and rewrite it here.
  */
-int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
+static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
 {
         int ret;
         int timeout = 0x400;
@@ -206,7 +208,15 @@ int bch_set_geometry(struct gpmi_nand_data *this)
         if (ret)
                 goto err_out;
 
-        ret = gpmi_reset_block(r->bch_regs, true);
+        /*
+        * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
+        * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
+        * On the other hand, the MX28 needs the reset, because one case has been
+        * seen where the BCH produced ECC errors constantly after 10000
+        * consecutive reboots. The latter case has not been seen on the MX23 yet,
+        * still we don't know if it could happen there as well.
+        */
+        ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
         if (ret)
                 goto err_out;
 
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 35b4565050f1..8a393f9e6027 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2588,7 +2588,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
         instr->state = MTD_ERASING;
 
         while (len) {
-                /* Heck if we have a bad block, we do not erase bad blocks! */
+                /* Check if we have a bad block, we do not erase bad blocks! */
                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
                                         chip->page_shift, 0, allowbbt)) {
                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",