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-rw-r--r--drivers/mtd/nand/Kconfig11
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/r852.c1117
-rw-r--r--drivers/mtd/nand/r852.h163
4 files changed, 1292 insertions, 0 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7a67218e86fc..6701a00b7a9a 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -102,6 +102,17 @@ config MTD_NAND_OMAP_PREFETCH_DMA
102config MTD_NAND_IDS 102config MTD_NAND_IDS
103 tristate 103 tristate
104 104
105config MTD_NAND_RICOH
106 tristate "Ricoh xD card reader"
107 default n
108 select MTD_SM_COMMON
109 help
110 Enable support for Ricoh R5C852 xD card reader
111 You also need to enable ether
112 NAND SSFDC (SmartMedia) read only translation layer' or new
113 expermental, readwrite
114 'SmartMedia/xD new translation layer'
115
105config MTD_NAND_AU1550 116config MTD_NAND_AU1550
106 tristate "Au1550/1200 NAND support" 117 tristate "Au1550/1200 NAND support"
107 depends on SOC_AU1200 || SOC_AU1550 118 depends on SOC_AU1200 || SOC_AU1550
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f39d0b6ed42c..5fbd1f83afb6 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -43,5 +43,6 @@ obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o
43obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o 43obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
44obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o 44obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
45obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o 45obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
46obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
46 47
47nand-objs := nand_base.o nand_bbt.o 48nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c
new file mode 100644
index 000000000000..9307a88e5229
--- /dev/null
+++ b/drivers/mtd/nand/r852.c
@@ -0,0 +1,1117 @@
1/*
2 * Copyright © 2009 - Maxim Levitsky
3 * driver for Ricoh xD readers
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/jiffies.h>
13#include <linux/workqueue.h>
14#include <linux/interrupt.h>
15#include <linux/pci_ids.h>
16#include <asm/byteorder.h>
17#include <linux/sched.h>
18#include "sm_common.h"
19#include "r852.h"
20
21
22static int enable_dma = 1;
23module_param(enable_dma, bool, S_IRUGO);
24MODULE_PARM_DESC(enable_dma, "Enable usage of the DMA (default)");
25
26static int debug;
27module_param(debug, int, S_IRUGO | S_IWUSR);
28MODULE_PARM_DESC(debug, "Debug level (0-2)");
29
30/* read register */
31static inline uint8_t r852_read_reg(struct r852_device *dev, int address)
32{
33 uint8_t reg = readb(dev->mmio + address);
34 return reg;
35}
36
37/* write register */
38static inline void r852_write_reg(struct r852_device *dev,
39 int address, uint8_t value)
40{
41 writeb(value, dev->mmio + address);
42 mmiowb();
43}
44
45
46/* read dword sized register */
47static inline uint32_t r852_read_reg_dword(struct r852_device *dev, int address)
48{
49 uint32_t reg = le32_to_cpu(readl(dev->mmio + address));
50 return reg;
51}
52
53/* write dword sized register */
54static inline void r852_write_reg_dword(struct r852_device *dev,
55 int address, uint32_t value)
56{
57 writel(cpu_to_le32(value), dev->mmio + address);
58 mmiowb();
59}
60
61/* returns pointer to our private structure */
62static inline struct r852_device *r852_get_dev(struct mtd_info *mtd)
63{
64 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
65 return (struct r852_device *)chip->priv;
66}
67
68
69/* check if controller supports dma */
70static void r852_dma_test(struct r852_device *dev)
71{
72 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) &
73 (R852_DMA1 | R852_DMA2)) == (R852_DMA1 | R852_DMA2);
74
75 if (!dev->dma_usable)
76 message("Non dma capable device detected, dma disabled");
77
78 if (!enable_dma) {
79 message("disabling dma on user request");
80 dev->dma_usable = 0;
81 }
82}
83
84/*
85 * Enable dma. Enables ether first or second stage of the DMA,
86 * Expects dev->dma_dir and dev->dma_state be set
87 */
88static void r852_dma_enable(struct r852_device *dev)
89{
90 uint8_t dma_reg, dma_irq_reg;
91
92 /* Set up dma settings */
93 dma_reg = r852_read_reg_dword(dev, R852_DMA_SETTINGS);
94 dma_reg &= ~(R852_DMA_READ | R852_DMA_INTERNAL | R852_DMA_MEMORY);
95
96 if (dev->dma_dir)
97 dma_reg |= R852_DMA_READ;
98
99 if (dev->dma_state == DMA_INTERNAL)
100 dma_reg |= R852_DMA_INTERNAL;
101 else {
102 dma_reg |= R852_DMA_MEMORY;
103 r852_write_reg_dword(dev, R852_DMA_ADDR,
104 cpu_to_le32(dev->phys_dma_addr));
105 }
106
107 r852_write_reg_dword(dev, R852_DMA_SETTINGS, dma_reg);
108
109 /* Set dma irq */
110 dma_irq_reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
111 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
112 dma_irq_reg |
113 R852_DMA_IRQ_INTERNAL |
114 R852_DMA_IRQ_ERROR |
115 R852_DMA_IRQ_MEMORY);
116}
117
118/*
119 * Disable dma, called from the interrupt handler, which specifies
120 * success of the operation via 'error' argument
121 */
122static void r852_dma_done(struct r852_device *dev, int error)
123{
124 WARN_ON(dev->dma_stage == 0);
125
126 r852_write_reg_dword(dev, R852_DMA_IRQ_STA,
127 r852_read_reg_dword(dev, R852_DMA_IRQ_STA));
128
129 r852_write_reg_dword(dev, R852_DMA_SETTINGS, 0);
130 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE, 0);
131
132 dev->dma_error = error;
133 dev->dma_stage = 0;
134
135 if (dev->phys_dma_addr && dev->phys_dma_addr != dev->phys_bounce_buffer)
136 pci_unmap_single(dev->pci_dev, dev->phys_dma_addr, R852_DMA_LEN,
137 dev->dma_dir ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
138 complete(&dev->dma_done);
139}
140
141/*
142 * Wait, till dma is done, which includes both phases of it
143 */
144static int r852_dma_wait(struct r852_device *dev)
145{
146 long timeout = wait_for_completion_timeout(&dev->dma_done,
147 msecs_to_jiffies(1000));
148 if (!timeout) {
149 dbg("timeout waiting for DMA interrupt");
150 return -ETIMEDOUT;
151 }
152
153 return 0;
154}
155
156/*
157 * Read/Write one page using dma. Only pages can be read (512 bytes)
158*/
159static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read)
160{
161 int bounce = 0;
162 unsigned long flags;
163 int error;
164
165 dev->dma_error = 0;
166
167 /* Set dma direction */
168 dev->dma_dir = do_read;
169 dev->dma_stage = 1;
170
171 dbg_verbose("doing dma %s ", do_read ? "read" : "write");
172
173 /* Set intial dma state: for reading first fill on board buffer,
174 from device, for writes first fill the buffer from memory*/
175 dev->dma_state = do_read ? DMA_INTERNAL : DMA_MEMORY;
176
177 /* if incoming buffer is not page aligned, we should do bounce */
178 if ((unsigned long)buf & (R852_DMA_LEN-1))
179 bounce = 1;
180
181 if (!bounce) {
182 dev->phys_dma_addr = pci_map_single(dev->pci_dev, (void *)buf,
183 R852_DMA_LEN,
184 (do_read ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
185
186 if (dev->phys_dma_addr == DMA_ERROR_CODE)
187 bounce = 1;
188 }
189
190 if (bounce) {
191 dbg_verbose("dma: using bounce buffer");
192 dev->phys_dma_addr = dev->phys_bounce_buffer;
193 if (!do_read)
194 memcpy(dev->bounce_buffer, buf, R852_DMA_LEN);
195 }
196
197 /* Enable DMA */
198 spin_lock_irqsave(&dev->irqlock, flags);
199 r852_dma_enable(dev);
200 spin_unlock_irqrestore(&dev->irqlock, flags);
201
202 /* Wait till complete */
203 error = r852_dma_wait(dev);
204
205 if (error) {
206 r852_dma_done(dev, error);
207 return;
208 }
209
210 if (do_read && bounce)
211 memcpy((void *)buf, dev->bounce_buffer, R852_DMA_LEN);
212}
213
214/*
215 * Program data lines of the nand chip to send data to it
216 */
217void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
218{
219 struct r852_device *dev = r852_get_dev(mtd);
220 uint32_t reg;
221
222 /* Don't allow any access to hardware if we suspect card removal */
223 if (dev->card_unstable)
224 return;
225
226 /* Special case for whole sector read */
227 if (len == R852_DMA_LEN && dev->dma_usable) {
228 r852_do_dma(dev, (uint8_t *)buf, 0);
229 return;
230 }
231
232 /* write DWORD chinks - faster */
233 while (len) {
234 reg = buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24;
235 r852_write_reg_dword(dev, R852_DATALINE, reg);
236 buf += 4;
237 len -= 4;
238
239 }
240
241 /* write rest */
242 while (len)
243 r852_write_reg(dev, R852_DATALINE, *buf++);
244}
245
246/*
247 * Read data lines of the nand chip to retrieve data
248 */
249void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
250{
251 struct r852_device *dev = r852_get_dev(mtd);
252 uint32_t reg;
253
254 if (dev->card_unstable) {
255 /* since we can't signal error here, at least, return
256 predictable buffer */
257 memset(buf, 0, len);
258 return;
259 }
260
261 /* special case for whole sector read */
262 if (len == R852_DMA_LEN && dev->dma_usable) {
263 r852_do_dma(dev, buf, 1);
264 return;
265 }
266
267 /* read in dword sized chunks */
268 while (len >= 4) {
269
270 reg = r852_read_reg_dword(dev, R852_DATALINE);
271 *buf++ = reg & 0xFF;
272 *buf++ = (reg >> 8) & 0xFF;
273 *buf++ = (reg >> 16) & 0xFF;
274 *buf++ = (reg >> 24) & 0xFF;
275 len -= 4;
276 }
277
278 /* read the reset by bytes */
279 while (len--)
280 *buf++ = r852_read_reg(dev, R852_DATALINE);
281}
282
283/*
284 * Read one byte from nand chip
285 */
286static uint8_t r852_read_byte(struct mtd_info *mtd)
287{
288 struct r852_device *dev = r852_get_dev(mtd);
289
290 /* Same problem as in r852_read_buf.... */
291 if (dev->card_unstable)
292 return 0;
293
294 return r852_read_reg(dev, R852_DATALINE);
295}
296
297
298/*
299 * Readback the buffer to verify it
300 */
301int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
302{
303 struct r852_device *dev = r852_get_dev(mtd);
304
305 /* We can't be sure about anything here... */
306 if (dev->card_unstable)
307 return -1;
308
309 /* This will never happen, unless you wired up a nand chip
310 with > 512 bytes page size to the reader */
311 if (len > SM_SECTOR_SIZE)
312 return 0;
313
314 r852_read_buf(mtd, dev->tmp_buffer, len);
315 return memcmp(buf, dev->tmp_buffer, len);
316}
317
318/*
319 * Control several chip lines & send commands
320 */
321void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl)
322{
323 struct r852_device *dev = r852_get_dev(mtd);
324
325 if (dev->card_unstable)
326 return;
327
328 if (ctrl & NAND_CTRL_CHANGE) {
329
330 dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
331 R852_CTL_ON | R852_CTL_CARDENABLE);
332
333 if (ctrl & NAND_ALE)
334 dev->ctlreg |= R852_CTL_DATA;
335
336 if (ctrl & NAND_CLE)
337 dev->ctlreg |= R852_CTL_COMMAND;
338
339 if (ctrl & NAND_NCE)
340 dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
341 else
342 dev->ctlreg &= ~R852_CTL_WRITE;
343
344 /* when write is stareted, enable write access */
345 if (dat == NAND_CMD_ERASE1)
346 dev->ctlreg |= R852_CTL_WRITE;
347
348 r852_write_reg(dev, R852_CTL, dev->ctlreg);
349 }
350
351 /* HACK: NAND_CMD_SEQIN is called without NAND_CTRL_CHANGE, but we need
352 to set write mode */
353 if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
354 dev->ctlreg |= R852_CTL_WRITE;
355 r852_write_reg(dev, R852_CTL, dev->ctlreg);
356 }
357
358 if (dat != NAND_CMD_NONE)
359 r852_write_reg(dev, R852_DATALINE, dat);
360}
361
362/*
363 * Wait till card is ready.
364 * based on nand_wait, but returns errors on DMA error
365 */
366int r852_wait(struct mtd_info *mtd, struct nand_chip *chip)
367{
368 struct r852_device *dev = (struct r852_device *)chip->priv;
369
370 unsigned long timeout;
371 int status;
372
373 timeout = jiffies + (chip->state == FL_ERASING ?
374 msecs_to_jiffies(400) : msecs_to_jiffies(20));
375
376 while (time_before(jiffies, timeout))
377 if (chip->dev_ready(mtd))
378 break;
379
380 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
381 status = (int)chip->read_byte(mtd);
382
383 /* Unfortunelly, no way to send detailed error status... */
384 if (dev->dma_error) {
385 status |= NAND_STATUS_FAIL;
386 dev->dma_error = 0;
387 }
388 return status;
389}
390
391/*
392 * Check if card is ready
393 */
394
395int r852_ready(struct mtd_info *mtd)
396{
397 struct r852_device *dev = r852_get_dev(mtd);
398 return !(r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_BUSY);
399}
400
401
402/*
403 * Set ECC engine mode
404*/
405
406void r852_ecc_hwctl(struct mtd_info *mtd, int mode)
407{
408 struct r852_device *dev = r852_get_dev(mtd);
409
410 if (dev->card_unstable)
411 return;
412
413 switch (mode) {
414 case NAND_ECC_READ:
415 case NAND_ECC_WRITE:
416 /* enable ecc generation/check*/
417 dev->ctlreg |= R852_CTL_ECC_ENABLE;
418
419 /* flush ecc buffer */
420 r852_write_reg(dev, R852_CTL,
421 dev->ctlreg | R852_CTL_ECC_ACCESS);
422
423 r852_read_reg_dword(dev, R852_DATALINE);
424 r852_write_reg(dev, R852_CTL, dev->ctlreg);
425 return;
426
427 case NAND_ECC_READSYN:
428 /* disable ecc generation */
429 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
430 r852_write_reg(dev, R852_CTL, dev->ctlreg);
431 }
432}
433
434/*
435 * Calculate ECC, only used for writes
436 */
437
438int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
439 uint8_t *ecc_code)
440{
441 struct r852_device *dev = r852_get_dev(mtd);
442 struct sm_oob *oob = (struct sm_oob *)ecc_code;
443 uint32_t ecc1, ecc2;
444
445 if (dev->card_unstable)
446 return 0;
447
448 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
449 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
450
451 ecc1 = r852_read_reg_dword(dev, R852_DATALINE);
452 ecc2 = r852_read_reg_dword(dev, R852_DATALINE);
453
454 oob->ecc1[0] = (ecc1) & 0xFF;
455 oob->ecc1[1] = (ecc1 >> 8) & 0xFF;
456 oob->ecc1[2] = (ecc1 >> 16) & 0xFF;
457
458 oob->ecc2[0] = (ecc2) & 0xFF;
459 oob->ecc2[1] = (ecc2 >> 8) & 0xFF;
460 oob->ecc2[2] = (ecc2 >> 16) & 0xFF;
461
462 r852_write_reg(dev, R852_CTL, dev->ctlreg);
463 return 0;
464}
465
466/*
467 * Correct the data using ECC, hw did almost everything for us
468 */
469
470int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
471 uint8_t *read_ecc, uint8_t *calc_ecc)
472{
473 uint16_t ecc_reg;
474 uint8_t ecc_status, err_byte;
475 int i, error = 0;
476
477 struct r852_device *dev = r852_get_dev(mtd);
478
479 if (dev->card_unstable)
480 return 0;
481
482 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
483 ecc_reg = r852_read_reg_dword(dev, R852_DATALINE);
484 r852_write_reg(dev, R852_CTL, dev->ctlreg);
485
486 for (i = 0 ; i <= 1 ; i++) {
487
488 ecc_status = (ecc_reg >> 8) & 0xFF;
489
490 /* ecc uncorrectable error */
491 if (ecc_status & R852_ECC_FAIL) {
492 dbg("ecc: unrecoverable error, in half %d", i);
493 error = -1;
494 goto exit;
495 }
496
497 /* correctable error */
498 if (ecc_status & R852_ECC_CORRECTABLE) {
499
500 err_byte = ecc_reg & 0xFF;
501 dbg("ecc: recoverable error, "
502 "in half %d, byte %d, bit %d", i,
503 err_byte, ecc_status & R852_ECC_ERR_BIT_MSK);
504
505 dat[err_byte] ^=
506 1 << (ecc_status & R852_ECC_ERR_BIT_MSK);
507 error++;
508 }
509
510 dat += 256;
511 ecc_reg >>= 16;
512 }
513exit:
514 return error;
515}
516
517/*
518 * This is copy of nand_read_oob_std
519 * nand_read_oob_syndrome assumes we can send column address - we can't
520 */
521static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
522 int page, int sndcmd)
523{
524 if (sndcmd) {
525 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
526 sndcmd = 0;
527 }
528 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
529 return sndcmd;
530}
531
532/*
533 * Start the nand engine
534 */
535
536void r852_engine_enable(struct r852_device *dev)
537{
538 if (r852_read_reg_dword(dev, R852_HW) & R852_HW_UNKNOWN) {
539 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
540 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
541 } else {
542 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
543 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
544 }
545 msleep(300);
546 r852_write_reg(dev, R852_CTL, 0);
547}
548
549
550/*
551 * Stop the nand engine
552 */
553
554void r852_engine_disable(struct r852_device *dev)
555{
556 r852_write_reg_dword(dev, R852_HW, 0);
557 r852_write_reg(dev, R852_CTL, R852_CTL_RESET);
558}
559
560/*
561 * Test if card is present
562 */
563
564void r852_card_update_present(struct r852_device *dev)
565{
566 unsigned long flags;
567 uint8_t reg;
568
569 spin_lock_irqsave(&dev->irqlock, flags);
570 reg = r852_read_reg(dev, R852_CARD_STA);
571 dev->card_detected = !!(reg & R852_CARD_STA_PRESENT);
572 spin_unlock_irqrestore(&dev->irqlock, flags);
573}
574
575/*
576 * Update card detection IRQ state according to current card state
577 * which is read in r852_card_update_present
578 */
579void r852_update_card_detect(struct r852_device *dev)
580{
581 int card_detect_reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
582
583 card_detect_reg &= ~(R852_CARD_IRQ_REMOVE | R852_CARD_IRQ_INSERT);
584 card_detect_reg |= R852_CARD_IRQ_GENABLE;
585
586 card_detect_reg |= dev->card_detected ?
587 R852_CARD_IRQ_REMOVE : R852_CARD_IRQ_INSERT;
588
589 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, card_detect_reg);
590}
591
592ssize_t r852_media_type_show(struct device *sys_dev,
593 struct device_attribute *attr, char *buf)
594{
595 struct mtd_info *mtd = container_of(sys_dev, struct mtd_info, dev);
596 struct r852_device *dev = r852_get_dev(mtd);
597 char *data = dev->sm ? "smartmedia" : "xd";
598
599 strcpy(buf, data);
600 return strlen(data);
601}
602
603DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL);
604
605
606/* Detect properties of card in slot */
607void r852_update_media_status(struct r852_device *dev)
608{
609 uint8_t reg;
610 unsigned long flags;
611 int readonly;
612
613 spin_lock_irqsave(&dev->irqlock, flags);
614 if (!dev->card_detected) {
615 message("card removed");
616 spin_unlock_irqrestore(&dev->irqlock, flags);
617 return ;
618 }
619
620 readonly = r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_RO;
621 reg = r852_read_reg(dev, R852_DMA_CAP);
622 dev->sm = (reg & (R852_DMA1 | R852_DMA2)) && (reg & R852_SMBIT);
623
624 message("detected %s %s card in slot",
625 dev->sm ? "SmartMedia" : "xD",
626 readonly ? "readonly" : "writeable");
627
628 dev->readonly = readonly;
629 spin_unlock_irqrestore(&dev->irqlock, flags);
630}
631
632/*
633 * Register the nand device
634 * Called when the card is detected
635 */
636int r852_register_nand_device(struct r852_device *dev)
637{
638 dev->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
639
640 if (!dev->mtd)
641 goto error1;
642
643 WARN_ON(dev->card_registred);
644
645 dev->mtd->owner = THIS_MODULE;
646 dev->mtd->priv = dev->chip;
647 dev->mtd->dev.parent = &dev->pci_dev->dev;
648
649 if (dev->readonly)
650 dev->chip->options |= NAND_ROM;
651
652 r852_engine_enable(dev);
653
654 if (sm_register_device(dev->mtd))
655 goto error2;
656
657 device_create_file(&dev->mtd->dev, &dev_attr_media_type);
658 dev->card_registred = 1;
659 return 0;
660error2:
661 kfree(dev->mtd);
662error1:
663 /* Force card redetect */
664 dev->card_detected = 0;
665 return -1;
666}
667
668/*
669 * Unregister the card
670 */
671
672void r852_unregister_nand_device(struct r852_device *dev)
673{
674 if (!dev->card_registred)
675 return;
676
677 device_remove_file(&dev->mtd->dev, &dev_attr_media_type);
678 nand_release(dev->mtd);
679 r852_engine_disable(dev);
680 dev->card_registred = 0;
681 kfree(dev->mtd);
682 dev->mtd = NULL;
683}
684
685/* Card state updater */
686void r852_card_detect_work(struct work_struct *work)
687{
688 struct r852_device *dev =
689 container_of(work, struct r852_device, card_detect_work.work);
690
691 r852_update_card_detect(dev);
692 dev->card_unstable = 0;
693
694 /* false alarm */
695 if (dev->card_detected == dev->card_registred)
696 goto exit;
697
698 /* Read media properties */
699 r852_update_media_status(dev);
700
701 /* Register the card */
702 if (dev->card_detected)
703 r852_register_nand_device(dev);
704 else
705 r852_unregister_nand_device(dev);
706exit:
707 /* Update detection logic */
708 r852_update_card_detect(dev);
709}
710
711/* Ack + disable IRQ generation */
712static void r852_disable_irqs(struct r852_device *dev)
713{
714 uint8_t reg;
715 reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
716 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, reg & ~R852_CARD_IRQ_MASK);
717
718 reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
719 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
720 reg & ~R852_DMA_IRQ_MASK);
721
722 r852_write_reg(dev, R852_CARD_IRQ_STA, R852_CARD_IRQ_MASK);
723 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, R852_DMA_IRQ_MASK);
724}
725
726/* Interrupt handler */
727static irqreturn_t r852_irq(int irq, void *data)
728{
729 struct r852_device *dev = (struct r852_device *)data;
730
731 uint8_t card_status, dma_status;
732 unsigned long flags;
733 irqreturn_t ret = IRQ_NONE;
734
735 spin_lock_irqsave(&dev->irqlock, flags);
736
737 /* We can recieve shared interrupt while pci is suspended
738 in that case reads will return 0xFFFFFFFF.... */
739 if (dev->insuspend)
740 goto out;
741
742 /* handle card detection interrupts first */
743 card_status = r852_read_reg(dev, R852_CARD_IRQ_STA);
744 r852_write_reg(dev, R852_CARD_IRQ_STA, card_status);
745
746 if (card_status & (R852_CARD_IRQ_INSERT|R852_CARD_IRQ_REMOVE)) {
747
748 ret = IRQ_HANDLED;
749 dev->card_detected = !!(card_status & R852_CARD_IRQ_INSERT);
750
751 /* we shouldn't recieve any interrupts if we wait for card
752 to settle */
753 WARN_ON(dev->card_unstable);
754
755 /* disable irqs while card is unstable */
756 /* this will timeout DMA if active, but better that garbage */
757 r852_disable_irqs(dev);
758
759 if (dev->card_unstable)
760 goto out;
761
762 /* let, card state to settle a bit, and then do the work */
763 dev->card_unstable = 1;
764 queue_delayed_work(dev->card_workqueue,
765 &dev->card_detect_work, msecs_to_jiffies(100));
766 goto out;
767 }
768
769
770 /* Handle dma interrupts */
771 dma_status = r852_read_reg_dword(dev, R852_DMA_IRQ_STA);
772 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, dma_status);
773
774 if (dma_status & R852_DMA_IRQ_MASK) {
775
776 ret = IRQ_HANDLED;
777
778 if (dma_status & R852_DMA_IRQ_ERROR) {
779 dbg("recieved dma error IRQ");
780 r852_dma_done(dev, -EIO);
781 goto out;
782 }
783
784 /* recieved DMA interrupt out of nowhere? */
785 WARN_ON_ONCE(dev->dma_stage == 0);
786
787 if (dev->dma_stage == 0)
788 goto out;
789
790 /* done device access */
791 if (dev->dma_state == DMA_INTERNAL &&
792 (dma_status & R852_DMA_IRQ_INTERNAL)) {
793
794 dev->dma_state = DMA_MEMORY;
795 dev->dma_stage++;
796 }
797
798 /* done memory DMA */
799 if (dev->dma_state == DMA_MEMORY &&
800 (dma_status & R852_DMA_IRQ_MEMORY)) {
801 dev->dma_state = DMA_INTERNAL;
802 dev->dma_stage++;
803 }
804
805 /* Enable 2nd half of dma dance */
806 if (dev->dma_stage == 2)
807 r852_dma_enable(dev);
808
809 /* Operation done */
810 if (dev->dma_stage == 3)
811 r852_dma_done(dev, 0);
812 goto out;
813 }
814
815 /* Handle unknown interrupts */
816 if (dma_status)
817 dbg("bad dma IRQ status = %x", dma_status);
818
819 if (card_status & ~R852_CARD_STA_CD)
820 dbg("strange card status = %x", card_status);
821
822out:
823 spin_unlock_irqrestore(&dev->irqlock, flags);
824 return ret;
825}
826
827int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
828{
829 int error;
830 struct nand_chip *chip;
831 struct r852_device *dev;
832
833 /* pci initialization */
834 error = pci_enable_device(pci_dev);
835
836 if (error)
837 goto error1;
838
839 pci_set_master(pci_dev);
840
841 error = pci_set_dma_mask(pci_dev, DMA_32BIT_MASK);
842 if (error)
843 goto error2;
844
845 error = pci_request_regions(pci_dev, DRV_NAME);
846
847 if (error)
848 goto error3;
849
850 error = -ENOMEM;
851
852 /* init nand chip, but register it only on card insert */
853 chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
854
855 if (!chip)
856 goto error4;
857
858 /* commands */
859 chip->cmd_ctrl = r852_cmdctl;
860 chip->waitfunc = r852_wait;
861 chip->dev_ready = r852_ready;
862
863 /* I/O */
864 chip->read_byte = r852_read_byte;
865 chip->read_buf = r852_read_buf;
866 chip->write_buf = r852_write_buf;
867 chip->verify_buf = r852_verify_buf;
868
869 /* ecc */
870 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
871 chip->ecc.size = R852_DMA_LEN;
872 chip->ecc.bytes = SM_OOB_SIZE;
873 chip->ecc.hwctl = r852_ecc_hwctl;
874 chip->ecc.calculate = r852_ecc_calculate;
875 chip->ecc.correct = r852_ecc_correct;
876
877 /* TODO: hack */
878 chip->ecc.read_oob = r852_read_oob;
879
880 /* init our device structure */
881 dev = kzalloc(sizeof(struct r852_device), GFP_KERNEL);
882
883 if (!dev)
884 goto error5;
885
886 chip->priv = dev;
887 dev->chip = chip;
888 dev->pci_dev = pci_dev;
889 pci_set_drvdata(pci_dev, dev);
890
891 dev->bounce_buffer = pci_alloc_consistent(pci_dev, R852_DMA_LEN,
892 &dev->phys_bounce_buffer);
893
894 if (!dev->bounce_buffer)
895 goto error6;
896
897
898 error = -ENODEV;
899 dev->mmio = pci_ioremap_bar(pci_dev, 0);
900
901 if (!dev->mmio)
902 goto error7;
903
904 error = -ENOMEM;
905 dev->tmp_buffer = kzalloc(SM_SECTOR_SIZE, GFP_KERNEL);
906
907 if (!dev->tmp_buffer)
908 goto error8;
909
910 init_completion(&dev->dma_done);
911
912 dev->card_workqueue = create_freezeable_workqueue(DRV_NAME);
913
914 if (!dev->card_workqueue)
915 goto error9;
916
917 INIT_DELAYED_WORK(&dev->card_detect_work, r852_card_detect_work);
918
919 /* shutdown everything - precation */
920 r852_engine_disable(dev);
921 r852_disable_irqs(dev);
922
923 r852_dma_test(dev);
924
925 /*register irq handler*/
926 error = -ENODEV;
927 if (request_irq(pci_dev->irq, &r852_irq, IRQF_SHARED,
928 DRV_NAME, dev))
929 goto error10;
930
931 dev->irq = pci_dev->irq;
932 spin_lock_init(&dev->irqlock);
933
934 /* kick initial present test */
935 dev->card_detected = 0;
936 r852_card_update_present(dev);
937 queue_delayed_work(dev->card_workqueue,
938 &dev->card_detect_work, 0);
939
940
941 printk(KERN_NOTICE DRV_NAME ": driver loaded succesfully\n");
942 return 0;
943
944error10:
945 destroy_workqueue(dev->card_workqueue);
946error9:
947 kfree(dev->tmp_buffer);
948error8:
949 pci_iounmap(pci_dev, dev->mmio);
950error7:
951 pci_free_consistent(pci_dev, R852_DMA_LEN,
952 dev->bounce_buffer, dev->phys_bounce_buffer);
953error6:
954 kfree(dev);
955error5:
956 kfree(chip);
957error4:
958 pci_release_regions(pci_dev);
959error3:
960error2:
961 pci_disable_device(pci_dev);
962error1:
963 return error;
964}
965
966void r852_remove(struct pci_dev *pci_dev)
967{
968 struct r852_device *dev = pci_get_drvdata(pci_dev);
969
970 /* Stop detect workqueue -
971 we are going to unregister the device anyway*/
972 cancel_delayed_work_sync(&dev->card_detect_work);
973 destroy_workqueue(dev->card_workqueue);
974
975 /* Unregister the device, this might make more IO */
976 r852_unregister_nand_device(dev);
977
978 /* Stop interrupts */
979 r852_disable_irqs(dev);
980 synchronize_irq(dev->irq);
981 free_irq(dev->irq, dev);
982
983 /* Cleanup */
984 kfree(dev->tmp_buffer);
985 pci_iounmap(pci_dev, dev->mmio);
986 pci_free_consistent(pci_dev, R852_DMA_LEN,
987 dev->bounce_buffer, dev->phys_bounce_buffer);
988
989 kfree(dev->chip);
990 kfree(dev);
991
992 /* Shutdown the PCI device */
993 pci_release_regions(pci_dev);
994 pci_disable_device(pci_dev);
995}
996
997void r852_shutdown(struct pci_dev *pci_dev)
998{
999 struct r852_device *dev = pci_get_drvdata(pci_dev);
1000
1001 cancel_delayed_work_sync(&dev->card_detect_work);
1002 r852_disable_irqs(dev);
1003 synchronize_irq(dev->irq);
1004 pci_disable_device(pci_dev);
1005}
1006
1007int r852_suspend(struct device *device)
1008{
1009 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1010 unsigned long flags;
1011
1012 if (dev->ctlreg & R852_CTL_CARDENABLE)
1013 return -EBUSY;
1014
1015 /* First make sure the detect work is gone */
1016 cancel_delayed_work_sync(&dev->card_detect_work);
1017
1018 /* Turn off the interrupts and stop the device */
1019 r852_disable_irqs(dev);
1020 r852_engine_disable(dev);
1021
1022 spin_lock_irqsave(&dev->irqlock, flags);
1023 dev->insuspend = 1;
1024 spin_unlock_irqrestore(&dev->irqlock, flags);
1025
1026 /* At that point, even if interrupt handler is running, it will quit */
1027 /* So wait for this to happen explictly */
1028 synchronize_irq(dev->irq);
1029
1030 /* If card was pulled off just during the suspend, which is very
1031 unlikely, we will remove it on resume, it too late now
1032 anyway... */
1033 dev->card_unstable = 0;
1034
1035 pci_save_state(to_pci_dev(device));
1036 return pci_prepare_to_sleep(to_pci_dev(device));
1037}
1038
1039int r852_resume(struct device *device)
1040{
1041 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1042 unsigned long flags;
1043
1044 /* Turn on the hardware */
1045 pci_back_from_sleep(to_pci_dev(device));
1046 pci_restore_state(to_pci_dev(device));
1047
1048 r852_disable_irqs(dev);
1049 r852_card_update_present(dev);
1050 r852_engine_disable(dev);
1051
1052
1053 /* Now its safe for IRQ to run */
1054 spin_lock_irqsave(&dev->irqlock, flags);
1055 dev->insuspend = 0;
1056 spin_unlock_irqrestore(&dev->irqlock, flags);
1057
1058
1059 /* If card status changed, just do the work */
1060 if (dev->card_detected != dev->card_registred) {
1061 dbg("card was %s during low power state",
1062 dev->card_detected ? "added" : "removed");
1063
1064 queue_delayed_work(dev->card_workqueue,
1065 &dev->card_detect_work, 1000);
1066 return 0;
1067 }
1068
1069 /* Otherwise, initialize the card */
1070 if (dev->card_registred) {
1071 r852_engine_enable(dev);
1072 dev->chip->select_chip(dev->mtd, 0);
1073 dev->chip->cmdfunc(dev->mtd, NAND_CMD_RESET, -1, -1);
1074 dev->chip->select_chip(dev->mtd, -1);
1075 }
1076
1077 /* Program card detection IRQ */
1078 r852_update_card_detect(dev);
1079 return 0;
1080}
1081
1082static const struct pci_device_id r852_pci_id_tbl[] = {
1083
1084 { PCI_VDEVICE(RICOH, PCI_DEVICE_ID_RICOH_R5C852), },
1085 { },
1086};
1087
1088MODULE_DEVICE_TABLE(pci, r852_pci_id_tbl);
1089
1090SIMPLE_DEV_PM_OPS(r852_pm_ops, r852_suspend, r852_resume);
1091
1092
1093static struct pci_driver r852_pci_driver = {
1094 .name = DRV_NAME,
1095 .id_table = r852_pci_id_tbl,
1096 .probe = r852_probe,
1097 .remove = r852_remove,
1098 .shutdown = r852_shutdown,
1099 .driver.pm = &r852_pm_ops,
1100};
1101
1102static __init int r852_module_init(void)
1103{
1104 return pci_register_driver(&r852_pci_driver);
1105}
1106
1107static void __exit r852_module_exit(void)
1108{
1109 pci_unregister_driver(&r852_pci_driver);
1110}
1111
1112module_init(r852_module_init);
1113module_exit(r852_module_exit);
1114
1115MODULE_LICENSE("GPL");
1116MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
1117MODULE_DESCRIPTION("Ricoh 85xx xD/smartmedia card reader driver");
diff --git a/drivers/mtd/nand/r852.h b/drivers/mtd/nand/r852.h
new file mode 100644
index 000000000000..8096cc280c73
--- /dev/null
+++ b/drivers/mtd/nand/r852.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright © 2009 - Maxim Levitsky
3 * driver for Ricoh xD readers
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/pci.h>
11#include <linux/completion.h>
12#include <linux/workqueue.h>
13#include <linux/mtd/nand.h>
14#include <linux/spinlock.h>
15
16
17/* nand interface + ecc
18 byte write/read does one cycle on nand data lines.
19 dword write/read does 4 cycles
20 if R852_CTL_ECC_ACCESS is set in R852_CTL, then dword read reads
21 results of ecc correction, if DMA read was done before.
22 If write was done two dword reads read generated ecc checksums
23*/
24#define R852_DATALINE 0x00
25
26/* control register */
27#define R852_CTL 0x04
28#define R852_CTL_COMMAND 0x01 /* send command (#CLE)*/
29#define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30#define R852_CTL_ON 0x04 /* only seem to controls the hd led, */
31 /* but has to be set on start...*/
32#define R852_CTL_RESET 0x08 /* unknown, set only on start once*/
33#define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
34#define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
35#define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
36#define R852_CTL_WRITE 0x80 /* set when performing writes (#WP) */
37
38/* card detection status */
39#define R852_CARD_STA 0x05
40
41#define R852_CARD_STA_CD 0x01 /* state of #CD line, same as 0x04 */
42#define R852_CARD_STA_RO 0x02 /* card is readonly */
43#define R852_CARD_STA_PRESENT 0x04 /* card is present (#CD) */
44#define R852_CARD_STA_ABSENT 0x08 /* card is absent */
45#define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
46
47/* card detection irq status & enable*/
48#define R852_CARD_IRQ_STA 0x06 /* IRQ status */
49#define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */
50
51#define R852_CARD_IRQ_CD 0x01 /* fire when #CD lights, same as 0x04*/
52#define R852_CARD_IRQ_REMOVE 0x04 /* detect card removal */
53#define R852_CARD_IRQ_INSERT 0x08 /* detect card insert */
54#define R852_CARD_IRQ_UNK1 0x10 /* unknown */
55#define R852_CARD_IRQ_GENABLE 0x80 /* general enable */
56#define R852_CARD_IRQ_MASK 0x1D
57
58
59
60/* hardware enable */
61#define R852_HW 0x08
62#define R852_HW_ENABLED 0x01 /* hw enabled */
63#define R852_HW_UNKNOWN 0x80
64
65
66/* dma capabilities */
67#define R852_DMA_CAP 0x09
68#define R852_SMBIT 0x20 /* if set with bit #6 or bit #7, then */
69 /* hw is smartmedia */
70#define R852_DMA1 0x40 /* if set w/bit #7, dma is supported */
71#define R852_DMA2 0x80 /* if set w/bit #6, dma is supported */
72
73
74/* physical DMA address - 32 bit value*/
75#define R852_DMA_ADDR 0x0C
76
77
78/* dma settings */
79#define R852_DMA_SETTINGS 0x10
80#define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
81#define R852_DMA_READ 0x02 /* 0 = write, 1 = read */
82#define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */
83
84/* dma IRQ status */
85#define R852_DMA_IRQ_STA 0x14
86
87/* dma IRQ enable */
88#define R852_DMA_IRQ_ENABLE 0x18
89
90#define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */
91#define R852_DMA_IRQ_ERROR 0x02 /* error did happen */
92#define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */
93#define R852_DMA_IRQ_MASK 0x07 /* mask of all IRQ bits */
94
95
96/* ECC syndrome format - read from reg #0 will return two copies of these for
97 each half of the page.
98 first byte is error byte location, and second, bit location + flags */
99#define R852_ECC_ERR_BIT_MSK 0x07 /* error bit location */
100#define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */
101#define R852_ECC_CORRECTABLE 0x20 /* correctable error exist */
102#define R852_ECC_FAIL 0x40 /* non correctable error detected */
103
104#define R852_DMA_LEN 512
105
106#define DMA_INTERNAL 0
107#define DMA_MEMORY 1
108
109struct r852_device {
110 void __iomem *mmio; /* mmio */
111 struct mtd_info *mtd; /* mtd backpointer */
112 struct nand_chip *chip; /* nand chip backpointer */
113 struct pci_dev *pci_dev; /* pci backpointer */
114
115 /* dma area */
116 dma_addr_t phys_dma_addr; /* bus address of buffer*/
117 struct completion dma_done; /* data transfer done */
118
119 dma_addr_t phys_bounce_buffer; /* bus address of bounce buffer */
120 uint8_t *bounce_buffer; /* virtual address of bounce buffer */
121
122 int dma_dir; /* 1 = read, 0 = write */
123 int dma_stage; /* 0 - idle, 1 - first step,
124 2 - second step */
125
126 int dma_state; /* 0 = internal, 1 = memory */
127 int dma_error; /* dma errors */
128 int dma_usable; /* is it possible to use dma */
129
130 /* card status area */
131 struct delayed_work card_detect_work;
132 struct workqueue_struct *card_workqueue;
133 int card_registred; /* card registered with mtd */
134 int card_detected; /* card detected in slot */
135 int card_unstable; /* whenever the card is inserted,
136 is not known yet */
137 int readonly; /* card is readonly */
138 int sm; /* Is card smartmedia */
139
140 /* interrupt handling */
141 spinlock_t irqlock; /* IRQ protecting lock */
142 int irq; /* irq num */
143 int insuspend; /* device is suspended */
144
145 /* misc */
146 void *tmp_buffer; /* temporary buffer */
147 uint8_t ctlreg; /* cached contents of control reg */
148};
149
150#define DRV_NAME "r852"
151
152
153#define dbg(format, ...) \
154 if (debug) \
155 printk(KERN_DEBUG DRV_NAME ": " format "\n", ## __VA_ARGS__)
156
157#define dbg_verbose(format, ...) \
158 if (debug > 1) \
159 printk(KERN_DEBUG DRV_NAME ": " format "\n", ## __VA_ARGS__)
160
161
162#define message(format, ...) \
163 printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 03:57:21 -0500