1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 1b06d29dd06b..99dc2be620a6 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -116,6 +116,20 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
         .oobavail = 48,
 };
 
+/*
+ * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
+ * 1, so we have to adjust bad block pattern. This pattern should be used for
+ * x8 chips only. So far hardware does not support x16 chips anyway.
+ */
+static u8 scan_ff_pattern[] = { 0xff, };
+
+static struct nand_bbt_descr largepage_memorybased = {
+        .options = 0,
+        .offs = 0,
+        .len = 1,
+        .pattern = scan_ff_pattern,
+};
+
 /*=================================*/
 
 /*
@@ -687,6 +701,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
                                            &fsl_elbc_oob_lp_eccm1 :
                                            &fsl_elbc_oob_lp_eccm0;
+                        chip->badblock_pattern = &largepage_memorybased;
                         mtd->ecclayout = chip->ecc.layout;
                         mtd->oobavail = chip->ecc.layout->oobavail;
                 }