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path: root/drivers/mtd/onenand/onenand_base.c
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Diffstat (limited to 'drivers/mtd/onenand/onenand_base.c')
-rw-r--r--drivers/mtd/onenand/onenand_base.c39
1 files changed, 37 insertions, 2 deletions
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index bcce22ae3cb1..e87489505772 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -379,6 +379,35 @@ static int onenand_read_bufferram(struct mtd_info *mtd, int area,
379} 379}
380 380
381/** 381/**
382 * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
383 * @param mtd MTD data structure
384 * @param area BufferRAM area
385 * @param buffer the databuffer to put/get data
386 * @param offset offset to read from or write to
387 * @param count number of bytes to read/write
388 *
389 * Read the BufferRAM area with Sync. Burst Mode
390 */
391static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
392 unsigned char *buffer, int offset, size_t count)
393{
394 struct onenand_chip *this = mtd->priv;
395 void __iomem *bufferram;
396
397 bufferram = this->base + area;
398
399 bufferram += onenand_bufferram_offset(mtd, area);
400
401 this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
402
403 memcpy(buffer, bufferram + offset, count);
404
405 this->mmcontrol(mtd, 0);
406
407 return 0;
408}
409
410/**
382 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area 411 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
383 * @param mtd MTD data structure 412 * @param mtd MTD data structure
384 * @param area BufferRAM area 413 * @param area BufferRAM area
@@ -1273,8 +1302,8 @@ static int onenand_check_maf(int manuf)
1273 break; 1302 break;
1274 } 1303 }
1275 1304
1276 printk(KERN_DEBUG "OneNAND Manufacturer: %s\n", 1305 printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n",
1277 onenand_manuf_ids[i].name); 1306 onenand_manuf_ids[i].name, manuf);
1278 1307
1279 return (i != ONENAND_MFR_UNKNOWN); 1308 return (i != ONENAND_MFR_UNKNOWN);
1280} 1309}
@@ -1385,6 +1414,12 @@ int onenand_scan(struct mtd_info *mtd, int maxchips)
1385 if (onenand_probe(mtd)) 1414 if (onenand_probe(mtd))
1386 return -ENXIO; 1415 return -ENXIO;
1387 1416
1417 /* Set Sync. Burst Read after probing */
1418 if (this->mmcontrol) {
1419 printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
1420 this->read_bufferram = onenand_sync_read_bufferram;
1421 }
1422
1388 this->state = FL_READY; 1423 this->state = FL_READY;
1389 init_waitqueue_head(&this->wq); 1424 init_waitqueue_head(&this->wq);
1390 spin_lock_init(&this->chip_lock); 1425 spin_lock_init(&this->chip_lock);