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-rw-r--r--drivers/mtd/nand/Kconfig13
-rw-r--r--drivers/mtd/nand/Makefile2
-rw-r--r--drivers/mtd/nand/autcpu12.c237
-rw-r--r--drivers/mtd/nand/spia.c176
4 files changed, 0 insertions, 428 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4883139460be..531807dec6b3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -49,13 +49,6 @@ config MTD_NAND_MUSEUM_IDS
49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs 49 NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
50 of these chips were reused by later, larger chips. 50 of these chips were reused by later, larger chips.
51 51
52config MTD_NAND_AUTCPU12
53 tristate "SmartMediaCard on autronix autcpu12 board"
54 depends on ARCH_AUTCPU12
55 help
56 This enables the driver for the autronix autcpu12 board to
57 access the SmartMediaCard.
58
59config MTD_NAND_DENALI 52config MTD_NAND_DENALI
60 depends on PCI 53 depends on PCI
61 tristate "Support Denali NAND controller on Intel Moorestown" 54 tristate "Support Denali NAND controller on Intel Moorestown"
@@ -86,12 +79,6 @@ config MTD_NAND_GPIO
86 help 79 help
87 This enables a GPIO based NAND flash driver. 80 This enables a GPIO based NAND flash driver.
88 81
89config MTD_NAND_SPIA
90 tristate "NAND Flash device on SPIA board"
91 depends on ARCH_P720T
92 help
93 If you had to ask, you don't have one. Say 'N'.
94
95config MTD_NAND_AMS_DELTA 82config MTD_NAND_AMS_DELTA
96 tristate "NAND Flash device on Amstrad E3" 83 tristate "NAND Flash device on Amstrad E3"
97 depends on MACH_AMS_DELTA 84 depends on MACH_AMS_DELTA
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2cbd0916b733..6c7f2b3ca8ae 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -9,9 +9,7 @@ obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
9obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o 9obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
10 10
11obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o 11obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
12obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
13obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o 12obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
14obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
15obj-$(CONFIG_MTD_NAND_DENALI) += denali.o 13obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
16obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o 14obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
17obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o 15obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
diff --git a/drivers/mtd/nand/autcpu12.c b/drivers/mtd/nand/autcpu12.c
deleted file mode 100644
index 04769a49a7cb..000000000000
--- a/drivers/mtd/nand/autcpu12.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/*
2 * drivers/mtd/autcpu12.c
3 *
4 * Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
5 *
6 * Derived from drivers/mtd/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the NAND flash device found on the
15 * autronix autcpu12 board, which is a SmartMediaCard. It supports
16 * 16MiB, 32MiB and 64MiB cards.
17 *
18 *
19 * 02-12-2002 TG Cleanup of module params
20 *
21 * 02-20-2002 TG adjusted for different rd/wr address support
22 * added support for read device ready/busy line
23 * added page_cache
24 *
25 * 10-06-2002 TG 128K card support added
26 */
27
28#include <linux/slab.h>
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <asm/io.h>
35#include <mach/hardware.h>
36#include <asm/sizes.h>
37#include <mach/autcpu12.h>
38
39/*
40 * MTD structure for AUTCPU12 board
41 */
42static struct mtd_info *autcpu12_mtd = NULL;
43static void __iomem *autcpu12_fio_base;
44
45/*
46 * Define partitions for flash devices
47 */
48static struct mtd_partition partition_info16k[] = {
49 { .name = "AUTCPU12 flash partition 1",
50 .offset = 0,
51 .size = 8 * SZ_1M },
52 { .name = "AUTCPU12 flash partition 2",
53 .offset = 8 * SZ_1M,
54 .size = 8 * SZ_1M },
55};
56
57static struct mtd_partition partition_info32k[] = {
58 { .name = "AUTCPU12 flash partition 1",
59 .offset = 0,
60 .size = 8 * SZ_1M },
61 { .name = "AUTCPU12 flash partition 2",
62 .offset = 8 * SZ_1M,
63 .size = 24 * SZ_1M },
64};
65
66static struct mtd_partition partition_info64k[] = {
67 { .name = "AUTCPU12 flash partition 1",
68 .offset = 0,
69 .size = 16 * SZ_1M },
70 { .name = "AUTCPU12 flash partition 2",
71 .offset = 16 * SZ_1M,
72 .size = 48 * SZ_1M },
73};
74
75static struct mtd_partition partition_info128k[] = {
76 { .name = "AUTCPU12 flash partition 1",
77 .offset = 0,
78 .size = 16 * SZ_1M },
79 { .name = "AUTCPU12 flash partition 2",
80 .offset = 16 * SZ_1M,
81 .size = 112 * SZ_1M },
82};
83
84#define NUM_PARTITIONS16K 2
85#define NUM_PARTITIONS32K 2
86#define NUM_PARTITIONS64K 2
87#define NUM_PARTITIONS128K 2
88/*
89 * hardware specific access to control-lines
90 *
91 * ALE bit 4 autcpu12_pedr
92 * CLE bit 5 autcpu12_pedr
93 * NCE bit 0 fio_ctrl
94 *
95 */
96static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
97 unsigned int ctrl)
98{
99 struct nand_chip *chip = mtd->priv;
100
101 if (ctrl & NAND_CTRL_CHANGE) {
102 void __iomem *addr;
103 unsigned char bits;
104
105 bits = clps_readb(AUTCPU12_SMC_PORT_OFFSET) & ~0x30;
106 bits |= (ctrl & NAND_CLE) << 4;
107 bits |= (ctrl & NAND_ALE) << 2;
108 clps_writeb(bits, AUTCPU12_SMC_PORT_OFFSET);
109
110 addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
111 writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
112 }
113
114 if (cmd != NAND_CMD_NONE)
115 writeb(cmd, chip->IO_ADDR_W);
116}
117
118/*
119 * read device ready pin
120 */
121int autcpu12_device_ready(struct mtd_info *mtd)
122{
123 return clps_readb(AUTCPU12_SMC_PORT_OFFSET) & AUTCPU12_SMC_RDY;
124}
125
126/*
127 * Main initialization routine
128 */
129static int __init autcpu12_init(void)
130{
131 struct nand_chip *this;
132 int err = 0;
133
134 /* Allocate memory for MTD device structure and private data */
135 autcpu12_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
136 GFP_KERNEL);
137 if (!autcpu12_mtd) {
138 printk("Unable to allocate AUTCPU12 NAND MTD device structure.\n");
139 err = -ENOMEM;
140 goto out;
141 }
142
143 /* map physical address */
144 autcpu12_fio_base = ioremap(AUTCPU12_PHYS_SMC, SZ_1K);
145 if (!autcpu12_fio_base) {
146 printk("Ioremap autcpu12 SmartMedia Card failed\n");
147 err = -EIO;
148 goto out_mtd;
149 }
150
151 /* Get pointer to private data */
152 this = (struct nand_chip *)(&autcpu12_mtd[1]);
153
154 /* Initialize structures */
155 memset(autcpu12_mtd, 0, sizeof(struct mtd_info));
156 memset(this, 0, sizeof(struct nand_chip));
157
158 /* Link the private data with the MTD structure */
159 autcpu12_mtd->priv = this;
160 autcpu12_mtd->owner = THIS_MODULE;
161
162 /* Set address of NAND IO lines */
163 this->IO_ADDR_R = autcpu12_fio_base;
164 this->IO_ADDR_W = autcpu12_fio_base;
165 this->cmd_ctrl = autcpu12_hwcontrol;
166 this->dev_ready = autcpu12_device_ready;
167 /* 20 us command delay time */
168 this->chip_delay = 20;
169 this->ecc.mode = NAND_ECC_SOFT;
170
171 /* Enable the following for a flash based bad block table */
172 /*
173 this->bbt_options = NAND_BBT_USE_FLASH;
174 */
175 this->bbt_options = NAND_BBT_USE_FLASH;
176
177 /* Scan to find existence of the device */
178 if (nand_scan(autcpu12_mtd, 1)) {
179 err = -ENXIO;
180 goto out_ior;
181 }
182
183 /* Register the partitions */
184 switch (autcpu12_mtd->size) {
185 case SZ_16M:
186 mtd_device_register(autcpu12_mtd, partition_info16k,
187 NUM_PARTITIONS16K);
188 break;
189 case SZ_32M:
190 mtd_device_register(autcpu12_mtd, partition_info32k,
191 NUM_PARTITIONS32K);
192 break;
193 case SZ_64M:
194 mtd_device_register(autcpu12_mtd, partition_info64k,
195 NUM_PARTITIONS64K);
196 break;
197 case SZ_128M:
198 mtd_device_register(autcpu12_mtd, partition_info128k,
199 NUM_PARTITIONS128K);
200 break;
201 default:
202 printk("Unsupported SmartMedia device\n");
203 err = -ENXIO;
204 goto out_ior;
205 }
206 goto out;
207
208 out_ior:
209 iounmap(autcpu12_fio_base);
210 out_mtd:
211 kfree(autcpu12_mtd);
212 out:
213 return err;
214}
215
216module_init(autcpu12_init);
217
218/*
219 * Clean up routine
220 */
221static void __exit autcpu12_cleanup(void)
222{
223 /* Release resources, unregister device */
224 nand_release(autcpu12_mtd);
225
226 /* unmap physical address */
227 iounmap(autcpu12_fio_base);
228
229 /* Free the MTD device structure */
230 kfree(autcpu12_mtd);
231}
232
233module_exit(autcpu12_cleanup);
234
235MODULE_LICENSE("GPL");
236MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
237MODULE_DESCRIPTION("Glue layer for SmartMediaCard on autronix autcpu12");
diff --git a/drivers/mtd/nand/spia.c b/drivers/mtd/nand/spia.c
deleted file mode 100644
index bef76cd7c24c..000000000000
--- a/drivers/mtd/nand/spia.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/*
2 * drivers/mtd/nand/spia.c
3 *
4 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
5 *
6 *
7 * 10-29-2001 TG change to support hardwarespecific access
8 * to controllines (due to change in nand.c)
9 * page_cache added
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Overview:
16 * This is a device driver for the NAND flash device found on the
17 * SPIA board which utilizes the Toshiba TC58V64AFT part. This is
18 * a 64Mibit (8MiB x 8 bits) NAND flash device.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/partitions.h>
28#include <asm/io.h>
29
30/*
31 * MTD structure for SPIA board
32 */
33static struct mtd_info *spia_mtd = NULL;
34
35/*
36 * Values specific to the SPIA board (used with EP7212 processor)
37 */
38#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */
39#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */
40#define SPIA_PEDR 0x0080 /*
41 * IO offset to Port E data register
42 * where the CLE, ALE and NCE pins
43 * are wired to.
44 */
45#define SPIA_PEDDR 0x00c0 /*
46 * IO offset to Port E data direction
47 * register so we can control the IO
48 * lines.
49 */
50
51/*
52 * Module stuff
53 */
54
55static int spia_io_base = SPIA_IO_BASE;
56static int spia_fio_base = SPIA_FIO_BASE;
57static int spia_pedr = SPIA_PEDR;
58static int spia_peddr = SPIA_PEDDR;
59
60module_param(spia_io_base, int, 0);
61module_param(spia_fio_base, int, 0);
62module_param(spia_pedr, int, 0);
63module_param(spia_peddr, int, 0);
64
65/*
66 * Define partitions for flash device
67 */
68static const struct mtd_partition partition_info[] = {
69 {
70 .name = "SPIA flash partition 1",
71 .offset = 0,
72 .size = 2 * 1024 * 1024},
73 {
74 .name = "SPIA flash partition 2",
75 .offset = 2 * 1024 * 1024,
76 .size = 6 * 1024 * 1024}
77};
78
79#define NUM_PARTITIONS 2
80
81/*
82 * hardware specific access to control-lines
83 *
84 * ctrl:
85 * NAND_CNE: bit 0 -> bit 2
86 * NAND_CLE: bit 1 -> bit 0
87 * NAND_ALE: bit 2 -> bit 1
88 */
89static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
90{
91 struct nand_chip *chip = mtd->priv;
92
93 if (ctrl & NAND_CTRL_CHANGE) {
94 void __iomem *addr = spia_io_base + spia_pedr;
95 unsigned char bits;
96
97 bits = (ctrl & NAND_CNE) << 2;
98 bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
99 writeb((readb(addr) & ~0x7) | bits, addr);
100 }
101
102 if (cmd != NAND_CMD_NONE)
103 writeb(cmd, chip->IO_ADDR_W);
104}
105
106/*
107 * Main initialization routine
108 */
109static int __init spia_init(void)
110{
111 struct nand_chip *this;
112
113 /* Allocate memory for MTD device structure and private data */
114 spia_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
115 if (!spia_mtd) {
116 printk("Unable to allocate SPIA NAND MTD device structure.\n");
117 return -ENOMEM;
118 }
119
120 /* Get pointer to private data */
121 this = (struct nand_chip *)(&spia_mtd[1]);
122
123 /* Initialize structures */
124 memset(spia_mtd, 0, sizeof(struct mtd_info));
125 memset(this, 0, sizeof(struct nand_chip));
126
127 /* Link the private data with the MTD structure */
128 spia_mtd->priv = this;
129 spia_mtd->owner = THIS_MODULE;
130
131 /*
132 * Set GPIO Port E control register so that the pins are configured
133 * to be outputs for controlling the NAND flash.
134 */
135 (*(volatile unsigned char *)(spia_io_base + spia_peddr)) = 0x07;
136
137 /* Set address of NAND IO lines */
138 this->IO_ADDR_R = (void __iomem *)spia_fio_base;
139 this->IO_ADDR_W = (void __iomem *)spia_fio_base;
140 /* Set address of hardware control function */
141 this->cmd_ctrl = spia_hwcontrol;
142 /* 15 us command delay time */
143 this->chip_delay = 15;
144
145 /* Scan to find existence of the device */
146 if (nand_scan(spia_mtd, 1)) {
147 kfree(spia_mtd);
148 return -ENXIO;
149 }
150
151 /* Register the partitions */
152 mtd_device_register(spia_mtd, partition_info, NUM_PARTITIONS);
153
154 /* Return happy */
155 return 0;
156}
157
158module_init(spia_init);
159
160/*
161 * Clean up routine
162 */
163static void __exit spia_cleanup(void)
164{
165 /* Release resources, unregister device */
166 nand_release(spia_mtd);
167
168 /* Free the MTD device structure */
169 kfree(spia_mtd);
170}
171
172module_exit(spia_cleanup);
173
174MODULE_LICENSE("GPL");
175MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");
176MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on SPIA board");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 03:23:46 -0500