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-rw-r--r--drivers/mtd/nand/Kconfig26
-rw-r--r--drivers/mtd/nand/Makefile3
-rw-r--r--drivers/mtd/nand/at91_nand.c12
-rw-r--r--drivers/mtd/nand/bf5xx_nand.c39
-rw-r--r--drivers/mtd/nand/cafe_nand.c19
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c1244
-rw-r--r--drivers/mtd/nand/nand_base.c8
-rw-r--r--drivers/mtd/nand/orion_nand.c171
-rw-r--r--drivers/mtd/nand/pasemi_nand.c243
-rw-r--r--drivers/mtd/nand/plat_nand.c2
-rw-r--r--drivers/mtd/nand/s3c2410.c48
11 files changed, 1780 insertions, 35 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 246d4512f64b..4a3c6759492b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -93,7 +93,7 @@ config MTD_NAND_AU1550
93 93
94config MTD_NAND_BF5XX 94config MTD_NAND_BF5XX
95 tristate "Blackfin on-chip NAND Flash Controller driver" 95 tristate "Blackfin on-chip NAND Flash Controller driver"
96 depends on BF54x && MTD_NAND 96 depends on (BF54x || BF52x) && MTD_NAND
97 help 97 help
98 This enables the Blackfin on-chip NAND flash controller 98 This enables the Blackfin on-chip NAND flash controller
99 99
@@ -283,6 +283,12 @@ config MTD_NAND_CM_X270
283 tristate "Support for NAND Flash on CM-X270 modules" 283 tristate "Support for NAND Flash on CM-X270 modules"
284 depends on MTD_NAND && MACH_ARMCORE 284 depends on MTD_NAND && MACH_ARMCORE
285 285
286config MTD_NAND_PASEMI
287 tristate "NAND support for PA Semi PWRficient"
288 depends on MTD_NAND && PPC_PASEMI
289 help
290 Enables support for NAND Flash interface on PA Semi PWRficient
291 based boards
286 292
287config MTD_NAND_NANDSIM 293config MTD_NAND_NANDSIM
288 tristate "Support for NAND Flash Simulator" 294 tristate "Support for NAND Flash Simulator"
@@ -306,4 +312,22 @@ config MTD_ALAUDA
306 These two (and possibly other) Alauda-based cardreaders for 312 These two (and possibly other) Alauda-based cardreaders for
307 SmartMedia and xD allow raw flash access. 313 SmartMedia and xD allow raw flash access.
308 314
315config MTD_NAND_ORION
316 tristate "NAND Flash support for Marvell Orion SoC"
317 depends on ARCH_ORION && MTD_NAND
318 help
319 This enables the NAND flash controller on Orion machines.
320
321 No board specific support is done by this driver, each board
322 must advertise a platform_device for the driver to attach.
323
324config MTD_NAND_FSL_ELBC
325 tristate "NAND support for Freescale eLBC controllers"
326 depends on MTD_NAND && PPC_OF
327 help
328 Various Freescale chips, including the 8313, include a NAND Flash
329 Controller Module with built-in hardware ECC capabilities.
330 Enabling this option will enable you to use this to control
331 external NAND devices.
332
309endif # MTD_NAND 333endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 3ad6c0165da3..80d575eeee96 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -29,5 +29,8 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
29obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o 29obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
30obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o 30obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
31obj-$(CONFIG_MTD_ALAUDA) += alauda.o 31obj-$(CONFIG_MTD_ALAUDA) += alauda.o
32obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
33obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
34obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
32 35
33nand-objs := nand_base.o nand_bbt.o 36nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/at91_nand.c b/drivers/mtd/nand/at91_nand.c
index b2a5672df6e0..c9fb2acf4056 100644
--- a/drivers/mtd/nand/at91_nand.c
+++ b/drivers/mtd/nand/at91_nand.c
@@ -156,14 +156,14 @@ static int __init at91_nand_probe(struct platform_device *pdev)
156 } 156 }
157 157
158#ifdef CONFIG_MTD_PARTITIONS 158#ifdef CONFIG_MTD_PARTITIONS
159 if (host->board->partition_info)
160 partitions = host->board->partition_info(mtd->size, &num_partitions);
161#ifdef CONFIG_MTD_CMDLINE_PARTS 159#ifdef CONFIG_MTD_CMDLINE_PARTS
162 else { 160 mtd->name = "at91_nand";
163 mtd->name = "at91_nand"; 161 num_partitions = parse_mtd_partitions(mtd, part_probes,
164 num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0); 162 &partitions, 0);
165 }
166#endif 163#endif
164 if (num_partitions <= 0 && host->board->partition_info)
165 partitions = host->board->partition_info(mtd->size,
166 &num_partitions);
167 167
168 if ((!partitions) || (num_partitions == 0)) { 168 if ((!partitions) || (num_partitions == 0)) {
169 printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n"); 169 printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index a52f3a737c39..747042ab094a 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -74,7 +74,22 @@ static int hardware_ecc = 1;
74static int hardware_ecc; 74static int hardware_ecc;
75#endif 75#endif
76 76
77static unsigned short bfin_nfc_pin_req[] = {P_NAND_CE, P_NAND_RB, 0}; 77static unsigned short bfin_nfc_pin_req[] =
78 {P_NAND_CE,
79 P_NAND_RB,
80 P_NAND_D0,
81 P_NAND_D1,
82 P_NAND_D2,
83 P_NAND_D3,
84 P_NAND_D4,
85 P_NAND_D5,
86 P_NAND_D6,
87 P_NAND_D7,
88 P_NAND_WE,
89 P_NAND_RE,
90 P_NAND_CLE,
91 P_NAND_ALE,
92 0};
78 93
79/* 94/*
80 * Data structures for bf5xx nand flash controller driver 95 * Data structures for bf5xx nand flash controller driver
@@ -278,7 +293,6 @@ static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
278 u16 ecc0, ecc1; 293 u16 ecc0, ecc1;
279 u32 code[2]; 294 u32 code[2];
280 u8 *p; 295 u8 *p;
281 int bytes = 3, i;
282 296
283 /* first 4 bytes ECC code for 256 page size */ 297 /* first 4 bytes ECC code for 256 page size */
284 ecc0 = bfin_read_NFC_ECC0(); 298 ecc0 = bfin_read_NFC_ECC0();
@@ -288,19 +302,24 @@ static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
288 302
289 dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]); 303 dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
290 304
305 /* first 3 bytes in ecc_code for 256 page size */
306 p = (u8 *) code;
307 memcpy(ecc_code, p, 3);
308
291 /* second 4 bytes ECC code for 512 page size */ 309 /* second 4 bytes ECC code for 512 page size */
292 if (page_size == 512) { 310 if (page_size == 512) {
293 ecc0 = bfin_read_NFC_ECC2(); 311 ecc0 = bfin_read_NFC_ECC2();
294 ecc1 = bfin_read_NFC_ECC3(); 312 ecc1 = bfin_read_NFC_ECC3();
295 code[1] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11); 313 code[1] = (ecc0 & 0x3FF) | ((ecc1 & 0x3FF) << 11);
296 bytes = 6; 314
315 /* second 3 bytes in ecc_code for second 256
316 * bytes of 512 page size
317 */
318 p = (u8 *) (code + 1);
319 memcpy((ecc_code + 3), p, 3);
297 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]); 320 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
298 } 321 }
299 322
300 p = (u8 *)code;
301 for (i = 0; i < bytes; i++)
302 ecc_code[i] = p[i];
303
304 return 0; 323 return 0;
305} 324}
306 325
@@ -507,12 +526,13 @@ static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
507 526
508 init_completion(&info->dma_completion); 527 init_completion(&info->dma_completion);
509 528
529#ifdef CONFIG_BF54x
510 /* Setup DMAC1 channel mux for NFC which shared with SDH */ 530 /* Setup DMAC1 channel mux for NFC which shared with SDH */
511 val = bfin_read_DMAC1_PERIMUX(); 531 val = bfin_read_DMAC1_PERIMUX();
512 val &= 0xFFFE; 532 val &= 0xFFFE;
513 bfin_write_DMAC1_PERIMUX(val); 533 bfin_write_DMAC1_PERIMUX(val);
514 SSYNC(); 534 SSYNC();
515 535#endif
516 /* Request NFC DMA channel */ 536 /* Request NFC DMA channel */
517 ret = request_dma(CH_NFC, "BF5XX NFC driver"); 537 ret = request_dma(CH_NFC, "BF5XX NFC driver");
518 if (ret < 0) { 538 if (ret < 0) {
@@ -744,9 +764,6 @@ static int bf5xx_nand_resume(struct platform_device *dev)
744{ 764{
745 struct bf5xx_nand_info *info = platform_get_drvdata(dev); 765 struct bf5xx_nand_info *info = platform_get_drvdata(dev);
746 766
747 if (info)
748 bf5xx_nand_hw_init(info);
749
750 return 0; 767 return 0;
751} 768}
752 769
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index 1e811715211a..da6ceaa80ba1 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -11,6 +11,7 @@
11#undef DEBUG 11#undef DEBUG
12#include <linux/mtd/mtd.h> 12#include <linux/mtd/mtd.h>
13#include <linux/mtd/nand.h> 13#include <linux/mtd/nand.h>
14#include <linux/mtd/partitions.h>
14#include <linux/rslib.h> 15#include <linux/rslib.h>
15#include <linux/pci.h> 16#include <linux/pci.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
@@ -52,6 +53,7 @@
52 53
53struct cafe_priv { 54struct cafe_priv {
54 struct nand_chip nand; 55 struct nand_chip nand;
56 struct mtd_partition *parts;
55 struct pci_dev *pdev; 57 struct pci_dev *pdev;
56 void __iomem *mmio; 58 void __iomem *mmio;
57 struct rs_control *rs; 59 struct rs_control *rs;
@@ -84,6 +86,10 @@ static unsigned int numtimings;
84static int timing[3]; 86static int timing[3];
85module_param_array(timing, int, &numtimings, 0644); 87module_param_array(timing, int, &numtimings, 0644);
86 88
89#ifdef CONFIG_MTD_PARTITIONS
90static const char *part_probes[] = { "RedBoot", NULL };
91#endif
92
87/* Hrm. Why isn't this already conditional on something in the struct device? */ 93/* Hrm. Why isn't this already conditional on something in the struct device? */
88#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) 94#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
89 95
@@ -620,7 +626,9 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
620{ 626{
621 struct mtd_info *mtd; 627 struct mtd_info *mtd;
622 struct cafe_priv *cafe; 628 struct cafe_priv *cafe;
629 struct mtd_partition *parts;
623 uint32_t ctrl; 630 uint32_t ctrl;
631 int nr_parts;
624 int err = 0; 632 int err = 0;
625 633
626 /* Very old versions shared the same PCI ident for all three 634 /* Very old versions shared the same PCI ident for all three
@@ -787,7 +795,18 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
787 goto out_irq; 795 goto out_irq;
788 796
789 pci_set_drvdata(pdev, mtd); 797 pci_set_drvdata(pdev, mtd);
798
799 /* We register the whole device first, separate from the partitions */
790 add_mtd_device(mtd); 800 add_mtd_device(mtd);
801
802#ifdef CONFIG_MTD_PARTITIONS
803 nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
804 if (nr_parts > 0) {
805 cafe->parts = parts;
806 dev_info(&cafe->pdev->dev, "%d RedBoot partitions found\n", nr_parts);
807 add_mtd_partitions(mtd, parts, nr_parts);
808 }
809#endif
791 goto out; 810 goto out;
792 811
793 out_irq: 812 out_irq:
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
new file mode 100644
index 000000000000..b025dfe0b274
--- /dev/null
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -0,0 +1,1244 @@
1/* Freescale Enhanced Local Bus Controller NAND driver
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/ioport.h>
29#include <linux/of_platform.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/nand.h>
35#include <linux/mtd/nand_ecc.h>
36#include <linux/mtd/partitions.h>
37
38#include <asm/io.h>
39
40
41#define MAX_BANKS 8
42#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
43#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
44
45struct elbc_bank {
46 __be32 br; /**< Base Register */
47#define BR_BA 0xFFFF8000
48#define BR_BA_SHIFT 15
49#define BR_PS 0x00001800
50#define BR_PS_SHIFT 11
51#define BR_PS_8 0x00000800 /* Port Size 8 bit */
52#define BR_PS_16 0x00001000 /* Port Size 16 bit */
53#define BR_PS_32 0x00001800 /* Port Size 32 bit */
54#define BR_DECC 0x00000600
55#define BR_DECC_SHIFT 9
56#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
57#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
58#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
59#define BR_WP 0x00000100
60#define BR_WP_SHIFT 8
61#define BR_MSEL 0x000000E0
62#define BR_MSEL_SHIFT 5
63#define BR_MS_GPCM 0x00000000 /* GPCM */
64#define BR_MS_FCM 0x00000020 /* FCM */
65#define BR_MS_SDRAM 0x00000060 /* SDRAM */
66#define BR_MS_UPMA 0x00000080 /* UPMA */
67#define BR_MS_UPMB 0x000000A0 /* UPMB */
68#define BR_MS_UPMC 0x000000C0 /* UPMC */
69#define BR_V 0x00000001
70#define BR_V_SHIFT 0
71#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
72
73 __be32 or; /**< Base Register */
74#define OR0 0x5004
75#define OR1 0x500C
76#define OR2 0x5014
77#define OR3 0x501C
78#define OR4 0x5024
79#define OR5 0x502C
80#define OR6 0x5034
81#define OR7 0x503C
82
83#define OR_FCM_AM 0xFFFF8000
84#define OR_FCM_AM_SHIFT 15
85#define OR_FCM_BCTLD 0x00001000
86#define OR_FCM_BCTLD_SHIFT 12
87#define OR_FCM_PGS 0x00000400
88#define OR_FCM_PGS_SHIFT 10
89#define OR_FCM_CSCT 0x00000200
90#define OR_FCM_CSCT_SHIFT 9
91#define OR_FCM_CST 0x00000100
92#define OR_FCM_CST_SHIFT 8
93#define OR_FCM_CHT 0x00000080
94#define OR_FCM_CHT_SHIFT 7
95#define OR_FCM_SCY 0x00000070
96#define OR_FCM_SCY_SHIFT 4
97#define OR_FCM_SCY_1 0x00000010
98#define OR_FCM_SCY_2 0x00000020
99#define OR_FCM_SCY_3 0x00000030
100#define OR_FCM_SCY_4 0x00000040
101#define OR_FCM_SCY_5 0x00000050
102#define OR_FCM_SCY_6 0x00000060
103#define OR_FCM_SCY_7 0x00000070
104#define OR_FCM_RST 0x00000008
105#define OR_FCM_RST_SHIFT 3
106#define OR_FCM_TRLX 0x00000004
107#define OR_FCM_TRLX_SHIFT 2
108#define OR_FCM_EHTR 0x00000002
109#define OR_FCM_EHTR_SHIFT 1
110};
111
112struct elbc_regs {
113 struct elbc_bank bank[8];
114 u8 res0[0x28];
115 __be32 mar; /**< UPM Address Register */
116 u8 res1[0x4];
117 __be32 mamr; /**< UPMA Mode Register */
118 __be32 mbmr; /**< UPMB Mode Register */
119 __be32 mcmr; /**< UPMC Mode Register */
120 u8 res2[0x8];
121 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
122 __be32 mdr; /**< UPM Data Register */
123 u8 res3[0x4];
124 __be32 lsor; /**< Special Operation Initiation Register */
125 __be32 lsdmr; /**< SDRAM Mode Register */
126 u8 res4[0x8];
127 __be32 lurt; /**< UPM Refresh Timer */
128 __be32 lsrt; /**< SDRAM Refresh Timer */
129 u8 res5[0x8];
130 __be32 ltesr; /**< Transfer Error Status Register */
131#define LTESR_BM 0x80000000
132#define LTESR_FCT 0x40000000
133#define LTESR_PAR 0x20000000
134#define LTESR_WP 0x04000000
135#define LTESR_ATMW 0x00800000
136#define LTESR_ATMR 0x00400000
137#define LTESR_CS 0x00080000
138#define LTESR_CC 0x00000001
139#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
140 __be32 ltedr; /**< Transfer Error Disable Register */
141 __be32 lteir; /**< Transfer Error Interrupt Register */
142 __be32 lteatr; /**< Transfer Error Attributes Register */
143 __be32 ltear; /**< Transfer Error Address Register */
144 u8 res6[0xC];
145 __be32 lbcr; /**< Configuration Register */
146#define LBCR_LDIS 0x80000000
147#define LBCR_LDIS_SHIFT 31
148#define LBCR_BCTLC 0x00C00000
149#define LBCR_BCTLC_SHIFT 22
150#define LBCR_AHD 0x00200000
151#define LBCR_LPBSE 0x00020000
152#define LBCR_LPBSE_SHIFT 17
153#define LBCR_EPAR 0x00010000
154#define LBCR_EPAR_SHIFT 16
155#define LBCR_BMT 0x0000FF00
156#define LBCR_BMT_SHIFT 8
157#define LBCR_INIT 0x00040000
158 __be32 lcrr; /**< Clock Ratio Register */
159#define LCRR_DBYP 0x80000000
160#define LCRR_DBYP_SHIFT 31
161#define LCRR_BUFCMDC 0x30000000
162#define LCRR_BUFCMDC_SHIFT 28
163#define LCRR_ECL 0x03000000
164#define LCRR_ECL_SHIFT 24
165#define LCRR_EADC 0x00030000
166#define LCRR_EADC_SHIFT 16
167#define LCRR_CLKDIV 0x0000000F
168#define LCRR_CLKDIV_SHIFT 0
169 u8 res7[0x8];
170 __be32 fmr; /**< Flash Mode Register */
171#define FMR_CWTO 0x0000F000
172#define FMR_CWTO_SHIFT 12
173#define FMR_BOOT 0x00000800
174#define FMR_ECCM 0x00000100
175#define FMR_AL 0x00000030
176#define FMR_AL_SHIFT 4
177#define FMR_OP 0x00000003
178#define FMR_OP_SHIFT 0
179 __be32 fir; /**< Flash Instruction Register */
180#define FIR_OP0 0xF0000000
181#define FIR_OP0_SHIFT 28
182#define FIR_OP1 0x0F000000
183#define FIR_OP1_SHIFT 24
184#define FIR_OP2 0x00F00000
185#define FIR_OP2_SHIFT 20
186#define FIR_OP3 0x000F0000
187#define FIR_OP3_SHIFT 16
188#define FIR_OP4 0x0000F000
189#define FIR_OP4_SHIFT 12
190#define FIR_OP5 0x00000F00
191#define FIR_OP5_SHIFT 8
192#define FIR_OP6 0x000000F0
193#define FIR_OP6_SHIFT 4
194#define FIR_OP7 0x0000000F
195#define FIR_OP7_SHIFT 0
196#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
197#define FIR_OP_CA 0x1 /* Issue current column address */
198#define FIR_OP_PA 0x2 /* Issue current block+page address */
199#define FIR_OP_UA 0x3 /* Issue user defined address */
200#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
201#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
202#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
203#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
204#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
205#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
206#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
207#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
208#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
209#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
210#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
211#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
212 __be32 fcr; /**< Flash Command Register */
213#define FCR_CMD0 0xFF000000
214#define FCR_CMD0_SHIFT 24
215#define FCR_CMD1 0x00FF0000
216#define FCR_CMD1_SHIFT 16
217#define FCR_CMD2 0x0000FF00
218#define FCR_CMD2_SHIFT 8
219#define FCR_CMD3 0x000000FF
220#define FCR_CMD3_SHIFT 0
221 __be32 fbar; /**< Flash Block Address Register */
222#define FBAR_BLK 0x00FFFFFF
223 __be32 fpar; /**< Flash Page Address Register */
224#define FPAR_SP_PI 0x00007C00
225#define FPAR_SP_PI_SHIFT 10
226#define FPAR_SP_MS 0x00000200
227#define FPAR_SP_CI 0x000001FF
228#define FPAR_SP_CI_SHIFT 0
229#define FPAR_LP_PI 0x0003F000
230#define FPAR_LP_PI_SHIFT 12
231#define FPAR_LP_MS 0x00000800
232#define FPAR_LP_CI 0x000007FF
233#define FPAR_LP_CI_SHIFT 0
234 __be32 fbcr; /**< Flash Byte Count Register */
235#define FBCR_BC 0x00000FFF
236 u8 res11[0x8];
237 u8 res8[0xF00];
238};
239
240struct fsl_elbc_ctrl;
241
242/* mtd information per set */
243
244struct fsl_elbc_mtd {
245 struct mtd_info mtd;
246 struct nand_chip chip;
247 struct fsl_elbc_ctrl *ctrl;
248
249 struct device *dev;
250 int bank; /* Chip select bank number */
251 u8 __iomem *vbase; /* Chip select base virtual address */
252 int page_size; /* NAND page size (0=512, 1=2048) */
253 unsigned int fmr; /* FCM Flash Mode Register value */
254};
255
256/* overview of the fsl elbc controller */
257
258struct fsl_elbc_ctrl {
259 struct nand_hw_control controller;
260 struct fsl_elbc_mtd *chips[MAX_BANKS];
261
262 /* device info */
263 struct device *dev;
264 struct elbc_regs __iomem *regs;
265 int irq;
266 wait_queue_head_t irq_wait;
267 unsigned int irq_status; /* status read from LTESR by irq handler */
268 u8 __iomem *addr; /* Address of assigned FCM buffer */
269 unsigned int page; /* Last page written to / read from */
270 unsigned int read_bytes; /* Number of bytes read during command */
271 unsigned int column; /* Saved column from SEQIN */
272 unsigned int index; /* Pointer to next byte to 'read' */
273 unsigned int status; /* status read from LTESR after last op */
274 unsigned int mdr; /* UPM/FCM Data Register value */
275 unsigned int use_mdr; /* Non zero if the MDR is to be set */
276 unsigned int oob; /* Non zero if operating on OOB data */
277 char *oob_poi; /* Place to write ECC after read back */
278};
279
280/* These map to the positions used by the FCM hardware ECC generator */
281
282/* Small Page FLASH with FMR[ECCM] = 0 */
283static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
284 .eccbytes = 3,
285 .eccpos = {6, 7, 8},
286 .oobfree = { {0, 5}, {9, 7} },
287 .oobavail = 12,
288};
289
290/* Small Page FLASH with FMR[ECCM] = 1 */
291static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
292 .eccbytes = 3,
293 .eccpos = {8, 9, 10},
294 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
295 .oobavail = 12,
296};
297
298/* Large Page FLASH with FMR[ECCM] = 0 */
299static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
300 .eccbytes = 12,
301 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
302 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
303 .oobavail = 48,
304};
305
306/* Large Page FLASH with FMR[ECCM] = 1 */
307static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
308 .eccbytes = 12,
309 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
310 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
311 .oobavail = 48,
312};
313
314/*=================================*/
315
316/*
317 * Set up the FCM hardware block and page address fields, and the fcm
318 * structure addr field to point to the correct FCM buffer in memory
319 */
320static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
321{
322 struct nand_chip *chip = mtd->priv;
323 struct fsl_elbc_mtd *priv = chip->priv;
324 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
325 struct elbc_regs __iomem *lbc = ctrl->regs;
326 int buf_num;
327
328 ctrl->page = page_addr;
329
330 out_be32(&lbc->fbar,
331 page_addr >> (chip->phys_erase_shift - chip->page_shift));
332
333 if (priv->page_size) {
334 out_be32(&lbc->fpar,
335 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
336 (oob ? FPAR_LP_MS : 0) | column);
337 buf_num = (page_addr & 1) << 2;
338 } else {
339 out_be32(&lbc->fpar,
340 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
341 (oob ? FPAR_SP_MS : 0) | column);
342 buf_num = page_addr & 7;
343 }
344
345 ctrl->addr = priv->vbase + buf_num * 1024;
346 ctrl->index = column;
347
348 /* for OOB data point to the second half of the buffer */
349 if (oob)
350 ctrl->index += priv->page_size ? 2048 : 512;
351
352 dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
353 "index %x, pes %d ps %d\n",
354 buf_num, ctrl->addr, priv->vbase, ctrl->index,
355 chip->phys_erase_shift, chip->page_shift);
356}
357
358/*
359 * execute FCM command and wait for it to complete
360 */
361static int fsl_elbc_run_command(struct mtd_info *mtd)
362{
363 struct nand_chip *chip = mtd->priv;
364 struct fsl_elbc_mtd *priv = chip->priv;
365 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
366 struct elbc_regs __iomem *lbc = ctrl->regs;
367
368 /* Setup the FMR[OP] to execute without write protection */
369 out_be32(&lbc->fmr, priv->fmr | 3);
370 if (ctrl->use_mdr)
371 out_be32(&lbc->mdr, ctrl->mdr);
372
373 dev_vdbg(ctrl->dev,
374 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
375 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
376 dev_vdbg(ctrl->dev,
377 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
378 "fbcr=%08x bank=%d\n",
379 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
380 in_be32(&lbc->fbcr), priv->bank);
381
382 /* execute special operation */
383 out_be32(&lbc->lsor, priv->bank);
384
385 /* wait for FCM complete flag or timeout */
386 ctrl->irq_status = 0;
387 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
388 FCM_TIMEOUT_MSECS * HZ/1000);
389 ctrl->status = ctrl->irq_status;
390
391 /* store mdr value in case it was needed */
392 if (ctrl->use_mdr)
393 ctrl->mdr = in_be32(&lbc->mdr);
394
395 ctrl->use_mdr = 0;
396
397 dev_vdbg(ctrl->dev,
398 "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
399 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
400
401 /* returns 0 on success otherwise non-zero) */
402 return ctrl->status == LTESR_CC ? 0 : -EIO;
403}
404
405static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
406{
407 struct fsl_elbc_mtd *priv = chip->priv;
408 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
409 struct elbc_regs __iomem *lbc = ctrl->regs;
410
411 if (priv->page_size) {
412 out_be32(&lbc->fir,
413 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
414 (FIR_OP_CA << FIR_OP1_SHIFT) |
415 (FIR_OP_PA << FIR_OP2_SHIFT) |
416 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
417 (FIR_OP_RBW << FIR_OP4_SHIFT));
418
419 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
420 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
421 } else {
422 out_be32(&lbc->fir,
423 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
424 (FIR_OP_CA << FIR_OP1_SHIFT) |
425 (FIR_OP_PA << FIR_OP2_SHIFT) |
426 (FIR_OP_RBW << FIR_OP3_SHIFT));
427
428 if (oob)
429 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
430 else
431 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
432 }
433}
434
435/* cmdfunc send commands to the FCM */
436static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
437 int column, int page_addr)
438{
439 struct nand_chip *chip = mtd->priv;
440 struct fsl_elbc_mtd *priv = chip->priv;
441 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
442 struct elbc_regs __iomem *lbc = ctrl->regs;
443
444 ctrl->use_mdr = 0;
445
446 /* clear the read buffer */
447 ctrl->read_bytes = 0;
448 if (command != NAND_CMD_PAGEPROG)
449 ctrl->index = 0;
450
451 switch (command) {
452 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
453 case NAND_CMD_READ1:
454 column += 256;
455
456 /* fall-through */
457 case NAND_CMD_READ0:
458 dev_dbg(ctrl->dev,
459 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
460 " 0x%x, column: 0x%x.\n", page_addr, column);
461
462
463 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
464 set_addr(mtd, 0, page_addr, 0);
465
466 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
467 ctrl->index += column;
468
469 fsl_elbc_do_read(chip, 0);
470 fsl_elbc_run_command(mtd);
471 return;
472
473 /* READOOB reads only the OOB because no ECC is performed. */
474 case NAND_CMD_READOOB:
475 dev_vdbg(ctrl->dev,
476 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
477 " 0x%x, column: 0x%x.\n", page_addr, column);
478
479 out_be32(&lbc->fbcr, mtd->oobsize - column);
480 set_addr(mtd, column, page_addr, 1);
481
482 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
483
484 fsl_elbc_do_read(chip, 1);
485 fsl_elbc_run_command(mtd);
486 return;
487
488 /* READID must read all 5 possible bytes while CEB is active */
489 case NAND_CMD_READID:
490 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
491
492 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
493 (FIR_OP_UA << FIR_OP1_SHIFT) |
494 (FIR_OP_RBW << FIR_OP2_SHIFT));
495 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
496 /* 5 bytes for manuf, device and exts */
497 out_be32(&lbc->fbcr, 5);
498 ctrl->read_bytes = 5;
499 ctrl->use_mdr = 1;
500 ctrl->mdr = 0;
501
502 set_addr(mtd, 0, 0, 0);
503 fsl_elbc_run_command(mtd);
504 return;
505
506 /* ERASE1 stores the block and page address */
507 case NAND_CMD_ERASE1:
508 dev_vdbg(ctrl->dev,
509 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
510 "page_addr: 0x%x.\n", page_addr);
511 set_addr(mtd, 0, page_addr, 0);
512 return;
513
514 /* ERASE2 uses the block and page address from ERASE1 */
515 case NAND_CMD_ERASE2:
516 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
517
518 out_be32(&lbc->fir,
519 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
520 (FIR_OP_PA << FIR_OP1_SHIFT) |
521 (FIR_OP_CM1 << FIR_OP2_SHIFT));
522
523 out_be32(&lbc->fcr,
524 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
525 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
526
527 out_be32(&lbc->fbcr, 0);
528 ctrl->read_bytes = 0;
529
530 fsl_elbc_run_command(mtd);
531 return;
532
533 /* SEQIN sets up the addr buffer and all registers except the length */
534 case NAND_CMD_SEQIN: {
535 __be32 fcr;
536 dev_vdbg(ctrl->dev,
537 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
538 "page_addr: 0x%x, column: 0x%x.\n",
539 page_addr, column);
540
541 ctrl->column = column;
542 ctrl->oob = 0;
543
544 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
545 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
546
547 if (priv->page_size) {
548 out_be32(&lbc->fir,
549 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
550 (FIR_OP_CA << FIR_OP1_SHIFT) |
551 (FIR_OP_PA << FIR_OP2_SHIFT) |
552 (FIR_OP_WB << FIR_OP3_SHIFT) |
553 (FIR_OP_CW1 << FIR_OP4_SHIFT));
554
555 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
556 } else {
557 out_be32(&lbc->fir,
558 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
559 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
560 (FIR_OP_CA << FIR_OP2_SHIFT) |
561 (FIR_OP_PA << FIR_OP3_SHIFT) |
562 (FIR_OP_WB << FIR_OP4_SHIFT) |
563 (FIR_OP_CW1 << FIR_OP5_SHIFT));
564
565 if (column >= mtd->writesize) {
566 /* OOB area --> READOOB */
567 column -= mtd->writesize;
568 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
569 ctrl->oob = 1;
570 } else if (column < 256) {
571 /* First 256 bytes --> READ0 */
572 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
573 } else {
574 /* Second 256 bytes --> READ1 */
575 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
576 }
577 }
578
579 out_be32(&lbc->fcr, fcr);
580 set_addr(mtd, column, page_addr, ctrl->oob);
581 return;
582 }
583
584 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
585 case NAND_CMD_PAGEPROG: {
586 int full_page;
587 dev_vdbg(ctrl->dev,
588 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
589 "writing %d bytes.\n", ctrl->index);
590
591 /* if the write did not start at 0 or is not a full page
592 * then set the exact length, otherwise use a full page
593 * write so the HW generates the ECC.
594 */
595 if (ctrl->oob || ctrl->column != 0 ||
596 ctrl->index != mtd->writesize + mtd->oobsize) {
597 out_be32(&lbc->fbcr, ctrl->index);
598 full_page = 0;
599 } else {
600 out_be32(&lbc->fbcr, 0);
601 full_page = 1;
602 }
603
604 fsl_elbc_run_command(mtd);
605
606 /* Read back the page in order to fill in the ECC for the
607 * caller. Is this really needed?
608 */
609 if (full_page && ctrl->oob_poi) {
610 out_be32(&lbc->fbcr, 3);
611 set_addr(mtd, 6, page_addr, 1);
612
613 ctrl->read_bytes = mtd->writesize + 9;
614
615 fsl_elbc_do_read(chip, 1);
616 fsl_elbc_run_command(mtd);
617
618 memcpy_fromio(ctrl->oob_poi + 6,
619 &ctrl->addr[ctrl->index], 3);
620 ctrl->index += 3;
621 }
622
623 ctrl->oob_poi = NULL;
624 return;
625 }
626
627 /* CMD_STATUS must read the status byte while CEB is active */
628 /* Note - it does not wait for the ready line */
629 case NAND_CMD_STATUS:
630 out_be32(&lbc->fir,
631 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
632 (FIR_OP_RBW << FIR_OP1_SHIFT));
633 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
634 out_be32(&lbc->fbcr, 1);
635 set_addr(mtd, 0, 0, 0);
636 ctrl->read_bytes = 1;
637
638 fsl_elbc_run_command(mtd);
639
640 /* The chip always seems to report that it is
641 * write-protected, even when it is not.
642 */
643 setbits8(ctrl->addr, NAND_STATUS_WP);
644 return;
645
646 /* RESET without waiting for the ready line */
647 case NAND_CMD_RESET:
648 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
649 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
650 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
651 fsl_elbc_run_command(mtd);
652 return;
653
654 default:
655 dev_err(ctrl->dev,
656 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
657 command);
658 }
659}
660
661static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
662{
663 /* The hardware does not seem to support multiple
664 * chips per bank.
665 */
666}
667
668/*
669 * Write buf to the FCM Controller Data Buffer
670 */
671static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
672{
673 struct nand_chip *chip = mtd->priv;
674 struct fsl_elbc_mtd *priv = chip->priv;
675 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
676 unsigned int bufsize = mtd->writesize + mtd->oobsize;
677
678 if (len < 0) {
679 dev_err(ctrl->dev, "write_buf of %d bytes", len);
680 ctrl->status = 0;
681 return;
682 }
683
684 if ((unsigned int)len > bufsize - ctrl->index) {
685 dev_err(ctrl->dev,
686 "write_buf beyond end of buffer "
687 "(%d requested, %u available)\n",
688 len, bufsize - ctrl->index);
689 len = bufsize - ctrl->index;
690 }
691
692 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
693 ctrl->index += len;
694}
695
696/*
697 * read a byte from either the FCM hardware buffer if it has any data left
698 * otherwise issue a command to read a single byte.
699 */
700static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
701{
702 struct nand_chip *chip = mtd->priv;
703 struct fsl_elbc_mtd *priv = chip->priv;
704 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
705
706 /* If there are still bytes in the FCM, then use the next byte. */
707 if (ctrl->index < ctrl->read_bytes)
708 return in_8(&ctrl->addr[ctrl->index++]);
709
710 dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
711 return ERR_BYTE;
712}
713
714/*
715 * Read from the FCM Controller Data Buffer
716 */
717static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
718{
719 struct nand_chip *chip = mtd->priv;
720 struct fsl_elbc_mtd *priv = chip->priv;
721 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
722 int avail;
723
724 if (len < 0)
725 return;
726
727 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
728 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
729 ctrl->index += avail;
730
731 if (len > avail)
732 dev_err(ctrl->dev,
733 "read_buf beyond end of buffer "
734 "(%d requested, %d available)\n",
735 len, avail);
736}
737
738/*
739 * Verify buffer against the FCM Controller Data Buffer
740 */
741static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
742{
743 struct nand_chip *chip = mtd->priv;
744 struct fsl_elbc_mtd *priv = chip->priv;
745 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
746 int i;
747
748 if (len < 0) {
749 dev_err(ctrl->dev, "write_buf of %d bytes", len);
750 return -EINVAL;
751 }
752
753 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
754 dev_err(ctrl->dev,
755 "verify_buf beyond end of buffer "
756 "(%d requested, %u available)\n",
757 len, ctrl->read_bytes - ctrl->index);
758
759 ctrl->index = ctrl->read_bytes;
760 return -EINVAL;
761 }
762
763 for (i = 0; i < len; i++)
764 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
765 break;
766
767 ctrl->index += len;
768 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
769}
770
771/* This function is called after Program and Erase Operations to
772 * check for success or failure.
773 */
774static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
775{
776 struct fsl_elbc_mtd *priv = chip->priv;
777 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
778 struct elbc_regs __iomem *lbc = ctrl->regs;
779
780 if (ctrl->status != LTESR_CC)
781 return NAND_STATUS_FAIL;
782
783 /* Use READ_STATUS command, but wait for the device to be ready */
784 ctrl->use_mdr = 0;
785 out_be32(&lbc->fir,
786 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
787 (FIR_OP_RBW << FIR_OP1_SHIFT));
788 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
789 out_be32(&lbc->fbcr, 1);
790 set_addr(mtd, 0, 0, 0);
791 ctrl->read_bytes = 1;
792
793 fsl_elbc_run_command(mtd);
794
795 if (ctrl->status != LTESR_CC)
796 return NAND_STATUS_FAIL;
797
798 /* The chip always seems to report that it is
799 * write-protected, even when it is not.
800 */
801 setbits8(ctrl->addr, NAND_STATUS_WP);
802 return fsl_elbc_read_byte(mtd);
803}
804
805static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
806{
807 struct nand_chip *chip = mtd->priv;
808 struct fsl_elbc_mtd *priv = chip->priv;
809 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
810 struct elbc_regs __iomem *lbc = ctrl->regs;
811 unsigned int al;
812
813 /* calculate FMR Address Length field */
814 al = 0;
815 if (chip->pagemask & 0xffff0000)
816 al++;
817 if (chip->pagemask & 0xff000000)
818 al++;
819
820 /* add to ECCM mode set in fsl_elbc_init */
821 priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
822 (al << FMR_AL_SHIFT);
823
824 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
825 chip->numchips);
826 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
827 chip->chipsize);
828 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
829 chip->pagemask);
830 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
831 chip->chip_delay);
832 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
833 chip->badblockpos);
834 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
835 chip->chip_shift);
836 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
837 chip->page_shift);
838 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
839 chip->phys_erase_shift);
840 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
841 chip->ecclayout);
842 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
843 chip->ecc.mode);
844 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
845 chip->ecc.steps);
846 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
847 chip->ecc.bytes);
848 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
849 chip->ecc.total);
850 dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
851 chip->ecc.layout);
852 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
853 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
854 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
855 mtd->erasesize);
856 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
857 mtd->writesize);
858 dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
859 mtd->oobsize);
860
861 /* adjust Option Register and ECC to match Flash page size */
862 if (mtd->writesize == 512) {
863 priv->page_size = 0;
864 clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);
865 } else if (mtd->writesize == 2048) {
866 priv->page_size = 1;
867 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
868 /* adjust ecc setup if needed */
869 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
870 BR_DECC_CHK_GEN) {
871 chip->ecc.size = 512;
872 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
873 &fsl_elbc_oob_lp_eccm1 :
874 &fsl_elbc_oob_lp_eccm0;
875 mtd->ecclayout = chip->ecc.layout;
876 mtd->oobavail = chip->ecc.layout->oobavail;
877 }
878 } else {
879 dev_err(ctrl->dev,
880 "fsl_elbc_init: page size %d is not supported\n",
881 mtd->writesize);
882 return -1;
883 }
884
885 /* The default u-boot configuration on MPC8313ERDB causes errors;
886 * more delay is needed. This should be safe for other boards
887 * as well.
888 */
889 setbits32(&lbc->bank[priv->bank].or, 0x70);
890 return 0;
891}
892
893static int fsl_elbc_read_page(struct mtd_info *mtd,
894 struct nand_chip *chip,
895 uint8_t *buf)
896{
897 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
898 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
899
900 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
901 mtd->ecc_stats.failed++;
902
903 return 0;
904}
905
906/* ECC will be calculated automatically, and errors will be detected in
907 * waitfunc.
908 */
909static void fsl_elbc_write_page(struct mtd_info *mtd,
910 struct nand_chip *chip,
911 const uint8_t *buf)
912{
913 struct fsl_elbc_mtd *priv = chip->priv;
914 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
915
916 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
917 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
918
919 ctrl->oob_poi = chip->oob_poi;
920}
921
922static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
923{
924 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
925 struct elbc_regs __iomem *lbc = ctrl->regs;
926 struct nand_chip *chip = &priv->chip;
927
928 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
929
930 /* Fill in fsl_elbc_mtd structure */
931 priv->mtd.priv = chip;
932 priv->mtd.owner = THIS_MODULE;
933 priv->fmr = 0; /* rest filled in later */
934
935 /* fill in nand_chip structure */
936 /* set up function call table */
937 chip->read_byte = fsl_elbc_read_byte;
938 chip->write_buf = fsl_elbc_write_buf;
939 chip->read_buf = fsl_elbc_read_buf;
940 chip->verify_buf = fsl_elbc_verify_buf;
941 chip->select_chip = fsl_elbc_select_chip;
942 chip->cmdfunc = fsl_elbc_cmdfunc;
943 chip->waitfunc = fsl_elbc_wait;
944
945 /* set up nand options */
946 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
947
948 chip->controller = &ctrl->controller;
949 chip->priv = priv;
950
951 chip->ecc.read_page = fsl_elbc_read_page;
952 chip->ecc.write_page = fsl_elbc_write_page;
953
954 /* If CS Base Register selects full hardware ECC then use it */
955 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
956 BR_DECC_CHK_GEN) {
957 chip->ecc.mode = NAND_ECC_HW;
958 /* put in small page settings and adjust later if needed */
959 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
960 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
961 chip->ecc.size = 512;
962 chip->ecc.bytes = 3;
963 } else {
964 /* otherwise fall back to default software ECC */
965 chip->ecc.mode = NAND_ECC_SOFT;
966 }
967
968 return 0;
969}
970
971static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
972{
973 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
974
975 nand_release(&priv->mtd);
976
977 if (priv->vbase)
978 iounmap(priv->vbase);
979
980 ctrl->chips[priv->bank] = NULL;
981 kfree(priv);
982
983 return 0;
984}
985
986static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
987 struct device_node *node)
988{
989 struct elbc_regs __iomem *lbc = ctrl->regs;
990 struct fsl_elbc_mtd *priv;
991 struct resource res;
992#ifdef CONFIG_MTD_PARTITIONS
993 static const char *part_probe_types[]
994 = { "cmdlinepart", "RedBoot", NULL };
995 struct mtd_partition *parts;
996#endif
997 int ret;
998 int bank;
999
1000 /* get, allocate and map the memory resource */
1001 ret = of_address_to_resource(node, 0, &res);
1002 if (ret) {
1003 dev_err(ctrl->dev, "failed to get resource\n");
1004 return ret;
1005 }
1006
1007 /* find which chip select it is connected to */
1008 for (bank = 0; bank < MAX_BANKS; bank++)
1009 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
1010 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
1011 (in_be32(&lbc->bank[bank].br) &
1012 in_be32(&lbc->bank[bank].or) & BR_BA)
1013 == res.start)
1014 break;
1015
1016 if (bank >= MAX_BANKS) {
1017 dev_err(ctrl->dev, "address did not match any chip selects\n");
1018 return -ENODEV;
1019 }
1020
1021 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1022 if (!priv)
1023 return -ENOMEM;
1024
1025 ctrl->chips[bank] = priv;
1026 priv->bank = bank;
1027 priv->ctrl = ctrl;
1028 priv->dev = ctrl->dev;
1029
1030 priv->vbase = ioremap(res.start, res.end - res.start + 1);
1031 if (!priv->vbase) {
1032 dev_err(ctrl->dev, "failed to map chip region\n");
1033 ret = -ENOMEM;
1034 goto err;
1035 }
1036
1037 ret = fsl_elbc_chip_init(priv);
1038 if (ret)
1039 goto err;
1040
1041 ret = nand_scan_ident(&priv->mtd, 1);
1042 if (ret)
1043 goto err;
1044
1045 ret = fsl_elbc_chip_init_tail(&priv->mtd);
1046 if (ret)
1047 goto err;
1048
1049 ret = nand_scan_tail(&priv->mtd);
1050 if (ret)
1051 goto err;
1052
1053#ifdef CONFIG_MTD_PARTITIONS
1054 /* First look for RedBoot table or partitions on the command
1055 * line, these take precedence over device tree information */
1056 ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
1057 if (ret < 0)
1058 goto err;
1059
1060#ifdef CONFIG_MTD_OF_PARTS
1061 if (ret == 0) {
1062 ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
1063 node, &parts);
1064 if (ret < 0)
1065 goto err;
1066 }
1067#endif
1068
1069 if (ret > 0)
1070 add_mtd_partitions(&priv->mtd, parts, ret);
1071 else
1072#endif
1073 add_mtd_device(&priv->mtd);
1074
1075 printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
1076 res.start, priv->bank);
1077 return 0;
1078
1079err:
1080 fsl_elbc_chip_remove(priv);
1081 return ret;
1082}
1083
1084static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
1085{
1086 struct elbc_regs __iomem *lbc = ctrl->regs;
1087
1088 /* clear event registers */
1089 setbits32(&lbc->ltesr, LTESR_NAND_MASK);
1090 out_be32(&lbc->lteatr, 0);
1091
1092 /* Enable interrupts for any detected events */
1093 out_be32(&lbc->lteir, LTESR_NAND_MASK);
1094
1095 ctrl->read_bytes = 0;
1096 ctrl->index = 0;
1097 ctrl->addr = NULL;
1098
1099 return 0;
1100}
1101
1102static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
1103{
1104 struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
1105 int i;
1106
1107 for (i = 0; i < MAX_BANKS; i++)
1108 if (ctrl->chips[i])
1109 fsl_elbc_chip_remove(ctrl->chips[i]);
1110
1111 if (ctrl->irq)
1112 free_irq(ctrl->irq, ctrl);
1113
1114 if (ctrl->regs)
1115 iounmap(ctrl->regs);
1116
1117 dev_set_drvdata(&ofdev->dev, NULL);
1118 kfree(ctrl);
1119 return 0;
1120}
1121
1122/* NOTE: This interrupt is also used to report other localbus events,
1123 * such as transaction errors on other chipselects. If we want to
1124 * capture those, we'll need to move the IRQ code into a shared
1125 * LBC driver.
1126 */
1127
1128static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
1129{
1130 struct fsl_elbc_ctrl *ctrl = data;
1131 struct elbc_regs __iomem *lbc = ctrl->regs;
1132 __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
1133
1134 if (status) {
1135 out_be32(&lbc->ltesr, status);
1136 out_be32(&lbc->lteatr, 0);
1137
1138 ctrl->irq_status = status;
1139 smp_wmb();
1140 wake_up(&ctrl->irq_wait);
1141
1142 return IRQ_HANDLED;
1143 }
1144
1145 return IRQ_NONE;
1146}
1147
1148/* fsl_elbc_ctrl_probe
1149 *
1150 * called by device layer when it finds a device matching
1151 * one our driver can handled. This code allocates all of
1152 * the resources needed for the controller only. The
1153 * resources for the NAND banks themselves are allocated
1154 * in the chip probe function.
1155*/
1156
1157static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
1158 const struct of_device_id *match)
1159{
1160 struct device_node *child;
1161 struct fsl_elbc_ctrl *ctrl;
1162 int ret;
1163
1164 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1165 if (!ctrl)
1166 return -ENOMEM;
1167
1168 dev_set_drvdata(&ofdev->dev, ctrl);
1169
1170 spin_lock_init(&ctrl->controller.lock);
1171 init_waitqueue_head(&ctrl->controller.wq);
1172 init_waitqueue_head(&ctrl->irq_wait);
1173
1174 ctrl->regs = of_iomap(ofdev->node, 0);
1175 if (!ctrl->regs) {
1176 dev_err(&ofdev->dev, "failed to get memory region\n");
1177 ret = -ENODEV;
1178 goto err;
1179 }
1180
1181 ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
1182 if (ctrl->irq == NO_IRQ) {
1183 dev_err(&ofdev->dev, "failed to get irq resource\n");
1184 ret = -ENODEV;
1185 goto err;
1186 }
1187
1188 ctrl->dev = &ofdev->dev;
1189
1190 ret = fsl_elbc_ctrl_init(ctrl);
1191 if (ret < 0)
1192 goto err;
1193
1194 ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1195 if (ret != 0) {
1196 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1197 ctrl->irq);
1198 ret = ctrl->irq;
1199 goto err;
1200 }
1201
1202 for_each_child_of_node(ofdev->node, child)
1203 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1204 fsl_elbc_chip_probe(ctrl, child);
1205
1206 return 0;
1207
1208err:
1209 fsl_elbc_ctrl_remove(ofdev);
1210 return ret;
1211}
1212
1213static const struct of_device_id fsl_elbc_match[] = {
1214 {
1215 .compatible = "fsl,elbc",
1216 },
1217 {}
1218};
1219
1220static struct of_platform_driver fsl_elbc_ctrl_driver = {
1221 .driver = {
1222 .name = "fsl-elbc",
1223 },
1224 .match_table = fsl_elbc_match,
1225 .probe = fsl_elbc_ctrl_probe,
1226 .remove = __devexit_p(fsl_elbc_ctrl_remove),
1227};
1228
1229static int __init fsl_elbc_init(void)
1230{
1231 return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1232}
1233
1234static void __exit fsl_elbc_exit(void)
1235{
1236 of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1237}
1238
1239module_init(fsl_elbc_init);
1240module_exit(fsl_elbc_exit);
1241
1242MODULE_LICENSE("GPL");
1243MODULE_AUTHOR("Freescale");
1244MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ddd4fc019042..7acb1a0e7409 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2469,8 +2469,12 @@ int nand_scan_tail(struct mtd_info *mtd)
2469 chip->ecc.write_oob = nand_write_oob_std; 2469 chip->ecc.write_oob = nand_write_oob_std;
2470 2470
2471 case NAND_ECC_HW_SYNDROME: 2471 case NAND_ECC_HW_SYNDROME:
2472 if (!chip->ecc.calculate || !chip->ecc.correct || 2472 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2473 !chip->ecc.hwctl) { 2473 !chip->ecc.hwctl) &&
2474 (!chip->ecc.read_page ||
2475 chip->ecc.read_page == nand_read_page_hwecc ||
2476 !chip->ecc.write_page ||
2477 chip->ecc.write_page == nand_write_page_hwecc)) {
2474 printk(KERN_WARNING "No ECC functions supplied, " 2478 printk(KERN_WARNING "No ECC functions supplied, "
2475 "Hardware ECC not possible\n"); 2479 "Hardware ECC not possible\n");
2476 BUG(); 2480 BUG();
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
new file mode 100644
index 000000000000..9162cca0182b
--- /dev/null
+++ b/drivers/mtd/nand/orion_nand.c
@@ -0,0 +1,171 @@
1/*
2 * drivers/mtd/nand/orion_nand.c
3 *
4 * NAND support for Marvell Orion SoC platforms
5 *
6 * Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/partitions.h>
19#include <asm/io.h>
20#include <asm/sizes.h>
21#include <asm/arch/platform.h>
22#include <asm/arch/hardware.h>
23
24#ifdef CONFIG_MTD_CMDLINE_PARTS
25static const char *part_probes[] = { "cmdlinepart", NULL };
26#endif
27
28static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
29{
30 struct nand_chip *nc = mtd->priv;
31 struct orion_nand_data *board = nc->priv;
32 u32 offs;
33
34 if (cmd == NAND_CMD_NONE)
35 return;
36
37 if (ctrl & NAND_CLE)
38 offs = (1 << board->cle);
39 else if (ctrl & NAND_ALE)
40 offs = (1 << board->ale);
41 else
42 return;
43
44 if (nc->options & NAND_BUSWIDTH_16)
45 offs <<= 1;
46
47 writeb(cmd, nc->IO_ADDR_W + offs);
48}
49
50static int __init orion_nand_probe(struct platform_device *pdev)
51{
52 struct mtd_info *mtd;
53 struct nand_chip *nc;
54 struct orion_nand_data *board;
55 void __iomem *io_base;
56 int ret = 0;
57#ifdef CONFIG_MTD_PARTITIONS
58 struct mtd_partition *partitions = NULL;
59 int num_part = 0;
60#endif
61
62 nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
63 if (!nc) {
64 printk(KERN_ERR "orion_nand: failed to allocate device structure.\n");
65 ret = -ENOMEM;
66 goto no_res;
67 }
68 mtd = (struct mtd_info *)(nc + 1);
69
70 io_base = ioremap(pdev->resource[0].start,
71 pdev->resource[0].end - pdev->resource[0].start + 1);
72 if (!io_base) {
73 printk(KERN_ERR "orion_nand: ioremap failed\n");
74 ret = -EIO;
75 goto no_res;
76 }
77
78 board = pdev->dev.platform_data;
79
80 mtd->priv = nc;
81 mtd->owner = THIS_MODULE;
82
83 nc->priv = board;
84 nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
85 nc->cmd_ctrl = orion_nand_cmd_ctrl;
86 nc->ecc.mode = NAND_ECC_SOFT;
87
88 if (board->width == 16)
89 nc->options |= NAND_BUSWIDTH_16;
90
91 platform_set_drvdata(pdev, mtd);
92
93 if (nand_scan(mtd, 1)) {
94 ret = -ENXIO;
95 goto no_dev;
96 }
97
98#ifdef CONFIG_MTD_PARTITIONS
99#ifdef CONFIG_MTD_CMDLINE_PARTS
100 mtd->name = "orion_nand";
101 num_part = parse_mtd_partitions(mtd, part_probes, &partitions, 0);
102#endif
103 /* If cmdline partitions have been passed, let them be used */
104 if (num_part <= 0) {
105 num_part = board->nr_parts;
106 partitions = board->parts;
107 }
108
109 if (partitions && num_part > 0)
110 ret = add_mtd_partitions(mtd, partitions, num_part);
111 else
112 ret = add_mtd_device(mtd);
113#else
114 ret = add_mtd_device(mtd);
115#endif
116
117 if (ret) {
118 nand_release(mtd);
119 goto no_dev;
120 }
121
122 return 0;
123
124no_dev:
125 platform_set_drvdata(pdev, NULL);
126 iounmap(io_base);
127no_res:
128 kfree(nc);
129
130 return ret;
131}
132
133static int __devexit orion_nand_remove(struct platform_device *pdev)
134{
135 struct mtd_info *mtd = platform_get_drvdata(pdev);
136 struct nand_chip *nc = mtd->priv;
137
138 nand_release(mtd);
139
140 iounmap(nc->IO_ADDR_W);
141
142 kfree(nc);
143
144 return 0;
145}
146
147static struct platform_driver orion_nand_driver = {
148 .probe = orion_nand_probe,
149 .remove = orion_nand_remove,
150 .driver = {
151 .name = "orion_nand",
152 .owner = THIS_MODULE,
153 },
154};
155
156static int __init orion_nand_init(void)
157{
158 return platform_driver_register(&orion_nand_driver);
159}
160
161static void __exit orion_nand_exit(void)
162{
163 platform_driver_unregister(&orion_nand_driver);
164}
165
166module_init(orion_nand_init);
167module_exit(orion_nand_exit);
168
169MODULE_LICENSE("GPL");
170MODULE_AUTHOR("Tzachi Perelstein");
171MODULE_DESCRIPTION("NAND glue for Orion platforms");
diff --git a/drivers/mtd/nand/pasemi_nand.c b/drivers/mtd/nand/pasemi_nand.c
new file mode 100644
index 000000000000..75c899039023
--- /dev/null
+++ b/drivers/mtd/nand/pasemi_nand.c
@@ -0,0 +1,243 @@
1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Author: Egor Martovetsky <egor@pasemi.com>
5 * Maintained by: Olof Johansson <olof@lixom.net>
6 *
7 * Driver for the PWRficient onchip NAND flash interface
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#undef DEBUG
24
25#include <linux/slab.h>
26#include <linux/init.h>
27#include <linux/module.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/nand_ecc.h>
31#include <linux/of_platform.h>
32#include <linux/platform_device.h>
33#include <linux/pci.h>
34
35#include <asm/io.h>
36
37#define LBICTRL_LPCCTL_NR 0x00004000
38#define CLE_PIN_CTL 15
39#define ALE_PIN_CTL 14
40
41static unsigned int lpcctl;
42static struct mtd_info *pasemi_nand_mtd;
43static const char driver_name[] = "pasemi-nand";
44
45static void pasemi_read_buf(struct mtd_info *mtd, u_char *buf, int len)
46{
47 struct nand_chip *chip = mtd->priv;
48
49 while (len > 0x800) {
50 memcpy_fromio(buf, chip->IO_ADDR_R, 0x800);
51 buf += 0x800;
52 len -= 0x800;
53 }
54 memcpy_fromio(buf, chip->IO_ADDR_R, len);
55}
56
57static void pasemi_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
58{
59 struct nand_chip *chip = mtd->priv;
60
61 while (len > 0x800) {
62 memcpy_toio(chip->IO_ADDR_R, buf, 0x800);
63 buf += 0x800;
64 len -= 0x800;
65 }
66 memcpy_toio(chip->IO_ADDR_R, buf, len);
67}
68
69static void pasemi_hwcontrol(struct mtd_info *mtd, int cmd,
70 unsigned int ctrl)
71{
72 struct nand_chip *chip = mtd->priv;
73
74 if (cmd == NAND_CMD_NONE)
75 return;
76
77 if (ctrl & NAND_CLE)
78 out_8(chip->IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
79 else
80 out_8(chip->IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
81
82 /* Push out posted writes */
83 eieio();
84 inl(lpcctl);
85}
86
87int pasemi_device_ready(struct mtd_info *mtd)
88{
89 return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR);
90}
91
92static int __devinit pasemi_nand_probe(struct of_device *ofdev,
93 const struct of_device_id *match)
94{
95 struct pci_dev *pdev;
96 struct device_node *np = ofdev->node;
97 struct resource res;
98 struct nand_chip *chip;
99 int err = 0;
100
101 err = of_address_to_resource(np, 0, &res);
102
103 if (err)
104 return -EINVAL;
105
106 /* We only support one device at the moment */
107 if (pasemi_nand_mtd)
108 return -ENODEV;
109
110 pr_debug("pasemi_nand at %lx-%lx\n", res.start, res.end);
111
112 /* Allocate memory for MTD device structure and private data */
113 pasemi_nand_mtd = kzalloc(sizeof(struct mtd_info) +
114 sizeof(struct nand_chip), GFP_KERNEL);
115 if (!pasemi_nand_mtd) {
116 printk(KERN_WARNING
117 "Unable to allocate PASEMI NAND MTD device structure\n");
118 err = -ENOMEM;
119 goto out;
120 }
121
122 /* Get pointer to private data */
123 chip = (struct nand_chip *)&pasemi_nand_mtd[1];
124
125 /* Link the private data with the MTD structure */
126 pasemi_nand_mtd->priv = chip;
127 pasemi_nand_mtd->owner = THIS_MODULE;
128
129 chip->IO_ADDR_R = of_iomap(np, 0);
130 chip->IO_ADDR_W = chip->IO_ADDR_R;
131
132 if (!chip->IO_ADDR_R) {
133 err = -EIO;
134 goto out_mtd;
135 }
136
137 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
138 if (!pdev) {
139 err = -ENODEV;
140 goto out_ior;
141 }
142
143 lpcctl = pci_resource_start(pdev, 0);
144
145 if (!request_region(lpcctl, 4, driver_name)) {
146 err = -EBUSY;
147 goto out_ior;
148 }
149
150 chip->cmd_ctrl = pasemi_hwcontrol;
151 chip->dev_ready = pasemi_device_ready;
152 chip->read_buf = pasemi_read_buf;
153 chip->write_buf = pasemi_write_buf;
154 chip->chip_delay = 0;
155 chip->ecc.mode = NAND_ECC_SOFT;
156
157 /* Enable the following for a flash based bad block table */
158 chip->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;
159
160 /* Scan to find existance of the device */
161 if (nand_scan(pasemi_nand_mtd, 1)) {
162 err = -ENXIO;
163 goto out_lpc;
164 }
165
166 if (add_mtd_device(pasemi_nand_mtd)) {
167 printk(KERN_ERR "pasemi_nand: Unable to register MTD device\n");
168 err = -ENODEV;
169 goto out_lpc;
170 }
171
172 printk(KERN_INFO "PA Semi NAND flash at %08lx, control at I/O %x\n",
173 res.start, lpcctl);
174
175 return 0;
176
177 out_lpc:
178 release_region(lpcctl, 4);
179 out_ior:
180 iounmap(chip->IO_ADDR_R);
181 out_mtd:
182 kfree(pasemi_nand_mtd);
183 out:
184 return err;
185}
186
187static int __devexit pasemi_nand_remove(struct of_device *ofdev)
188{
189 struct nand_chip *chip;
190
191 if (!pasemi_nand_mtd)
192 return 0;
193
194 chip = pasemi_nand_mtd->priv;
195
196 /* Release resources, unregister device */
197 nand_release(pasemi_nand_mtd);
198
199 release_region(lpcctl, 4);
200
201 iounmap(chip->IO_ADDR_R);
202
203 /* Free the MTD device structure */
204 kfree(pasemi_nand_mtd);
205
206 pasemi_nand_mtd = NULL;
207
208 return 0;
209}
210
211static struct of_device_id pasemi_nand_match[] =
212{
213 {
214 .compatible = "pasemi,localbus-nand",
215 },
216 {},
217};
218
219MODULE_DEVICE_TABLE(of, pasemi_nand_match);
220
221static struct of_platform_driver pasemi_nand_driver =
222{
223 .name = (char*)driver_name,
224 .match_table = pasemi_nand_match,
225 .probe = pasemi_nand_probe,
226 .remove = pasemi_nand_remove,
227};
228
229static int __init pasemi_nand_init(void)
230{
231 return of_register_platform_driver(&pasemi_nand_driver);
232}
233module_init(pasemi_nand_init);
234
235static void __exit pasemi_nand_exit(void)
236{
237 of_unregister_platform_driver(&pasemi_nand_driver);
238}
239module_exit(pasemi_nand_exit);
240
241MODULE_LICENSE("GPL");
242MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
243MODULE_DESCRIPTION("NAND flash interface driver for PA Semi PWRficient");
diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
index cd725fc5e813..f6d5c2adc4fd 100644
--- a/drivers/mtd/nand/plat_nand.c
+++ b/drivers/mtd/nand/plat_nand.c
@@ -110,7 +110,9 @@ out:
110static int __devexit plat_nand_remove(struct platform_device *pdev) 110static int __devexit plat_nand_remove(struct platform_device *pdev)
111{ 111{
112 struct plat_nand_data *data = platform_get_drvdata(pdev); 112 struct plat_nand_data *data = platform_get_drvdata(pdev);
113#ifdef CONFIG_MTD_PARTITIONS
113 struct platform_nand_data *pdata = pdev->dev.platform_data; 114 struct platform_nand_data *pdata = pdev->dev.platform_data;
115#endif
114 116
115 nand_release(&data->mtd); 117 nand_release(&data->mtd);
116#ifdef CONFIG_MTD_PARTITIONS 118#ifdef CONFIG_MTD_PARTITIONS
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 2bd0737572c6..9260ad947524 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -120,6 +120,8 @@ struct s3c2410_nand_info {
120 int sel_bit; 120 int sel_bit;
121 int mtd_count; 121 int mtd_count;
122 122
123 unsigned long save_nfconf;
124
123 enum s3c_cpu_type cpu_type; 125 enum s3c_cpu_type cpu_type;
124}; 126};
125 127
@@ -364,23 +366,21 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
364 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { 366 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
365 /* calculate the bit position of the error */ 367 /* calculate the bit position of the error */
366 368
367 bit = (diff2 >> 2) & 1; 369 bit = ((diff2 >> 3) & 1) |
368 bit |= (diff2 >> 3) & 2; 370 ((diff2 >> 4) & 2) |
369 bit |= (diff2 >> 4) & 4; 371 ((diff2 >> 5) & 4);
370 372
371 /* calculate the byte position of the error */ 373 /* calculate the byte position of the error */
372 374
373 byte = (diff1 << 1) & 0x80; 375 byte = ((diff2 << 7) & 0x100) |
374 byte |= (diff1 << 2) & 0x40; 376 ((diff1 << 0) & 0x80) |
375 byte |= (diff1 << 3) & 0x20; 377 ((diff1 << 1) & 0x40) |
376 byte |= (diff1 << 4) & 0x10; 378 ((diff1 << 2) & 0x20) |
377 379 ((diff1 << 3) & 0x10) |
378 byte |= (diff0 >> 3) & 0x08; 380 ((diff0 >> 4) & 0x08) |
379 byte |= (diff0 >> 2) & 0x04; 381 ((diff0 >> 3) & 0x04) |
380 byte |= (diff0 >> 1) & 0x02; 382 ((diff0 >> 2) & 0x02) |
381 byte |= (diff0 >> 0) & 0x01; 383 ((diff0 >> 1) & 0x01);
382
383 byte |= (diff2 << 8) & 0x100;
384 384
385 dev_dbg(info->device, "correcting error bit %d, byte %d\n", 385 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
386 bit, byte); 386 bit, byte);
@@ -399,7 +399,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
399 if ((diff0 & ~(1<<fls(diff0))) == 0) 399 if ((diff0 & ~(1<<fls(diff0))) == 0)
400 return 1; 400 return 1;
401 401
402 return 0; 402 return -1;
403} 403}
404 404
405/* ECC functions 405/* ECC functions
@@ -810,6 +810,16 @@ static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
810 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 810 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
811 811
812 if (info) { 812 if (info) {
813 info->save_nfconf = readl(info->regs + S3C2410_NFCONF);
814
815 /* For the moment, we must ensure nFCE is high during
816 * the time we are suspended. This really should be
817 * handled by suspending the MTDs we are using, but
818 * that is currently not the case. */
819
820 writel(info->save_nfconf | info->sel_bit,
821 info->regs + S3C2410_NFCONF);
822
813 if (!allow_clk_stop(info)) 823 if (!allow_clk_stop(info))
814 clk_disable(info->clk); 824 clk_disable(info->clk);
815 } 825 }
@@ -820,11 +830,19 @@ static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
820static int s3c24xx_nand_resume(struct platform_device *dev) 830static int s3c24xx_nand_resume(struct platform_device *dev)
821{ 831{
822 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 832 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
833 unsigned long nfconf;
823 834
824 if (info) { 835 if (info) {
825 clk_enable(info->clk); 836 clk_enable(info->clk);
826 s3c2410_nand_inithw(info, dev); 837 s3c2410_nand_inithw(info, dev);
827 838
839 /* Restore the state of the nFCE line. */
840
841 nfconf = readl(info->regs + S3C2410_NFCONF);
842 nfconf &= ~info->sel_bit;
843 nfconf |= info->save_nfconf & info->sel_bit;
844 writel(nfconf, info->regs + S3C2410_NFCONF);
845
828 if (allow_clk_stop(info)) 846 if (allow_clk_stop(info))
829 clk_disable(info->clk); 847 clk_disable(info->clk);
830 } 848 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 09:57:31 -0500