diff options
Diffstat (limited to 'drivers/mtd/nand/s3c2410.c')
-rw-r--r-- | drivers/mtd/nand/s3c2410.c | 252 |
1 files changed, 135 insertions, 117 deletions
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 5b55599739f3..2c262fe03d8a 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c | |||
@@ -18,8 +18,9 @@ | |||
18 | * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug | 18 | * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug |
19 | * 08-Jul-2005 BJD Fix OOPS when no platform data supplied | 19 | * 08-Jul-2005 BJD Fix OOPS when no platform data supplied |
20 | * 20-Oct-2005 BJD Fix timing calculation bug | 20 | * 20-Oct-2005 BJD Fix timing calculation bug |
21 | * 14-Jan-2006 BJD Allow clock to be stopped when idle | ||
21 | * | 22 | * |
22 | * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $ | 23 | * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $ |
23 | * | 24 | * |
24 | * This program is free software; you can redistribute it and/or modify | 25 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License as published by | 26 | * it under the terms of the GNU General Public License as published by |
@@ -36,9 +37,6 @@ | |||
36 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 37 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
37 | */ | 38 | */ |
38 | 39 | ||
39 | #include <config/mtd/nand/s3c2410/hwecc.h> | ||
40 | #include <config/mtd/nand/s3c2410/debug.h> | ||
41 | |||
42 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG | 40 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
43 | #define DEBUG | 41 | #define DEBUG |
44 | #endif | 42 | #endif |
@@ -73,14 +71,20 @@ static int hardware_ecc = 1; | |||
73 | static int hardware_ecc = 0; | 71 | static int hardware_ecc = 0; |
74 | #endif | 72 | #endif |
75 | 73 | ||
74 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP | ||
75 | static int clock_stop = 1; | ||
76 | #else | ||
77 | static const int clock_stop = 0; | ||
78 | #endif | ||
79 | |||
80 | |||
76 | /* new oob placement block for use with hardware ecc generation | 81 | /* new oob placement block for use with hardware ecc generation |
77 | */ | 82 | */ |
78 | 83 | ||
79 | static struct nand_oobinfo nand_hw_eccoob = { | 84 | static struct nand_ecclayout nand_hw_eccoob = { |
80 | .useecc = MTD_NANDECC_AUTOPLACE, | 85 | .eccbytes = 3, |
81 | .eccbytes = 3, | 86 | .eccpos = {0, 1, 2}, |
82 | .eccpos = {0, 1, 2 }, | 87 | .oobfree = {{8, 8}} |
83 | .oobfree = { {8, 8} } | ||
84 | }; | 88 | }; |
85 | 89 | ||
86 | /* controller and mtd information */ | 90 | /* controller and mtd information */ |
@@ -135,6 +139,11 @@ static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) | |||
135 | return dev->dev.platform_data; | 139 | return dev->dev.platform_data; |
136 | } | 140 | } |
137 | 141 | ||
142 | static inline int allow_clk_stop(struct s3c2410_nand_info *info) | ||
143 | { | ||
144 | return clock_stop; | ||
145 | } | ||
146 | |||
138 | /* timing calculations */ | 147 | /* timing calculations */ |
139 | 148 | ||
140 | #define NS_IN_KHZ 1000000 | 149 | #define NS_IN_KHZ 1000000 |
@@ -149,8 +158,7 @@ static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) | |||
149 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | 158 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); |
150 | 159 | ||
151 | if (result > max) { | 160 | if (result > max) { |
152 | printk("%d ns is too big for current clock rate %ld\n", | 161 | printk("%d ns is too big for current clock rate %ld\n", wanted, clk); |
153 | wanted, clk); | ||
154 | return -1; | 162 | return -1; |
155 | } | 163 | } |
156 | 164 | ||
@@ -164,8 +172,7 @@ static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) | |||
164 | 172 | ||
165 | /* controller setup */ | 173 | /* controller setup */ |
166 | 174 | ||
167 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, | 175 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev) |
168 | struct platform_device *pdev) | ||
169 | { | 176 | { |
170 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); | 177 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
171 | unsigned long clkrate = clk_get_rate(info->clk); | 178 | unsigned long clkrate = clk_get_rate(info->clk); |
@@ -177,7 +184,7 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, | |||
177 | clkrate /= 1000; /* turn clock into kHz for ease of use */ | 184 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
178 | 185 | ||
179 | if (plat != NULL) { | 186 | if (plat != NULL) { |
180 | tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); | 187 | tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); |
181 | twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); | 188 | twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); |
182 | twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); | 189 | twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); |
183 | } else { | 190 | } else { |
@@ -193,19 +200,22 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, | |||
193 | } | 200 | } |
194 | 201 | ||
195 | printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", | 202 | printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
196 | tacls, to_ns(tacls, clkrate), | 203 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
197 | twrph0, to_ns(twrph0, clkrate), | ||
198 | twrph1, to_ns(twrph1, clkrate)); | ||
199 | 204 | ||
200 | if (!info->is_s3c2440) { | 205 | if (!info->is_s3c2440) { |
201 | cfg = S3C2410_NFCONF_EN; | 206 | cfg = S3C2410_NFCONF_EN; |
202 | cfg |= S3C2410_NFCONF_TACLS(tacls-1); | 207 | cfg |= S3C2410_NFCONF_TACLS(tacls - 1); |
203 | cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1); | 208 | cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); |
204 | cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1); | 209 | cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); |
205 | } else { | 210 | } else { |
206 | cfg = S3C2440_NFCONF_TACLS(tacls-1); | 211 | cfg = S3C2440_NFCONF_TACLS(tacls - 1); |
207 | cfg |= S3C2440_NFCONF_TWRPH0(twrph0-1); | 212 | cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); |
208 | cfg |= S3C2440_NFCONF_TWRPH1(twrph1-1); | 213 | cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); |
214 | |||
215 | /* enable the controller and de-assert nFCE */ | ||
216 | |||
217 | writel(S3C2440_NFCONT_ENABLE | S3C2440_NFCONT_ENABLE, | ||
218 | info->regs + S3C2440_NFCONT); | ||
209 | } | 219 | } |
210 | 220 | ||
211 | pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); | 221 | pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); |
@@ -229,7 +239,10 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) | |||
229 | info = nmtd->info; | 239 | info = nmtd->info; |
230 | 240 | ||
231 | bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; | 241 | bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; |
232 | reg = info->regs+((info->is_s3c2440) ? S3C2440_NFCONT:S3C2410_NFCONF); | 242 | reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF); |
243 | |||
244 | if (chip != -1 && allow_clk_stop(info)) | ||
245 | clk_enable(info->clk); | ||
233 | 246 | ||
234 | cur = readl(reg); | 247 | cur = readl(reg); |
235 | 248 | ||
@@ -243,77 +256,51 @@ static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) | |||
243 | 256 | ||
244 | if (info->platform != NULL) { | 257 | if (info->platform != NULL) { |
245 | if (info->platform->select_chip != NULL) | 258 | if (info->platform->select_chip != NULL) |
246 | (info->platform->select_chip)(nmtd->set, chip); | 259 | (info->platform->select_chip) (nmtd->set, chip); |
247 | } | 260 | } |
248 | 261 | ||
249 | cur &= ~bit; | 262 | cur &= ~bit; |
250 | } | 263 | } |
251 | 264 | ||
252 | writel(cur, reg); | 265 | writel(cur, reg); |
266 | |||
267 | if (chip == -1 && allow_clk_stop(info)) | ||
268 | clk_disable(info->clk); | ||
253 | } | 269 | } |
254 | 270 | ||
255 | /* command and control functions | 271 | /* s3c2410_nand_hwcontrol |
256 | * | ||
257 | * Note, these all use tglx's method of changing the IO_ADDR_W field | ||
258 | * to make the code simpler, and use the nand layer's code to issue the | ||
259 | * command and address sequences via the proper IO ports. | ||
260 | * | 272 | * |
273 | * Issue command and address cycles to the chip | ||
261 | */ | 274 | */ |
262 | 275 | ||
263 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd) | 276 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
277 | unsigned int ctrl) | ||
264 | { | 278 | { |
265 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | 279 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
266 | struct nand_chip *chip = mtd->priv; | 280 | |
267 | 281 | if (cmd == NAND_CMD_NONE) | |
268 | switch (cmd) { | 282 | return; |
269 | case NAND_CTL_SETNCE: | 283 | |
270 | case NAND_CTL_CLRNCE: | 284 | if (ctrl & NAND_CLE) |
271 | printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); | 285 | writeb(cmd, info->regs + S3C2410_NFCMD); |
272 | break; | 286 | else |
273 | 287 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
274 | case NAND_CTL_SETCLE: | ||
275 | chip->IO_ADDR_W = info->regs + S3C2410_NFCMD; | ||
276 | break; | ||
277 | |||
278 | case NAND_CTL_SETALE: | ||
279 | chip->IO_ADDR_W = info->regs + S3C2410_NFADDR; | ||
280 | break; | ||
281 | |||
282 | /* NAND_CTL_CLRCLE: */ | ||
283 | /* NAND_CTL_CLRALE: */ | ||
284 | default: | ||
285 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; | ||
286 | break; | ||
287 | } | ||
288 | } | 288 | } |
289 | 289 | ||
290 | /* command and control functions */ | 290 | /* command and control functions */ |
291 | 291 | ||
292 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) | 292 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
293 | unsigned int ctrl) | ||
293 | { | 294 | { |
294 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | 295 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
295 | struct nand_chip *chip = mtd->priv; | 296 | |
296 | 297 | if (cmd == NAND_CMD_NONE) | |
297 | switch (cmd) { | 298 | return; |
298 | case NAND_CTL_SETNCE: | 299 | |
299 | case NAND_CTL_CLRNCE: | 300 | if (ctrl & NAND_CLE) |
300 | printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); | 301 | writeb(cmd, info->regs + S3C2440_NFCMD); |
301 | break; | 302 | else |
302 | 303 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
303 | case NAND_CTL_SETCLE: | ||
304 | chip->IO_ADDR_W = info->regs + S3C2440_NFCMD; | ||
305 | break; | ||
306 | |||
307 | case NAND_CTL_SETALE: | ||
308 | chip->IO_ADDR_W = info->regs + S3C2440_NFADDR; | ||
309 | break; | ||
310 | |||
311 | /* NAND_CTL_CLRCLE: */ | ||
312 | /* NAND_CTL_CLRALE: */ | ||
313 | default: | ||
314 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; | ||
315 | break; | ||
316 | } | ||
317 | } | 304 | } |
318 | 305 | ||
319 | /* s3c2410_nand_devready() | 306 | /* s3c2410_nand_devready() |
@@ -330,22 +317,16 @@ static int s3c2410_nand_devready(struct mtd_info *mtd) | |||
330 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; | 317 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
331 | } | 318 | } |
332 | 319 | ||
333 | |||
334 | /* ECC handling functions */ | 320 | /* ECC handling functions */ |
335 | 321 | ||
336 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, | 322 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) |
337 | u_char *read_ecc, u_char *calc_ecc) | ||
338 | { | 323 | { |
339 | pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", | 324 | pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc); |
340 | mtd, dat, read_ecc, calc_ecc); | ||
341 | 325 | ||
342 | pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", | 326 | pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", |
343 | read_ecc[0], read_ecc[1], read_ecc[2], | 327 | read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]); |
344 | calc_ecc[0], calc_ecc[1], calc_ecc[2]); | ||
345 | 328 | ||
346 | if (read_ecc[0] == calc_ecc[0] && | 329 | if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2]) |
347 | read_ecc[1] == calc_ecc[1] && | ||
348 | read_ecc[2] == calc_ecc[2]) | ||
349 | return 0; | 330 | return 0; |
350 | 331 | ||
351 | /* we curently have no method for correcting the error */ | 332 | /* we curently have no method for correcting the error */ |
@@ -378,8 +359,7 @@ static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |||
378 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | 359 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); |
379 | } | 360 | } |
380 | 361 | ||
381 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, | 362 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
382 | const u_char *dat, u_char *ecc_code) | ||
383 | { | 363 | { |
384 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | 364 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
385 | 365 | ||
@@ -387,15 +367,12 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, | |||
387 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | 367 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); |
388 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | 368 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); |
389 | 369 | ||
390 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", | 370 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
391 | ecc_code[0], ecc_code[1], ecc_code[2]); | ||
392 | 371 | ||
393 | return 0; | 372 | return 0; |
394 | } | 373 | } |
395 | 374 | ||
396 | 375 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) | |
397 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, | ||
398 | const u_char *dat, u_char *ecc_code) | ||
399 | { | 376 | { |
400 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | 377 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
401 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | 378 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); |
@@ -404,13 +381,11 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, | |||
404 | ecc_code[1] = ecc >> 8; | 381 | ecc_code[1] = ecc >> 8; |
405 | ecc_code[2] = ecc >> 16; | 382 | ecc_code[2] = ecc >> 16; |
406 | 383 | ||
407 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", | 384 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
408 | ecc_code[0], ecc_code[1], ecc_code[2]); | ||
409 | 385 | ||
410 | return 0; | 386 | return 0; |
411 | } | 387 | } |
412 | 388 | ||
413 | |||
414 | /* over-ride the standard functions for a little more speed. We can | 389 | /* over-ride the standard functions for a little more speed. We can |
415 | * use read/write block to move the data buffers to/from the controller | 390 | * use read/write block to move the data buffers to/from the controller |
416 | */ | 391 | */ |
@@ -421,8 +396,7 @@ static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |||
421 | readsb(this->IO_ADDR_R, buf, len); | 396 | readsb(this->IO_ADDR_R, buf, len); |
422 | } | 397 | } |
423 | 398 | ||
424 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, | 399 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
425 | const u_char *buf, int len) | ||
426 | { | 400 | { |
427 | struct nand_chip *this = mtd->priv; | 401 | struct nand_chip *this = mtd->priv; |
428 | writesb(this->IO_ADDR_W, buf, len); | 402 | writesb(this->IO_ADDR_W, buf, len); |
@@ -459,7 +433,8 @@ static int s3c2410_nand_remove(struct platform_device *pdev) | |||
459 | /* free the common resources */ | 433 | /* free the common resources */ |
460 | 434 | ||
461 | if (info->clk != NULL && !IS_ERR(info->clk)) { | 435 | if (info->clk != NULL && !IS_ERR(info->clk)) { |
462 | clk_disable(info->clk); | 436 | if (!allow_clk_stop(info)) |
437 | clk_disable(info->clk); | ||
463 | clk_put(info->clk); | 438 | clk_put(info->clk); |
464 | } | 439 | } |
465 | 440 | ||
@@ -488,9 +463,7 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, | |||
488 | return add_mtd_device(&mtd->mtd); | 463 | return add_mtd_device(&mtd->mtd); |
489 | 464 | ||
490 | if (set->nr_partitions > 0 && set->partitions != NULL) { | 465 | if (set->nr_partitions > 0 && set->partitions != NULL) { |
491 | return add_mtd_partitions(&mtd->mtd, | 466 | return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions); |
492 | set->partitions, | ||
493 | set->nr_partitions); | ||
494 | } | 467 | } |
495 | 468 | ||
496 | return add_mtd_device(&mtd->mtd); | 469 | return add_mtd_device(&mtd->mtd); |
@@ -517,7 +490,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, | |||
517 | 490 | ||
518 | chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; | 491 | chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; |
519 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; | 492 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; |
520 | chip->hwcontrol = s3c2410_nand_hwcontrol; | 493 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; |
521 | chip->dev_ready = s3c2410_nand_devready; | 494 | chip->dev_ready = s3c2410_nand_devready; |
522 | chip->write_buf = s3c2410_nand_write_buf; | 495 | chip->write_buf = s3c2410_nand_write_buf; |
523 | chip->read_buf = s3c2410_nand_read_buf; | 496 | chip->read_buf = s3c2410_nand_read_buf; |
@@ -530,26 +503,29 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, | |||
530 | if (info->is_s3c2440) { | 503 | if (info->is_s3c2440) { |
531 | chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; | 504 | chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; |
532 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; | 505 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; |
533 | chip->hwcontrol = s3c2440_nand_hwcontrol; | 506 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
534 | } | 507 | } |
535 | 508 | ||
536 | nmtd->info = info; | 509 | nmtd->info = info; |
537 | nmtd->mtd.priv = chip; | 510 | nmtd->mtd.priv = chip; |
511 | nmtd->mtd.owner = THIS_MODULE; | ||
538 | nmtd->set = set; | 512 | nmtd->set = set; |
539 | 513 | ||
540 | if (hardware_ecc) { | 514 | if (hardware_ecc) { |
541 | chip->correct_data = s3c2410_nand_correct_data; | 515 | chip->ecc.correct = s3c2410_nand_correct_data; |
542 | chip->enable_hwecc = s3c2410_nand_enable_hwecc; | 516 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; |
543 | chip->calculate_ecc = s3c2410_nand_calculate_ecc; | 517 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
544 | chip->eccmode = NAND_ECC_HW3_512; | 518 | chip->ecc.mode = NAND_ECC_HW; |
545 | chip->autooob = &nand_hw_eccoob; | 519 | chip->ecc.size = 512; |
520 | chip->ecc.bytes = 3; | ||
521 | chip->ecc.layout = &nand_hw_eccoob; | ||
546 | 522 | ||
547 | if (info->is_s3c2440) { | 523 | if (info->is_s3c2440) { |
548 | chip->enable_hwecc = s3c2440_nand_enable_hwecc; | 524 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; |
549 | chip->calculate_ecc = s3c2440_nand_calculate_ecc; | 525 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; |
550 | } | 526 | } |
551 | } else { | 527 | } else { |
552 | chip->eccmode = NAND_ECC_SOFT; | 528 | chip->ecc.mode = NAND_ECC_SOFT; |
553 | } | 529 | } |
554 | } | 530 | } |
555 | 531 | ||
@@ -654,13 +630,11 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) | |||
654 | nmtd = info->mtds; | 630 | nmtd = info->mtds; |
655 | 631 | ||
656 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | 632 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { |
657 | pr_debug("initialising set %d (%p, info %p)\n", | 633 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
658 | setno, nmtd, info); | ||
659 | 634 | ||
660 | s3c2410_nand_init_chip(info, nmtd, sets); | 635 | s3c2410_nand_init_chip(info, nmtd, sets); |
661 | 636 | ||
662 | nmtd->scan_res = nand_scan(&nmtd->mtd, | 637 | nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1); |
663 | (sets) ? sets->nr_chips : 1); | ||
664 | 638 | ||
665 | if (nmtd->scan_res == 0) { | 639 | if (nmtd->scan_res == 0) { |
666 | s3c2410_nand_add_partition(info, nmtd, sets); | 640 | s3c2410_nand_add_partition(info, nmtd, sets); |
@@ -670,6 +644,11 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) | |||
670 | sets++; | 644 | sets++; |
671 | } | 645 | } |
672 | 646 | ||
647 | if (allow_clk_stop(info)) { | ||
648 | dev_info(&pdev->dev, "clock idle support enabled\n"); | ||
649 | clk_disable(info->clk); | ||
650 | } | ||
651 | |||
673 | pr_debug("initialised ok\n"); | 652 | pr_debug("initialised ok\n"); |
674 | return 0; | 653 | return 0; |
675 | 654 | ||
@@ -681,6 +660,41 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) | |||
681 | return err; | 660 | return err; |
682 | } | 661 | } |
683 | 662 | ||
663 | /* PM Support */ | ||
664 | #ifdef CONFIG_PM | ||
665 | |||
666 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | ||
667 | { | ||
668 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | ||
669 | |||
670 | if (info) { | ||
671 | if (!allow_clk_stop(info)) | ||
672 | clk_disable(info->clk); | ||
673 | } | ||
674 | |||
675 | return 0; | ||
676 | } | ||
677 | |||
678 | static int s3c24xx_nand_resume(struct platform_device *dev) | ||
679 | { | ||
680 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | ||
681 | |||
682 | if (info) { | ||
683 | clk_enable(info->clk); | ||
684 | s3c2410_nand_inithw(info, dev); | ||
685 | |||
686 | if (allow_clk_stop(info)) | ||
687 | clk_disable(info->clk); | ||
688 | } | ||
689 | |||
690 | return 0; | ||
691 | } | ||
692 | |||
693 | #else | ||
694 | #define s3c24xx_nand_suspend NULL | ||
695 | #define s3c24xx_nand_resume NULL | ||
696 | #endif | ||
697 | |||
684 | /* driver device registration */ | 698 | /* driver device registration */ |
685 | 699 | ||
686 | static int s3c2410_nand_probe(struct platform_device *dev) | 700 | static int s3c2410_nand_probe(struct platform_device *dev) |
@@ -696,6 +710,8 @@ static int s3c2440_nand_probe(struct platform_device *dev) | |||
696 | static struct platform_driver s3c2410_nand_driver = { | 710 | static struct platform_driver s3c2410_nand_driver = { |
697 | .probe = s3c2410_nand_probe, | 711 | .probe = s3c2410_nand_probe, |
698 | .remove = s3c2410_nand_remove, | 712 | .remove = s3c2410_nand_remove, |
713 | .suspend = s3c24xx_nand_suspend, | ||
714 | .resume = s3c24xx_nand_resume, | ||
699 | .driver = { | 715 | .driver = { |
700 | .name = "s3c2410-nand", | 716 | .name = "s3c2410-nand", |
701 | .owner = THIS_MODULE, | 717 | .owner = THIS_MODULE, |
@@ -705,6 +721,8 @@ static struct platform_driver s3c2410_nand_driver = { | |||
705 | static struct platform_driver s3c2440_nand_driver = { | 721 | static struct platform_driver s3c2440_nand_driver = { |
706 | .probe = s3c2440_nand_probe, | 722 | .probe = s3c2440_nand_probe, |
707 | .remove = s3c2410_nand_remove, | 723 | .remove = s3c2410_nand_remove, |
724 | .suspend = s3c24xx_nand_suspend, | ||
725 | .resume = s3c24xx_nand_resume, | ||
708 | .driver = { | 726 | .driver = { |
709 | .name = "s3c2440-nand", | 727 | .name = "s3c2440-nand", |
710 | .owner = THIS_MODULE, | 728 | .owner = THIS_MODULE, |