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Diffstat (limited to 'drivers/mtd/nand/pxa3xx_nand.c')
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index fc4144495610..cc55cbc2b308 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -298,7 +298,7 @@ static struct pxa3xx_nand_flash *builtin_flash_types[] = {
298#define NDTR1_tAR(c) (min((c), 15) << 0) 298#define NDTR1_tAR(c) (min((c), 15) << 0)
299 299
300/* convert nano-seconds to nand flash controller clock cycles */ 300/* convert nano-seconds to nand flash controller clock cycles */
301#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) + 1) 301#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1)
302 302
303static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info, 303static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
304 const struct pxa3xx_nand_timing *t) 304 const struct pxa3xx_nand_timing *t)
@@ -368,14 +368,14 @@ static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
368 /* large block, 2 cycles for column address 368 /* large block, 2 cycles for column address
369 * row address starts from 3rd cycle 369 * row address starts from 3rd cycle
370 */ 370 */
371 info->ndcb1 |= (page_addr << 16) | (column & 0xffff); 371 info->ndcb1 |= page_addr << 16;
372 if (info->row_addr_cycles == 3) 372 if (info->row_addr_cycles == 3)
373 info->ndcb2 = (page_addr >> 16) & 0xff; 373 info->ndcb2 = (page_addr >> 16) & 0xff;
374 } else 374 } else
375 /* small block, 1 cycles for column address 375 /* small block, 1 cycles for column address
376 * row address starts from 2nd cycle 376 * row address starts from 2nd cycle
377 */ 377 */
378 info->ndcb1 = (page_addr << 8) | (column & 0xff); 378 info->ndcb1 = page_addr << 8;
379 379
380 if (cmd == cmdset->program) 380 if (cmd == cmdset->program)
381 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS; 381 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;