aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/mtd/nand/denali.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/mtd/nand/denali.h')
-rw-r--r--drivers/mtd/nand/denali.h140
1 files changed, 49 insertions, 91 deletions
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index 422a29ab2f60..b680474e6333 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -17,7 +17,7 @@
17 * 17 *
18 */ 18 */
19 19
20#include <linux/mtd/nand.h> 20#include <linux/mtd/nand.h>
21 21
22#define DEVICE_RESET 0x0 22#define DEVICE_RESET 0x0
23#define DEVICE_RESET__BANK0 0x0001 23#define DEVICE_RESET__BANK0 0x0001
@@ -29,7 +29,7 @@
29#define TRANSFER_SPARE_REG__FLAG 0x0001 29#define TRANSFER_SPARE_REG__FLAG 0x0001
30 30
31#define LOAD_WAIT_CNT 0x20 31#define LOAD_WAIT_CNT 0x20
32#define LOAD_WAIT_CNT__VALUE 0xffff 32#define LOAD_WAIT_CNT__VALUE 0xffff
33 33
34#define PROGRAM_WAIT_CNT 0x30 34#define PROGRAM_WAIT_CNT 0x30
35#define PROGRAM_WAIT_CNT__VALUE 0xffff 35#define PROGRAM_WAIT_CNT__VALUE 0xffff
@@ -83,7 +83,7 @@
83#define RE_2_WE 0x120 83#define RE_2_WE 0x120
84#define RE_2_WE__VALUE 0x003f 84#define RE_2_WE__VALUE 0x003f
85 85
86#define ACC_CLKS 0x130 86#define ACC_CLKS 0x130
87#define ACC_CLKS__VALUE 0x000f 87#define ACC_CLKS__VALUE 0x000f
88 88
89#define NUMBER_OF_PLANES 0x140 89#define NUMBER_OF_PLANES 0x140
@@ -140,7 +140,7 @@
140#define DEVICES_CONNECTED 0x250 140#define DEVICES_CONNECTED 0x250
141#define DEVICES_CONNECTED__VALUE 0x0007 141#define DEVICES_CONNECTED__VALUE 0x0007
142 142
143#define DIE_MASK 0x260 143#define DIE_MASK 0x260
144#define DIE_MASK__VALUE 0x00ff 144#define DIE_MASK__VALUE 0x00ff
145 145
146#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 146#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
@@ -152,7 +152,7 @@
152#define RE_2_RE 0x290 152#define RE_2_RE 0x290
153#define RE_2_RE__VALUE 0x003f 153#define RE_2_RE__VALUE 0x003f
154 154
155#define MANUFACTURER_ID 0x300 155#define MANUFACTURER_ID 0x300
156#define MANUFACTURER_ID__VALUE 0x00ff 156#define MANUFACTURER_ID__VALUE 0x00ff
157 157
158#define DEVICE_ID 0x310 158#define DEVICE_ID 0x310
@@ -173,13 +173,13 @@
173#define LOGICAL_PAGE_SPARE_SIZE 0x360 173#define LOGICAL_PAGE_SPARE_SIZE 0x360
174#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff 174#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
175 175
176#define REVISION 0x370 176#define REVISION 0x370
177#define REVISION__VALUE 0xffff 177#define REVISION__VALUE 0xffff
178 178
179#define ONFI_DEVICE_FEATURES 0x380 179#define ONFI_DEVICE_FEATURES 0x380
180#define ONFI_DEVICE_FEATURES__VALUE 0x003f 180#define ONFI_DEVICE_FEATURES__VALUE 0x003f
181 181
182#define ONFI_OPTIONAL_COMMANDS 0x390 182#define ONFI_OPTIONAL_COMMANDS 0x390
183#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f 183#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
184 184
185#define ONFI_TIMING_MODE 0x3a0 185#define ONFI_TIMING_MODE 0x3a0
@@ -201,12 +201,12 @@
201#define FEATURES 0x3f0 201#define FEATURES 0x3f0
202#define FEATURES__N_BANKS 0x0003 202#define FEATURES__N_BANKS 0x0003
203#define FEATURES__ECC_MAX_ERR 0x003c 203#define FEATURES__ECC_MAX_ERR 0x003c
204#define FEATURES__DMA 0x0040 204#define FEATURES__DMA 0x0040
205#define FEATURES__CMD_DMA 0x0080 205#define FEATURES__CMD_DMA 0x0080
206#define FEATURES__PARTITION 0x0100 206#define FEATURES__PARTITION 0x0100
207#define FEATURES__XDMA_SIDEBAND 0x0200 207#define FEATURES__XDMA_SIDEBAND 0x0200
208#define FEATURES__GPREG 0x0400 208#define FEATURES__GPREG 0x0400
209#define FEATURES__INDEX_ADDR 0x0800 209#define FEATURES__INDEX_ADDR 0x0800
210 210
211#define TRANSFER_MODE 0x400 211#define TRANSFER_MODE 0x400
212#define TRANSFER_MODE__VALUE 0x0003 212#define TRANSFER_MODE__VALUE 0x0003
@@ -235,12 +235,12 @@
235#define INTR_EN0__DMA_CMD_COMP 0x0004 235#define INTR_EN0__DMA_CMD_COMP 0x0004
236#define INTR_EN0__TIME_OUT 0x0008 236#define INTR_EN0__TIME_OUT 0x0008
237#define INTR_EN0__PROGRAM_FAIL 0x0010 237#define INTR_EN0__PROGRAM_FAIL 0x0010
238#define INTR_EN0__ERASE_FAIL 0x0020 238#define INTR_EN0__ERASE_FAIL 0x0020
239#define INTR_EN0__LOAD_COMP 0x0040 239#define INTR_EN0__LOAD_COMP 0x0040
240#define INTR_EN0__PROGRAM_COMP 0x0080 240#define INTR_EN0__PROGRAM_COMP 0x0080
241#define INTR_EN0__ERASE_COMP 0x0100 241#define INTR_EN0__ERASE_COMP 0x0100
242#define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200 242#define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200
243#define INTR_EN0__LOCKED_BLK 0x0400 243#define INTR_EN0__LOCKED_BLK 0x0400
244#define INTR_EN0__UNSUP_CMD 0x0800 244#define INTR_EN0__UNSUP_CMD 0x0800
245#define INTR_EN0__INT_ACT 0x1000 245#define INTR_EN0__INT_ACT 0x1000
246#define INTR_EN0__RST_COMP 0x2000 246#define INTR_EN0__RST_COMP 0x2000
@@ -253,7 +253,7 @@
253#define ERR_PAGE_ADDR0 0x440 253#define ERR_PAGE_ADDR0 0x440
254#define ERR_PAGE_ADDR0__VALUE 0xffff 254#define ERR_PAGE_ADDR0__VALUE 0xffff
255 255
256#define ERR_BLOCK_ADDR0 0x450 256#define ERR_BLOCK_ADDR0 0x450
257#define ERR_BLOCK_ADDR0__VALUE 0xffff 257#define ERR_BLOCK_ADDR0__VALUE 0xffff
258 258
259#define INTR_STATUS1 0x460 259#define INTR_STATUS1 0x460
@@ -280,12 +280,12 @@
280#define INTR_EN1__DMA_CMD_COMP 0x0004 280#define INTR_EN1__DMA_CMD_COMP 0x0004
281#define INTR_EN1__TIME_OUT 0x0008 281#define INTR_EN1__TIME_OUT 0x0008
282#define INTR_EN1__PROGRAM_FAIL 0x0010 282#define INTR_EN1__PROGRAM_FAIL 0x0010
283#define INTR_EN1__ERASE_FAIL 0x0020 283#define INTR_EN1__ERASE_FAIL 0x0020
284#define INTR_EN1__LOAD_COMP 0x0040 284#define INTR_EN1__LOAD_COMP 0x0040
285#define INTR_EN1__PROGRAM_COMP 0x0080 285#define INTR_EN1__PROGRAM_COMP 0x0080
286#define INTR_EN1__ERASE_COMP 0x0100 286#define INTR_EN1__ERASE_COMP 0x0100
287#define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200 287#define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200
288#define INTR_EN1__LOCKED_BLK 0x0400 288#define INTR_EN1__LOCKED_BLK 0x0400
289#define INTR_EN1__UNSUP_CMD 0x0800 289#define INTR_EN1__UNSUP_CMD 0x0800
290#define INTR_EN1__INT_ACT 0x1000 290#define INTR_EN1__INT_ACT 0x1000
291#define INTR_EN1__RST_COMP 0x2000 291#define INTR_EN1__RST_COMP 0x2000
@@ -298,7 +298,7 @@
298#define ERR_PAGE_ADDR1 0x490 298#define ERR_PAGE_ADDR1 0x490
299#define ERR_PAGE_ADDR1__VALUE 0xffff 299#define ERR_PAGE_ADDR1__VALUE 0xffff
300 300
301#define ERR_BLOCK_ADDR1 0x4a0 301#define ERR_BLOCK_ADDR1 0x4a0
302#define ERR_BLOCK_ADDR1__VALUE 0xffff 302#define ERR_BLOCK_ADDR1__VALUE 0xffff
303 303
304#define INTR_STATUS2 0x4b0 304#define INTR_STATUS2 0x4b0
@@ -325,12 +325,12 @@
325#define INTR_EN2__DMA_CMD_COMP 0x0004 325#define INTR_EN2__DMA_CMD_COMP 0x0004
326#define INTR_EN2__TIME_OUT 0x0008 326#define INTR_EN2__TIME_OUT 0x0008
327#define INTR_EN2__PROGRAM_FAIL 0x0010 327#define INTR_EN2__PROGRAM_FAIL 0x0010
328#define INTR_EN2__ERASE_FAIL 0x0020 328#define INTR_EN2__ERASE_FAIL 0x0020
329#define INTR_EN2__LOAD_COMP 0x0040 329#define INTR_EN2__LOAD_COMP 0x0040
330#define INTR_EN2__PROGRAM_COMP 0x0080 330#define INTR_EN2__PROGRAM_COMP 0x0080
331#define INTR_EN2__ERASE_COMP 0x0100 331#define INTR_EN2__ERASE_COMP 0x0100
332#define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200 332#define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200
333#define INTR_EN2__LOCKED_BLK 0x0400 333#define INTR_EN2__LOCKED_BLK 0x0400
334#define INTR_EN2__UNSUP_CMD 0x0800 334#define INTR_EN2__UNSUP_CMD 0x0800
335#define INTR_EN2__INT_ACT 0x1000 335#define INTR_EN2__INT_ACT 0x1000
336#define INTR_EN2__RST_COMP 0x2000 336#define INTR_EN2__RST_COMP 0x2000
@@ -343,7 +343,7 @@
343#define ERR_PAGE_ADDR2 0x4e0 343#define ERR_PAGE_ADDR2 0x4e0
344#define ERR_PAGE_ADDR2__VALUE 0xffff 344#define ERR_PAGE_ADDR2__VALUE 0xffff
345 345
346#define ERR_BLOCK_ADDR2 0x4f0 346#define ERR_BLOCK_ADDR2 0x4f0
347#define ERR_BLOCK_ADDR2__VALUE 0xffff 347#define ERR_BLOCK_ADDR2__VALUE 0xffff
348 348
349#define INTR_STATUS3 0x500 349#define INTR_STATUS3 0x500
@@ -370,12 +370,12 @@
370#define INTR_EN3__DMA_CMD_COMP 0x0004 370#define INTR_EN3__DMA_CMD_COMP 0x0004
371#define INTR_EN3__TIME_OUT 0x0008 371#define INTR_EN3__TIME_OUT 0x0008
372#define INTR_EN3__PROGRAM_FAIL 0x0010 372#define INTR_EN3__PROGRAM_FAIL 0x0010
373#define INTR_EN3__ERASE_FAIL 0x0020 373#define INTR_EN3__ERASE_FAIL 0x0020
374#define INTR_EN3__LOAD_COMP 0x0040 374#define INTR_EN3__LOAD_COMP 0x0040
375#define INTR_EN3__PROGRAM_COMP 0x0080 375#define INTR_EN3__PROGRAM_COMP 0x0080
376#define INTR_EN3__ERASE_COMP 0x0100 376#define INTR_EN3__ERASE_COMP 0x0100
377#define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200 377#define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200
378#define INTR_EN3__LOCKED_BLK 0x0400 378#define INTR_EN3__LOCKED_BLK 0x0400
379#define INTR_EN3__UNSUP_CMD 0x0800 379#define INTR_EN3__UNSUP_CMD 0x0800
380#define INTR_EN3__INT_ACT 0x1000 380#define INTR_EN3__INT_ACT 0x1000
381#define INTR_EN3__RST_COMP 0x2000 381#define INTR_EN3__RST_COMP 0x2000
@@ -388,7 +388,7 @@
388#define ERR_PAGE_ADDR3 0x530 388#define ERR_PAGE_ADDR3 0x530
389#define ERR_PAGE_ADDR3__VALUE 0xffff 389#define ERR_PAGE_ADDR3__VALUE 0xffff
390 390
391#define ERR_BLOCK_ADDR3 0x540 391#define ERR_BLOCK_ADDR3 0x540
392#define ERR_BLOCK_ADDR3__VALUE 0xffff 392#define ERR_BLOCK_ADDR3__VALUE 0xffff
393 393
394#define DATA_INTR 0x550 394#define DATA_INTR 0x550
@@ -412,9 +412,9 @@
412#define GPREG_3__VALUE 0xffff 412#define GPREG_3__VALUE 0xffff
413 413
414#define ECC_THRESHOLD 0x600 414#define ECC_THRESHOLD 0x600
415#define ECC_THRESHOLD__VALUE 0x03ff 415#define ECC_THRESHOLD__VALUE 0x03ff
416 416
417#define ECC_ERROR_BLOCK_ADDRESS 0x610 417#define ECC_ERROR_BLOCK_ADDRESS 0x610
418#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff 418#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
419 419
420#define ECC_ERROR_PAGE_ADDRESS 0x620 420#define ECC_ERROR_PAGE_ADDRESS 0x620
@@ -466,7 +466,7 @@
466#define CHNL_ACTIVE__CHANNEL3 0x0008 466#define CHNL_ACTIVE__CHANNEL3 0x0008
467 467
468#define ACTIVE_SRC_ID 0x800 468#define ACTIVE_SRC_ID 0x800
469#define ACTIVE_SRC_ID__VALUE 0x00ff 469#define ACTIVE_SRC_ID__VALUE 0x00ff
470 470
471#define PTN_INTR 0x810 471#define PTN_INTR 0x810
472#define PTN_INTR__CONFIG_ERROR 0x0001 472#define PTN_INTR__CONFIG_ERROR 0x0001
@@ -485,7 +485,7 @@
485#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 485#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
486 486
487#define PERM_SRC_ID_0 0x830 487#define PERM_SRC_ID_0 0x830
488#define PERM_SRC_ID_0__SRCID 0x00ff 488#define PERM_SRC_ID_0__SRCID 0x00ff
489#define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800 489#define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800
490#define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000 490#define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000
491#define PERM_SRC_ID_0__READ_ACTIVE 0x4000 491#define PERM_SRC_ID_0__READ_ACTIVE 0x4000
@@ -502,7 +502,7 @@
502#define MIN_MAX_BANK_0__MAX_VALUE 0x000c 502#define MIN_MAX_BANK_0__MAX_VALUE 0x000c
503 503
504#define PERM_SRC_ID_1 0x870 504#define PERM_SRC_ID_1 0x870
505#define PERM_SRC_ID_1__SRCID 0x00ff 505#define PERM_SRC_ID_1__SRCID 0x00ff
506#define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800 506#define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800
507#define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000 507#define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000
508#define PERM_SRC_ID_1__READ_ACTIVE 0x4000 508#define PERM_SRC_ID_1__READ_ACTIVE 0x4000
@@ -519,7 +519,7 @@
519#define MIN_MAX_BANK_1__MAX_VALUE 0x000c 519#define MIN_MAX_BANK_1__MAX_VALUE 0x000c
520 520
521#define PERM_SRC_ID_2 0x8b0 521#define PERM_SRC_ID_2 0x8b0
522#define PERM_SRC_ID_2__SRCID 0x00ff 522#define PERM_SRC_ID_2__SRCID 0x00ff
523#define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800 523#define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800
524#define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000 524#define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000
525#define PERM_SRC_ID_2__READ_ACTIVE 0x4000 525#define PERM_SRC_ID_2__READ_ACTIVE 0x4000
@@ -536,7 +536,7 @@
536#define MIN_MAX_BANK_2__MAX_VALUE 0x000c 536#define MIN_MAX_BANK_2__MAX_VALUE 0x000c
537 537
538#define PERM_SRC_ID_3 0x8f0 538#define PERM_SRC_ID_3 0x8f0
539#define PERM_SRC_ID_3__SRCID 0x00ff 539#define PERM_SRC_ID_3__SRCID 0x00ff
540#define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800 540#define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800
541#define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000 541#define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000
542#define PERM_SRC_ID_3__READ_ACTIVE 0x4000 542#define PERM_SRC_ID_3__READ_ACTIVE 0x4000
@@ -553,7 +553,7 @@
553#define MIN_MAX_BANK_3__MAX_VALUE 0x000c 553#define MIN_MAX_BANK_3__MAX_VALUE 0x000c
554 554
555#define PERM_SRC_ID_4 0x930 555#define PERM_SRC_ID_4 0x930
556#define PERM_SRC_ID_4__SRCID 0x00ff 556#define PERM_SRC_ID_4__SRCID 0x00ff
557#define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800 557#define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800
558#define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000 558#define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000
559#define PERM_SRC_ID_4__READ_ACTIVE 0x4000 559#define PERM_SRC_ID_4__READ_ACTIVE 0x4000
@@ -570,7 +570,7 @@
570#define MIN_MAX_BANK_4__MAX_VALUE 0x000c 570#define MIN_MAX_BANK_4__MAX_VALUE 0x000c
571 571
572#define PERM_SRC_ID_5 0x970 572#define PERM_SRC_ID_5 0x970
573#define PERM_SRC_ID_5__SRCID 0x00ff 573#define PERM_SRC_ID_5__SRCID 0x00ff
574#define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800 574#define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800
575#define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000 575#define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000
576#define PERM_SRC_ID_5__READ_ACTIVE 0x4000 576#define PERM_SRC_ID_5__READ_ACTIVE 0x4000
@@ -587,7 +587,7 @@
587#define MIN_MAX_BANK_5__MAX_VALUE 0x000c 587#define MIN_MAX_BANK_5__MAX_VALUE 0x000c
588 588
589#define PERM_SRC_ID_6 0x9b0 589#define PERM_SRC_ID_6 0x9b0
590#define PERM_SRC_ID_6__SRCID 0x00ff 590#define PERM_SRC_ID_6__SRCID 0x00ff
591#define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800 591#define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800
592#define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000 592#define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000
593#define PERM_SRC_ID_6__READ_ACTIVE 0x4000 593#define PERM_SRC_ID_6__READ_ACTIVE 0x4000
@@ -604,7 +604,7 @@
604#define MIN_MAX_BANK_6__MAX_VALUE 0x000c 604#define MIN_MAX_BANK_6__MAX_VALUE 0x000c
605 605
606#define PERM_SRC_ID_7 0x9f0 606#define PERM_SRC_ID_7 0x9f0
607#define PERM_SRC_ID_7__SRCID 0x00ff 607#define PERM_SRC_ID_7__SRCID 0x00ff
608#define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800 608#define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800
609#define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000 609#define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000
610#define PERM_SRC_ID_7__READ_ACTIVE 0x4000 610#define PERM_SRC_ID_7__READ_ACTIVE 0x4000
@@ -620,47 +620,6 @@
620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003 620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003
621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c 621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c
622 622
623/* flash.h */
624struct device_info_tag {
625 uint16_t wDeviceMaker;
626 uint16_t wDeviceID;
627 uint8_t bDeviceParam0;
628 uint8_t bDeviceParam1;
629 uint8_t bDeviceParam2;
630 uint32_t wDeviceType;
631 uint32_t wSpectraStartBlock;
632 uint32_t wSpectraEndBlock;
633 uint32_t wTotalBlocks;
634 uint16_t wPagesPerBlock;
635 uint16_t wPageSize;
636 uint16_t wPageDataSize;
637 uint16_t wPageSpareSize;
638 uint16_t wNumPageSpareFlag;
639 uint16_t wECCBytesPerSector;
640 uint32_t wBlockSize;
641 uint32_t wBlockDataSize;
642 uint32_t wDataBlockNum;
643 uint8_t bPlaneNum;
644 uint16_t wDeviceMainAreaSize;
645 uint16_t wDeviceSpareAreaSize;
646 uint16_t wDevicesConnected;
647 uint16_t wDeviceWidth;
648 uint16_t wHWRevision;
649 uint16_t wHWFeatures;
650
651 uint16_t wONFIDevFeatures;
652 uint16_t wONFIOptCommands;
653 uint16_t wONFITimingMode;
654 uint16_t wONFIPgmCacheTimingMode;
655
656 uint16_t MLCDevice;
657 uint16_t wSpareSkipBytes;
658
659 uint8_t nBitsInPageNumber;
660 uint8_t nBitsInPageDataSize;
661 uint8_t nBitsInBlockDataSize;
662};
663
664/* ffsdefs.h */ 623/* ffsdefs.h */
665#define CLEAR 0 /*use this to clear a field instead of "fail"*/ 624#define CLEAR 0 /*use this to clear a field instead of "fail"*/
666#define SET 1 /*use this to set a field instead of "pass"*/ 625#define SET 1 /*use this to set a field instead of "pass"*/
@@ -684,11 +643,11 @@ struct device_info_tag {
684#define NAND_DBG_TRACE 3 643#define NAND_DBG_TRACE 3
685 644
686#ifdef VERBOSE 645#ifdef VERBOSE
687#define nand_dbg_print(level, args...) \ 646#define nand_dbg_print(level, args...) \
688 do { \ 647 do { \
689 if (level <= nand_debug_level) \ 648 if (level <= nand_debug_level) \
690 printk(KERN_ALERT args); \ 649 printk(KERN_ALERT args); \
691 } while (0) 650 } while (0)
692#else 651#else
693#define nand_dbg_print(level, args...) 652#define nand_dbg_print(level, args...)
694#endif 653#endif
@@ -772,10 +731,9 @@ struct device_info_tag {
772#define ECC_SECTOR_SIZE 512 731#define ECC_SECTOR_SIZE 512
773#define LLD_MAX_FLASH_BANKS 4 732#define LLD_MAX_FLASH_BANKS 4
774 733
775#define DENALI_BUF_SIZE NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE 734#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
776 735
777struct nand_buf 736struct nand_buf {
778{
779 int head; 737 int head;
780 int tail; 738 int tail;
781 uint8_t buf[DENALI_BUF_SIZE]; 739 uint8_t buf[DENALI_BUF_SIZE];
@@ -788,7 +746,6 @@ struct nand_buf
788struct denali_nand_info { 746struct denali_nand_info {
789 struct mtd_info mtd; 747 struct mtd_info mtd;
790 struct nand_chip nand; 748 struct nand_chip nand;
791 struct device_info_tag dev_info;
792 int flash_bank; /* currently selected chip */ 749 int flash_bank; /* currently selected chip */
793 int status; 750 int status;
794 int platform; 751 int platform;
@@ -806,11 +763,12 @@ struct denali_nand_info {
806 uint32_t irq_status; 763 uint32_t irq_status;
807 int irq_debug_array[32]; 764 int irq_debug_array[32];
808 int idx; 765 int idx;
809};
810 766
811static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali); 767 uint32_t devnum; /* represent how many nands connected */
812static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali); 768 uint32_t fwblks; /* represent how many blocks FW used */
813static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali, uint16_t INT_ENABLE); 769 uint32_t totalblks;
770 uint32_t blksperchip;
771 uint32_t bbtskipbytes;
772};
814 773
815#endif /*_LLD_NAND_*/ 774#endif /*_LLD_NAND_*/
816
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 14:04:35 -0500