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-rw-r--r--drivers/mtd/nand/denali.c1240
1 files changed, 475 insertions, 765 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 3dfda9cc677d..618fb42b86b0 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -21,6 +21,7 @@
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/wait.h> 22#include <linux/wait.h>
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/slab.h>
24#include <linux/pci.h> 25#include <linux/pci.h>
25#include <linux/mtd/mtd.h> 26#include <linux/mtd/mtd.h>
26#include <linux/module.h> 27#include <linux/module.h>
@@ -29,15 +30,15 @@
29 30
30MODULE_LICENSE("GPL"); 31MODULE_LICENSE("GPL");
31 32
32/* We define a module parameter that allows the user to override 33/* We define a module parameter that allows the user to override
33 * the hardware and decide what timing mode should be used. 34 * the hardware and decide what timing mode should be used.
34 */ 35 */
35#define NAND_DEFAULT_TIMINGS -1 36#define NAND_DEFAULT_TIMINGS -1
36 37
37static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; 38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
38module_param(onfi_timing_mode, int, S_IRUGO); 39module_param(onfi_timing_mode, int, S_IRUGO);
39MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates" 40MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
40 " use default timings"); 41 " -1 indicates use default timings");
41 42
42#define DENALI_NAND_NAME "denali-nand" 43#define DENALI_NAND_NAME "denali-nand"
43 44
@@ -54,13 +55,13 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates
54 INTR_STATUS0__RST_COMP | \ 55 INTR_STATUS0__RST_COMP | \
55 INTR_STATUS0__ERASE_COMP) 56 INTR_STATUS0__ERASE_COMP)
56 57
57/* indicates whether or not the internal value for the flash bank is 58/* indicates whether or not the internal value for the flash bank is
58 valid or not */ 59 valid or not */
59#define CHIP_SELECT_INVALID -1 60#define CHIP_SELECT_INVALID -1
60 61
61#define SUPPORT_8BITECC 1 62#define SUPPORT_8BITECC 1
62 63
63/* This macro divides two integers and rounds fractional values up 64/* This macro divides two integers and rounds fractional values up
64 * to the nearest integer value. */ 65 * to the nearest integer value. */
65#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) 66#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
66 67
@@ -83,7 +84,7 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates
83#define ADDR_CYCLE 1 84#define ADDR_CYCLE 1
84#define STATUS_CYCLE 2 85#define STATUS_CYCLE 2
85 86
86/* this is a helper macro that allows us to 87/* this is a helper macro that allows us to
87 * format the bank into the proper bits for the controller */ 88 * format the bank into the proper bits for the controller */
88#define BANK(x) ((x) << 24) 89#define BANK(x) ((x) << 24)
89 90
@@ -95,59 +96,64 @@ static const struct pci_device_id denali_pci_ids[] = {
95}; 96};
96 97
97 98
98/* these are static lookup tables that give us easy access to 99/* these are static lookup tables that give us easy access to
99 registers in the NAND controller. 100 registers in the NAND controller.
100 */ 101 */
101static const uint32_t intr_status_addresses[4] = {INTR_STATUS0, 102static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
102 INTR_STATUS1, 103 INTR_STATUS1,
103 INTR_STATUS2, 104 INTR_STATUS2,
104 INTR_STATUS3}; 105 INTR_STATUS3};
105 106
106static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0, 107static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
107 DEVICE_RESET__BANK1, 108 DEVICE_RESET__BANK1,
108 DEVICE_RESET__BANK2, 109 DEVICE_RESET__BANK2,
109 DEVICE_RESET__BANK3}; 110 DEVICE_RESET__BANK3};
110 111
111static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT, 112static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
112 INTR_STATUS1__TIME_OUT, 113 INTR_STATUS1__TIME_OUT,
113 INTR_STATUS2__TIME_OUT, 114 INTR_STATUS2__TIME_OUT,
114 INTR_STATUS3__TIME_OUT}; 115 INTR_STATUS3__TIME_OUT};
115 116
116static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, 117static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
117 INTR_STATUS1__RST_COMP, 118 INTR_STATUS1__RST_COMP,
118 INTR_STATUS2__RST_COMP, 119 INTR_STATUS2__RST_COMP,
119 INTR_STATUS3__RST_COMP}; 120 INTR_STATUS3__RST_COMP};
120 121
121/* specifies the debug level of the driver */ 122/* specifies the debug level of the driver */
122static int nand_debug_level = 0; 123static int nand_debug_level;
123 124
124/* forward declarations */ 125/* forward declarations */
125static void clear_interrupts(struct denali_nand_info *denali); 126static void clear_interrupts(struct denali_nand_info *denali);
126static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask); 127static uint32_t wait_for_irq(struct denali_nand_info *denali,
127static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask); 128 uint32_t irq_mask);
129static void denali_irq_enable(struct denali_nand_info *denali,
130 uint32_t int_mask);
128static uint32_t read_interrupt_status(struct denali_nand_info *denali); 131static uint32_t read_interrupt_status(struct denali_nand_info *denali);
129 132
130#define DEBUG_DENALI 0 133#define DEBUG_DENALI 0
131 134
132/* This is a wrapper for writing to the denali registers. 135/* This is a wrapper for writing to the denali registers.
133 * this allows us to create debug information so we can 136 * this allows us to create debug information so we can
134 * observe how the driver is programming the device. 137 * observe how the driver is programming the device.
135 * it uses standard linux convention for (val, addr) */ 138 * it uses standard linux convention for (val, addr) */
136static void denali_write32(uint32_t value, void *addr) 139static void denali_write32(uint32_t value, void *addr)
137{ 140{
138 iowrite32(value, addr); 141 iowrite32(value, addr);
139 142
140#if DEBUG_DENALI 143#if DEBUG_DENALI
141 printk(KERN_ERR "wrote: 0x%x -> 0x%x\n", value, (uint32_t)((uint32_t)addr & 0x1fff)); 144 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
145 (uint32_t)((uint32_t)addr & 0x1fff));
142#endif 146#endif
143} 147}
144 148
145/* Certain operations for the denali NAND controller use an indexed mode to read/write 149/* Certain operations for the denali NAND controller use
146 data. The operation is performed by writing the address value of the command to 150 * an indexed mode to read/write data. The operation is
147 the device memory followed by the data. This function abstracts this common 151 * performed by writing the address value of the command
148 operation. 152 * to the device memory followed by the data. This function
153 * abstracts this common operation.
149*/ 154*/
150static void index_addr(struct denali_nand_info *denali, uint32_t address, uint32_t data) 155static void index_addr(struct denali_nand_info *denali,
156 uint32_t address, uint32_t data)
151{ 157{
152 denali_write32(address, denali->flash_mem); 158 denali_write32(address, denali->flash_mem);
153 denali_write32(data, denali->flash_mem + 0x10); 159 denali_write32(data, denali->flash_mem + 0x10);
@@ -161,7 +167,7 @@ static void index_addr_read_data(struct denali_nand_info *denali,
161 *pdata = ioread32(denali->flash_mem + 0x10); 167 *pdata = ioread32(denali->flash_mem + 0x10);
162} 168}
163 169
164/* We need to buffer some data for some of the NAND core routines. 170/* We need to buffer some data for some of the NAND core routines.
165 * The operations manage buffering that data. */ 171 * The operations manage buffering that data. */
166static void reset_buf(struct denali_nand_info *denali) 172static void reset_buf(struct denali_nand_info *denali)
167{ 173{
@@ -183,7 +189,7 @@ static void read_status(struct denali_nand_info *denali)
183 reset_buf(denali); 189 reset_buf(denali);
184 190
185 /* initiate a device status read */ 191 /* initiate a device status read */
186 cmd = MODE_11 | BANK(denali->flash_bank); 192 cmd = MODE_11 | BANK(denali->flash_bank);
187 index_addr(denali, cmd | COMMAND_CYCLE, 0x70); 193 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
188 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem); 194 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
189 195
@@ -191,7 +197,8 @@ static void read_status(struct denali_nand_info *denali)
191 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); 197 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
192 198
193#if DEBUG_DENALI 199#if DEBUG_DENALI
194 printk("device reporting status value of 0x%2x\n", denali->buf.buf[0]); 200 printk(KERN_INFO "device reporting status value of 0x%2x\n",
201 denali->buf.buf[0]);
195#endif 202#endif
196} 203}
197 204
@@ -199,7 +206,7 @@ static void read_status(struct denali_nand_info *denali)
199static void reset_bank(struct denali_nand_info *denali) 206static void reset_bank(struct denali_nand_info *denali)
200{ 207{
201 uint32_t irq_status = 0; 208 uint32_t irq_status = 0;
202 uint32_t irq_mask = reset_complete[denali->flash_bank] | 209 uint32_t irq_mask = reset_complete[denali->flash_bank] |
203 operation_timeout[denali->flash_bank]; 210 operation_timeout[denali->flash_bank];
204 int bank = 0; 211 int bank = 0;
205 212
@@ -209,15 +216,13 @@ static void reset_bank(struct denali_nand_info *denali)
209 denali_write32(bank, denali->flash_reg + DEVICE_RESET); 216 denali_write32(bank, denali->flash_reg + DEVICE_RESET);
210 217
211 irq_status = wait_for_irq(denali, irq_mask); 218 irq_status = wait_for_irq(denali, irq_mask);
212 219
213 if (irq_status & operation_timeout[denali->flash_bank]) 220 if (irq_status & operation_timeout[denali->flash_bank])
214 {
215 printk(KERN_ERR "reset bank failed.\n"); 221 printk(KERN_ERR "reset bank failed.\n");
216 }
217} 222}
218 223
219/* Reset the flash controller */ 224/* Reset the flash controller */
220static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali) 225static uint16_t denali_nand_reset(struct denali_nand_info *denali)
221{ 226{
222 uint32_t i; 227 uint32_t i;
223 228
@@ -229,8 +234,10 @@ static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali)
229 denali->flash_reg + intr_status_addresses[i]); 234 denali->flash_reg + intr_status_addresses[i]);
230 235
231 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { 236 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
232 denali_write32(device_reset_banks[i], denali->flash_reg + DEVICE_RESET); 237 denali_write32(device_reset_banks[i],
233 while (!(ioread32(denali->flash_reg + intr_status_addresses[i]) & 238 denali->flash_reg + DEVICE_RESET);
239 while (!(ioread32(denali->flash_reg +
240 intr_status_addresses[i]) &
234 (reset_complete[i] | operation_timeout[i]))) 241 (reset_complete[i] | operation_timeout[i])))
235 ; 242 ;
236 if (ioread32(denali->flash_reg + intr_status_addresses[i]) & 243 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
@@ -246,11 +253,12 @@ static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali)
246 return PASS; 253 return PASS;
247} 254}
248 255
249/* this routine calculates the ONFI timing values for a given mode and programs 256/* this routine calculates the ONFI timing values for a given mode and
250 * the clocking register accordingly. The mode is determined by the get_onfi_nand_para 257 * programs the clocking register accordingly. The mode is determined by
251 routine. 258 * the get_onfi_nand_para routine.
252 */ 259 */
253static void NAND_ONFi_Timing_Mode(struct denali_nand_info *denali, uint16_t mode) 260static void nand_onfi_timing_set(struct denali_nand_info *denali,
261 uint16_t mode)
254{ 262{
255 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; 263 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
256 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; 264 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
@@ -347,136 +355,24 @@ static void NAND_ONFi_Timing_Mode(struct denali_nand_info *denali, uint16_t mode
347 denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); 355 denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
348} 356}
349 357
350/* configures the initial ECC settings for the controller */
351static void set_ecc_config(struct denali_nand_info *denali)
352{
353#if SUPPORT_8BITECC
354 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
355 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
356 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
357#endif
358
359 if ((ioread32(denali->flash_reg + ECC_CORRECTION) & ECC_CORRECTION__VALUE)
360 == 1) {
361 denali->dev_info.wECCBytesPerSector = 4;
362 denali->dev_info.wECCBytesPerSector *= denali->dev_info.wDevicesConnected;
363 denali->dev_info.wNumPageSpareFlag =
364 denali->dev_info.wPageSpareSize -
365 denali->dev_info.wPageDataSize /
366 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
367 denali->dev_info.wECCBytesPerSector
368 - denali->dev_info.wSpareSkipBytes;
369 } else {
370 denali->dev_info.wECCBytesPerSector =
371 (ioread32(denali->flash_reg + ECC_CORRECTION) &
372 ECC_CORRECTION__VALUE) * 13 / 8;
373 if ((denali->dev_info.wECCBytesPerSector) % 2 == 0)
374 denali->dev_info.wECCBytesPerSector += 2;
375 else
376 denali->dev_info.wECCBytesPerSector += 1;
377
378 denali->dev_info.wECCBytesPerSector *= denali->dev_info.wDevicesConnected;
379 denali->dev_info.wNumPageSpareFlag = denali->dev_info.wPageSpareSize -
380 denali->dev_info.wPageDataSize /
381 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
382 denali->dev_info.wECCBytesPerSector
383 - denali->dev_info.wSpareSkipBytes;
384 }
385}
386
387/* queries the NAND device to see what ONFI modes it supports. */ 358/* queries the NAND device to see what ONFI modes it supports. */
388static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) 359static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
389{ 360{
390 int i; 361 int i;
391 uint16_t blks_lun_l, blks_lun_h, n_of_luns; 362 /* we needn't to do a reset here because driver has already
392 uint32_t blockperlun, id; 363 * reset all the banks before
393 364 * */
394 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
395
396 while (!((ioread32(denali->flash_reg + INTR_STATUS0) &
397 INTR_STATUS0__RST_COMP) |
398 (ioread32(denali->flash_reg + INTR_STATUS0) &
399 INTR_STATUS0__TIME_OUT)))
400 ;
401
402 if (ioread32(denali->flash_reg + INTR_STATUS0) & INTR_STATUS0__RST_COMP) {
403 denali_write32(DEVICE_RESET__BANK1, denali->flash_reg + DEVICE_RESET);
404 while (!((ioread32(denali->flash_reg + INTR_STATUS1) &
405 INTR_STATUS1__RST_COMP) |
406 (ioread32(denali->flash_reg + INTR_STATUS1) &
407 INTR_STATUS1__TIME_OUT)))
408 ;
409
410 if (ioread32(denali->flash_reg + INTR_STATUS1) &
411 INTR_STATUS1__RST_COMP) {
412 denali_write32(DEVICE_RESET__BANK2,
413 denali->flash_reg + DEVICE_RESET);
414 while (!((ioread32(denali->flash_reg + INTR_STATUS2) &
415 INTR_STATUS2__RST_COMP) |
416 (ioread32(denali->flash_reg + INTR_STATUS2) &
417 INTR_STATUS2__TIME_OUT)))
418 ;
419
420 if (ioread32(denali->flash_reg + INTR_STATUS2) &
421 INTR_STATUS2__RST_COMP) {
422 denali_write32(DEVICE_RESET__BANK3,
423 denali->flash_reg + DEVICE_RESET);
424 while (!((ioread32(denali->flash_reg + INTR_STATUS3) &
425 INTR_STATUS3__RST_COMP) |
426 (ioread32(denali->flash_reg + INTR_STATUS3) &
427 INTR_STATUS3__TIME_OUT)))
428 ;
429 } else {
430 printk(KERN_ERR "Getting a time out for bank 2!\n");
431 }
432 } else {
433 printk(KERN_ERR "Getting a time out for bank 1!\n");
434 }
435 }
436
437 denali_write32(INTR_STATUS0__TIME_OUT, denali->flash_reg + INTR_STATUS0);
438 denali_write32(INTR_STATUS1__TIME_OUT, denali->flash_reg + INTR_STATUS1);
439 denali_write32(INTR_STATUS2__TIME_OUT, denali->flash_reg + INTR_STATUS2);
440 denali_write32(INTR_STATUS3__TIME_OUT, denali->flash_reg + INTR_STATUS3);
441
442 denali->dev_info.wONFIDevFeatures =
443 ioread32(denali->flash_reg + ONFI_DEVICE_FEATURES);
444 denali->dev_info.wONFIOptCommands =
445 ioread32(denali->flash_reg + ONFI_OPTIONAL_COMMANDS);
446 denali->dev_info.wONFITimingMode =
447 ioread32(denali->flash_reg + ONFI_TIMING_MODE);
448 denali->dev_info.wONFIPgmCacheTimingMode =
449 ioread32(denali->flash_reg + ONFI_PGM_CACHE_TIMING_MODE);
450
451 n_of_luns = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
452 ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS;
453 blks_lun_l = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L);
454 blks_lun_h = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U);
455
456 blockperlun = (blks_lun_h << 16) | blks_lun_l;
457
458 denali->dev_info.wTotalBlocks = n_of_luns * blockperlun;
459
460 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & 365 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
461 ONFI_TIMING_MODE__VALUE)) 366 ONFI_TIMING_MODE__VALUE))
462 return FAIL; 367 return FAIL;
463 368
464 for (i = 5; i > 0; i--) { 369 for (i = 5; i > 0; i--) {
465 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & (0x01 << i)) 370 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
371 (0x01 << i))
466 break; 372 break;
467 } 373 }
468 374
469 NAND_ONFi_Timing_Mode(denali, i); 375 nand_onfi_timing_set(denali, i);
470
471 index_addr(denali, MODE_11 | 0, 0x90);
472 index_addr(denali, MODE_11 | 1, 0);
473
474 for (i = 0; i < 3; i++)
475 index_addr_read_data(denali, MODE_11 | 2, &id);
476
477 nand_dbg_print(NAND_DBG_DEBUG, "3rd ID: 0x%x\n", id);
478
479 denali->dev_info.MLCDevice = id & 0x0C;
480 376
481 /* By now, all the ONFI devices we know support the page cache */ 377 /* By now, all the ONFI devices we know support the page cache */
482 /* rw feature. So here we enable the pipeline_rw_ahead feature */ 378 /* rw feature. So here we enable the pipeline_rw_ahead feature */
@@ -486,25 +382,10 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
486 return PASS; 382 return PASS;
487} 383}
488 384
489static void get_samsung_nand_para(struct denali_nand_info *denali) 385static void get_samsung_nand_para(struct denali_nand_info *denali,
386 uint8_t device_id)
490{ 387{
491 uint8_t no_of_planes; 388 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
492 uint32_t blk_size;
493 uint64_t plane_size, capacity;
494 uint32_t id_bytes[5];
495 int i;
496
497 index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90);
498 index_addr(denali, (uint32_t)(MODE_11 | 1), 0);
499 for (i = 0; i < 5; i++)
500 index_addr_read_data(denali, (uint32_t)(MODE_11 | 2), &id_bytes[i]);
501
502 nand_dbg_print(NAND_DBG_DEBUG,
503 "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
504 id_bytes[0], id_bytes[1], id_bytes[2],
505 id_bytes[3], id_bytes[4]);
506
507 if ((id_bytes[1] & 0xff) == 0xd3) { /* Samsung K9WAG08U1A */
508 /* Set timing register values according to datasheet */ 389 /* Set timing register values according to datasheet */
509 denali_write32(5, denali->flash_reg + ACC_CLKS); 390 denali_write32(5, denali->flash_reg + ACC_CLKS);
510 denali_write32(20, denali->flash_reg + RE_2_WE); 391 denali_write32(20, denali->flash_reg + RE_2_WE);
@@ -514,19 +395,10 @@ static void get_samsung_nand_para(struct denali_nand_info *denali)
514 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT); 395 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
515 denali_write32(2, denali->flash_reg + CS_SETUP_CNT); 396 denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
516 } 397 }
517
518 no_of_planes = 1 << ((id_bytes[4] & 0x0c) >> 2);
519 plane_size = (uint64_t)64 << ((id_bytes[4] & 0x70) >> 4);
520 blk_size = 64 << ((ioread32(denali->flash_reg + DEVICE_PARAM_1) & 0x30) >> 4);
521 capacity = (uint64_t)128 * plane_size * no_of_planes;
522
523 do_div(capacity, blk_size);
524 denali->dev_info.wTotalBlocks = capacity;
525} 398}
526 399
527static void get_toshiba_nand_para(struct denali_nand_info *denali) 400static void get_toshiba_nand_para(struct denali_nand_info *denali)
528{ 401{
529 void __iomem *scratch_reg;
530 uint32_t tmp; 402 uint32_t tmp;
531 403
532 /* Workaround to fix a controller bug which reports a wrong */ 404 /* Workaround to fix a controller bug which reports a wrong */
@@ -536,81 +408,52 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali)
536 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 408 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
537 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * 409 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
538 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 410 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
539 denali_write32(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); 411 denali_write32(tmp,
412 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
540#if SUPPORT_15BITECC 413#if SUPPORT_15BITECC
541 denali_write32(15, denali->flash_reg + ECC_CORRECTION); 414 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
542#elif SUPPORT_8BITECC 415#elif SUPPORT_8BITECC
543 denali_write32(8, denali->flash_reg + ECC_CORRECTION); 416 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
544#endif 417#endif
545 } 418 }
546
547 /* As Toshiba NAND can not provide it's block number, */
548 /* so here we need user to provide the correct block */
549 /* number in a scratch register before the Linux NAND */
550 /* driver is loaded. If no valid value found in the scratch */
551 /* register, then we use default block number value */
552 scratch_reg = ioremap_nocache(SCRATCH_REG_ADDR, SCRATCH_REG_SIZE);
553 if (!scratch_reg) {
554 printk(KERN_ERR "Spectra: ioremap failed in %s, Line %d",
555 __FILE__, __LINE__);
556 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
557 } else {
558 nand_dbg_print(NAND_DBG_WARN,
559 "Spectra: ioremap reg address: 0x%p\n", scratch_reg);
560 denali->dev_info.wTotalBlocks = 1 << ioread8(scratch_reg);
561 if (denali->dev_info.wTotalBlocks < 512)
562 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
563 iounmap(scratch_reg);
564 }
565} 419}
566 420
567static void get_hynix_nand_para(struct denali_nand_info *denali) 421static void get_hynix_nand_para(struct denali_nand_info *denali,
422 uint8_t device_id)
568{ 423{
569 void __iomem *scratch_reg;
570 uint32_t main_size, spare_size; 424 uint32_t main_size, spare_size;
571 425
572 switch (denali->dev_info.wDeviceID) { 426 switch (device_id) {
573 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ 427 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
574 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ 428 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
575 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK); 429 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
576 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); 430 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
577 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 431 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
578 main_size = 4096 * ioread32(denali->flash_reg + DEVICES_CONNECTED); 432 main_size = 4096 *
579 spare_size = 224 * ioread32(denali->flash_reg + DEVICES_CONNECTED); 433 ioread32(denali->flash_reg + DEVICES_CONNECTED);
580 denali_write32(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); 434 spare_size = 224 *
581 denali_write32(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); 435 ioread32(denali->flash_reg + DEVICES_CONNECTED);
436 denali_write32(main_size,
437 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
438 denali_write32(spare_size,
439 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
582 denali_write32(0, denali->flash_reg + DEVICE_WIDTH); 440 denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
583#if SUPPORT_15BITECC 441#if SUPPORT_15BITECC
584 denali_write32(15, denali->flash_reg + ECC_CORRECTION); 442 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
585#elif SUPPORT_8BITECC 443#elif SUPPORT_8BITECC
586 denali_write32(8, denali->flash_reg + ECC_CORRECTION); 444 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
587#endif 445#endif
588 denali->dev_info.MLCDevice = 1;
589 break; 446 break;
590 default: 447 default:
591 nand_dbg_print(NAND_DBG_WARN, 448 nand_dbg_print(NAND_DBG_WARN,
592 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." 449 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
593 "Will use default parameter values instead.\n", 450 "Will use default parameter values instead.\n",
594 denali->dev_info.wDeviceID); 451 device_id);
595 }
596
597 scratch_reg = ioremap_nocache(SCRATCH_REG_ADDR, SCRATCH_REG_SIZE);
598 if (!scratch_reg) {
599 printk(KERN_ERR "Spectra: ioremap failed in %s, Line %d",
600 __FILE__, __LINE__);
601 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
602 } else {
603 nand_dbg_print(NAND_DBG_WARN,
604 "Spectra: ioremap reg address: 0x%p\n", scratch_reg);
605 denali->dev_info.wTotalBlocks = 1 << ioread8(scratch_reg);
606 if (denali->dev_info.wTotalBlocks < 512)
607 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
608 iounmap(scratch_reg);
609 } 452 }
610} 453}
611 454
612/* determines how many NAND chips are connected to the controller. Note for 455/* determines how many NAND chips are connected to the controller. Note for
613 Intel CE4100 devices we don't support more than one device. 456 Intel CE4100 devices we don't support more than one device.
614 */ 457 */
615static void find_valid_banks(struct denali_nand_info *denali) 458static void find_valid_banks(struct denali_nand_info *denali)
616{ 459{
@@ -621,7 +464,8 @@ static void find_valid_banks(struct denali_nand_info *denali)
621 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { 464 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
622 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); 465 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
623 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); 466 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
624 index_addr_read_data(denali, (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); 467 index_addr_read_data(denali,
468 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
625 469
626 nand_dbg_print(NAND_DBG_DEBUG, 470 nand_dbg_print(NAND_DBG_DEBUG,
627 "Return 1st ID for bank[%d]: %x\n", i, id[i]); 471 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
@@ -637,14 +481,12 @@ static void find_valid_banks(struct denali_nand_info *denali)
637 } 481 }
638 } 482 }
639 483
640 if (denali->platform == INTEL_CE4100) 484 if (denali->platform == INTEL_CE4100) {
641 {
642 /* Platform limitations of the CE4100 device limit 485 /* Platform limitations of the CE4100 device limit
643 * users to a single chip solution for NAND. 486 * users to a single chip solution for NAND.
644 * Multichip support is not enabled. 487 * Multichip support is not enabled.
645 */ 488 */
646 if (denali->total_used_banks != 1) 489 if (denali->total_used_banks != 1) {
647 {
648 printk(KERN_ERR "Sorry, Intel CE4100 only supports " 490 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
649 "a single NAND device.\n"); 491 "a single NAND device.\n");
650 BUG(); 492 BUG();
@@ -656,150 +498,60 @@ static void find_valid_banks(struct denali_nand_info *denali)
656 498
657static void detect_partition_feature(struct denali_nand_info *denali) 499static void detect_partition_feature(struct denali_nand_info *denali)
658{ 500{
501 /* For MRST platform, denali->fwblks represent the
502 * number of blocks firmware is taken,
503 * FW is in protect partition and MTD driver has no
504 * permission to access it. So let driver know how many
505 * blocks it can't touch.
506 * */
659 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { 507 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
660 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & 508 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
661 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { 509 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
662 denali->dev_info.wSpectraStartBlock = 510 denali->fwblks =
663 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 511 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
664 MIN_MAX_BANK_1__MIN_VALUE) * 512 MIN_MAX_BANK_1__MIN_VALUE) *
665 denali->dev_info.wTotalBlocks) 513 denali->blksperchip)
666 + 514 +
667 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & 515 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
668 MIN_BLK_ADDR_1__VALUE); 516 MIN_BLK_ADDR_1__VALUE);
669 517 } else
670 denali->dev_info.wSpectraEndBlock = 518 denali->fwblks = SPECTRA_START_BLOCK;
671 (((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 519 } else
672 MIN_MAX_BANK_1__MAX_VALUE) >> 2) * 520 denali->fwblks = SPECTRA_START_BLOCK;
673 denali->dev_info.wTotalBlocks)
674 +
675 (ioread32(denali->flash_reg + MAX_BLK_ADDR_1) &
676 MAX_BLK_ADDR_1__VALUE);
677
678 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
679
680 if (denali->dev_info.wSpectraEndBlock >=
681 denali->dev_info.wTotalBlocks) {
682 denali->dev_info.wSpectraEndBlock =
683 denali->dev_info.wTotalBlocks - 1;
684 }
685
686 denali->dev_info.wDataBlockNum =
687 denali->dev_info.wSpectraEndBlock -
688 denali->dev_info.wSpectraStartBlock + 1;
689 } else {
690 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
691 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK;
692 denali->dev_info.wSpectraEndBlock =
693 denali->dev_info.wTotalBlocks - 1;
694 denali->dev_info.wDataBlockNum =
695 denali->dev_info.wSpectraEndBlock -
696 denali->dev_info.wSpectraStartBlock + 1;
697 }
698 } else {
699 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
700 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK;
701 denali->dev_info.wSpectraEndBlock = denali->dev_info.wTotalBlocks - 1;
702 denali->dev_info.wDataBlockNum =
703 denali->dev_info.wSpectraEndBlock -
704 denali->dev_info.wSpectraStartBlock + 1;
705 }
706} 521}
707 522
708static void dump_device_info(struct denali_nand_info *denali) 523static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
709{
710 nand_dbg_print(NAND_DBG_DEBUG, "denali->dev_info:\n");
711 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMaker: 0x%x\n",
712 denali->dev_info.wDeviceMaker);
713 nand_dbg_print(NAND_DBG_DEBUG, "DeviceID: 0x%x\n",
714 denali->dev_info.wDeviceID);
715 nand_dbg_print(NAND_DBG_DEBUG, "DeviceType: 0x%x\n",
716 denali->dev_info.wDeviceType);
717 nand_dbg_print(NAND_DBG_DEBUG, "SpectraStartBlock: %d\n",
718 denali->dev_info.wSpectraStartBlock);
719 nand_dbg_print(NAND_DBG_DEBUG, "SpectraEndBlock: %d\n",
720 denali->dev_info.wSpectraEndBlock);
721 nand_dbg_print(NAND_DBG_DEBUG, "TotalBlocks: %d\n",
722 denali->dev_info.wTotalBlocks);
723 nand_dbg_print(NAND_DBG_DEBUG, "PagesPerBlock: %d\n",
724 denali->dev_info.wPagesPerBlock);
725 nand_dbg_print(NAND_DBG_DEBUG, "PageSize: %d\n",
726 denali->dev_info.wPageSize);
727 nand_dbg_print(NAND_DBG_DEBUG, "PageDataSize: %d\n",
728 denali->dev_info.wPageDataSize);
729 nand_dbg_print(NAND_DBG_DEBUG, "PageSpareSize: %d\n",
730 denali->dev_info.wPageSpareSize);
731 nand_dbg_print(NAND_DBG_DEBUG, "NumPageSpareFlag: %d\n",
732 denali->dev_info.wNumPageSpareFlag);
733 nand_dbg_print(NAND_DBG_DEBUG, "ECCBytesPerSector: %d\n",
734 denali->dev_info.wECCBytesPerSector);
735 nand_dbg_print(NAND_DBG_DEBUG, "BlockSize: %d\n",
736 denali->dev_info.wBlockSize);
737 nand_dbg_print(NAND_DBG_DEBUG, "BlockDataSize: %d\n",
738 denali->dev_info.wBlockDataSize);
739 nand_dbg_print(NAND_DBG_DEBUG, "DataBlockNum: %d\n",
740 denali->dev_info.wDataBlockNum);
741 nand_dbg_print(NAND_DBG_DEBUG, "PlaneNum: %d\n",
742 denali->dev_info.bPlaneNum);
743 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMainAreaSize: %d\n",
744 denali->dev_info.wDeviceMainAreaSize);
745 nand_dbg_print(NAND_DBG_DEBUG, "DeviceSpareAreaSize: %d\n",
746 denali->dev_info.wDeviceSpareAreaSize);
747 nand_dbg_print(NAND_DBG_DEBUG, "DevicesConnected: %d\n",
748 denali->dev_info.wDevicesConnected);
749 nand_dbg_print(NAND_DBG_DEBUG, "DeviceWidth: %d\n",
750 denali->dev_info.wDeviceWidth);
751 nand_dbg_print(NAND_DBG_DEBUG, "HWRevision: 0x%x\n",
752 denali->dev_info.wHWRevision);
753 nand_dbg_print(NAND_DBG_DEBUG, "HWFeatures: 0x%x\n",
754 denali->dev_info.wHWFeatures);
755 nand_dbg_print(NAND_DBG_DEBUG, "ONFIDevFeatures: 0x%x\n",
756 denali->dev_info.wONFIDevFeatures);
757 nand_dbg_print(NAND_DBG_DEBUG, "ONFIOptCommands: 0x%x\n",
758 denali->dev_info.wONFIOptCommands);
759 nand_dbg_print(NAND_DBG_DEBUG, "ONFITimingMode: 0x%x\n",
760 denali->dev_info.wONFITimingMode);
761 nand_dbg_print(NAND_DBG_DEBUG, "ONFIPgmCacheTimingMode: 0x%x\n",
762 denali->dev_info.wONFIPgmCacheTimingMode);
763 nand_dbg_print(NAND_DBG_DEBUG, "MLCDevice: %s\n",
764 denali->dev_info.MLCDevice ? "Yes" : "No");
765 nand_dbg_print(NAND_DBG_DEBUG, "SpareSkipBytes: %d\n",
766 denali->dev_info.wSpareSkipBytes);
767 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageNumber: %d\n",
768 denali->dev_info.nBitsInPageNumber);
769 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageDataSize: %d\n",
770 denali->dev_info.nBitsInPageDataSize);
771 nand_dbg_print(NAND_DBG_DEBUG, "BitsInBlockDataSize: %d\n",
772 denali->dev_info.nBitsInBlockDataSize);
773}
774
775static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
776{ 524{
777 uint16_t status = PASS; 525 uint16_t status = PASS;
778 uint8_t no_of_planes; 526 uint32_t id_bytes[5], addr;
527 uint8_t i, maf_id, device_id;
779 528
780 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", 529 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
781 __FILE__, __LINE__, __func__); 530 __FILE__, __LINE__, __func__);
782 531
783 denali->dev_info.wDeviceMaker = ioread32(denali->flash_reg + MANUFACTURER_ID); 532 /* Use read id method to get device ID and other
784 denali->dev_info.wDeviceID = ioread32(denali->flash_reg + DEVICE_ID); 533 * params. For some NAND chips, controller can't
785 denali->dev_info.bDeviceParam0 = ioread32(denali->flash_reg + DEVICE_PARAM_0); 534 * report the correct device ID by reading from
786 denali->dev_info.bDeviceParam1 = ioread32(denali->flash_reg + DEVICE_PARAM_1); 535 * DEVICE_ID register
787 denali->dev_info.bDeviceParam2 = ioread32(denali->flash_reg + DEVICE_PARAM_2); 536 * */
788 537 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
789 denali->dev_info.MLCDevice = ioread32(denali->flash_reg + DEVICE_PARAM_0) & 0x0c; 538 index_addr(denali, (uint32_t)addr | 0, 0x90);
539 index_addr(denali, (uint32_t)addr | 1, 0);
540 for (i = 0; i < 5; i++)
541 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
542 maf_id = id_bytes[0];
543 device_id = id_bytes[1];
790 544
791 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & 545 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
792 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ 546 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
793 if (FAIL == get_onfi_nand_para(denali)) 547 if (FAIL == get_onfi_nand_para(denali))
794 return FAIL; 548 return FAIL;
795 } else if (denali->dev_info.wDeviceMaker == 0xEC) { /* Samsung NAND */ 549 } else if (maf_id == 0xEC) { /* Samsung NAND */
796 get_samsung_nand_para(denali); 550 get_samsung_nand_para(denali, device_id);
797 } else if (denali->dev_info.wDeviceMaker == 0x98) { /* Toshiba NAND */ 551 } else if (maf_id == 0x98) { /* Toshiba NAND */
798 get_toshiba_nand_para(denali); 552 get_toshiba_nand_para(denali);
799 } else if (denali->dev_info.wDeviceMaker == 0xAD) { /* Hynix NAND */ 553 } else if (maf_id == 0xAD) { /* Hynix NAND */
800 get_hynix_nand_para(denali); 554 get_hynix_nand_para(denali, device_id);
801 } else {
802 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
803 } 555 }
804 556
805 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" 557 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
@@ -814,88 +566,20 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
814 ioread32(denali->flash_reg + RDWR_EN_HI_CNT), 566 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
815 ioread32(denali->flash_reg + CS_SETUP_CNT)); 567 ioread32(denali->flash_reg + CS_SETUP_CNT));
816 568
817 denali->dev_info.wHWRevision = ioread32(denali->flash_reg + REVISION);
818 denali->dev_info.wHWFeatures = ioread32(denali->flash_reg + FEATURES);
819
820 denali->dev_info.wDeviceMainAreaSize =
821 ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
822 denali->dev_info.wDeviceSpareAreaSize =
823 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
824
825 denali->dev_info.wPageDataSize =
826 ioread32(denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
827
828 /* Note: When using the Micon 4K NAND device, the controller will report
829 * Page Spare Size as 216 bytes. But Micron's Spec say it's 218 bytes.
830 * And if force set it to 218 bytes, the controller can not work
831 * correctly. So just let it be. But keep in mind that this bug may
832 * cause
833 * other problems in future. - Yunpeng 2008-10-10
834 */
835 denali->dev_info.wPageSpareSize =
836 ioread32(denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
837
838 denali->dev_info.wPagesPerBlock = ioread32(denali->flash_reg + PAGES_PER_BLOCK);
839
840 denali->dev_info.wPageSize =
841 denali->dev_info.wPageDataSize + denali->dev_info.wPageSpareSize;
842 denali->dev_info.wBlockSize =
843 denali->dev_info.wPageSize * denali->dev_info.wPagesPerBlock;
844 denali->dev_info.wBlockDataSize =
845 denali->dev_info.wPagesPerBlock * denali->dev_info.wPageDataSize;
846
847 denali->dev_info.wDeviceWidth = ioread32(denali->flash_reg + DEVICE_WIDTH);
848 denali->dev_info.wDeviceType =
849 ((ioread32(denali->flash_reg + DEVICE_WIDTH) > 0) ? 16 : 8);
850
851 denali->dev_info.wDevicesConnected = ioread32(denali->flash_reg + DEVICES_CONNECTED);
852
853 denali->dev_info.wSpareSkipBytes =
854 ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES) *
855 denali->dev_info.wDevicesConnected;
856
857 denali->dev_info.nBitsInPageNumber =
858 ilog2(denali->dev_info.wPagesPerBlock);
859 denali->dev_info.nBitsInPageDataSize =
860 ilog2(denali->dev_info.wPageDataSize);
861 denali->dev_info.nBitsInBlockDataSize =
862 ilog2(denali->dev_info.wBlockDataSize);
863
864 set_ecc_config(denali);
865
866 no_of_planes = ioread32(denali->flash_reg + NUMBER_OF_PLANES) &
867 NUMBER_OF_PLANES__VALUE;
868
869 switch (no_of_planes) {
870 case 0:
871 case 1:
872 case 3:
873 case 7:
874 denali->dev_info.bPlaneNum = no_of_planes + 1;
875 break;
876 default:
877 status = FAIL;
878 break;
879 }
880
881 find_valid_banks(denali); 569 find_valid_banks(denali);
882 570
883 detect_partition_feature(denali); 571 detect_partition_feature(denali);
884 572
885 dump_device_info(denali);
886
887 /* If the user specified to override the default timings 573 /* If the user specified to override the default timings
888 * with a specific ONFI mode, we apply those changes here. 574 * with a specific ONFI mode, we apply those changes here.
889 */ 575 */
890 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) 576 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
891 { 577 nand_onfi_timing_set(denali, onfi_timing_mode);
892 NAND_ONFi_Timing_Mode(denali, onfi_timing_mode);
893 }
894 578
895 return status; 579 return status;
896} 580}
897 581
898static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali, 582static void denali_set_intr_modes(struct denali_nand_info *denali,
899 uint16_t INT_ENABLE) 583 uint16_t INT_ENABLE)
900{ 584{
901 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", 585 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
@@ -912,7 +596,7 @@ static void NAND_LLD_Enable_Disable_Interrupts(struct denali_nand_info *denali,
912 */ 596 */
913static inline bool is_flash_bank_valid(int flash_bank) 597static inline bool is_flash_bank_valid(int flash_bank)
914{ 598{
915 return (flash_bank >= 0 && flash_bank < 4); 599 return (flash_bank >= 0 && flash_bank < 4);
916} 600}
917 601
918static void denali_irq_init(struct denali_nand_info *denali) 602static void denali_irq_init(struct denali_nand_info *denali)
@@ -920,7 +604,7 @@ static void denali_irq_init(struct denali_nand_info *denali)
920 uint32_t int_mask = 0; 604 uint32_t int_mask = 0;
921 605
922 /* Disable global interrupts */ 606 /* Disable global interrupts */
923 NAND_LLD_Enable_Disable_Interrupts(denali, false); 607 denali_set_intr_modes(denali, false);
924 608
925 int_mask = DENALI_IRQ_ALL; 609 int_mask = DENALI_IRQ_ALL;
926 610
@@ -935,11 +619,12 @@ static void denali_irq_init(struct denali_nand_info *denali)
935 619
936static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) 620static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
937{ 621{
938 NAND_LLD_Enable_Disable_Interrupts(denali, false); 622 denali_set_intr_modes(denali, false);
939 free_irq(irqnum, denali); 623 free_irq(irqnum, denali);
940} 624}
941 625
942static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask) 626static void denali_irq_enable(struct denali_nand_info *denali,
627 uint32_t int_mask)
943{ 628{
944 denali_write32(int_mask, denali->flash_reg + INTR_EN0); 629 denali_write32(int_mask, denali->flash_reg + INTR_EN0);
945 denali_write32(int_mask, denali->flash_reg + INTR_EN1); 630 denali_write32(int_mask, denali->flash_reg + INTR_EN1);
@@ -948,15 +633,16 @@ static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask
948} 633}
949 634
950/* This function only returns when an interrupt that this driver cares about 635/* This function only returns when an interrupt that this driver cares about
951 * occurs. This is to reduce the overhead of servicing interrupts 636 * occurs. This is to reduce the overhead of servicing interrupts
952 */ 637 */
953static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) 638static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
954{ 639{
955 return (read_interrupt_status(denali) & DENALI_IRQ_ALL); 640 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
956} 641}
957 642
958/* Interrupts are cleared by writing a 1 to the appropriate status bit */ 643/* Interrupts are cleared by writing a 1 to the appropriate status bit */
959static inline void clear_interrupt(struct denali_nand_info *denali, uint32_t irq_mask) 644static inline void clear_interrupt(struct denali_nand_info *denali,
645 uint32_t irq_mask)
960{ 646{
961 uint32_t intr_status_reg = 0; 647 uint32_t intr_status_reg = 0;
962 648
@@ -995,17 +681,15 @@ static void print_irq_log(struct denali_nand_info *denali)
995{ 681{
996 int i = 0; 682 int i = 0;
997 683
998 printk("ISR debug log index = %X\n", denali->idx); 684 printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
999 for (i = 0; i < 32; i++) 685 for (i = 0; i < 32; i++)
1000 { 686 printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
1001 printk("%08X: %08X\n", i, denali->irq_debug_array[i]);
1002 }
1003} 687}
1004#endif 688#endif
1005 689
1006/* This is the interrupt service routine. It handles all interrupts 690/* This is the interrupt service routine. It handles all interrupts
1007 * sent to this device. Note that on CE4100, this is a shared 691 * sent to this device. Note that on CE4100, this is a shared
1008 * interrupt. 692 * interrupt.
1009 */ 693 */
1010static irqreturn_t denali_isr(int irq, void *dev_id) 694static irqreturn_t denali_isr(int irq, void *dev_id)
1011{ 695{
@@ -1015,20 +699,20 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
1015 699
1016 spin_lock(&denali->irq_lock); 700 spin_lock(&denali->irq_lock);
1017 701
1018 /* check to see if a valid NAND chip has 702 /* check to see if a valid NAND chip has
1019 * been selected. 703 * been selected.
1020 */ 704 */
1021 if (is_flash_bank_valid(denali->flash_bank)) 705 if (is_flash_bank_valid(denali->flash_bank)) {
1022 { 706 /* check to see if controller generated
1023 /* check to see if controller generated
1024 * the interrupt, since this is a shared interrupt */ 707 * the interrupt, since this is a shared interrupt */
1025 if ((irq_status = denali_irq_detected(denali)) != 0) 708 irq_status = denali_irq_detected(denali);
1026 { 709 if (irq_status != 0) {
1027#if DEBUG_DENALI 710#if DEBUG_DENALI
1028 denali->irq_debug_array[denali->idx++] = 0x10000000 | irq_status; 711 denali->irq_debug_array[denali->idx++] =
712 0x10000000 | irq_status;
1029 denali->idx %= 32; 713 denali->idx %= 32;
1030 714
1031 printk("IRQ status = 0x%04x\n", irq_status); 715 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
1032#endif 716#endif
1033 /* handle interrupt */ 717 /* handle interrupt */
1034 /* first acknowledge it */ 718 /* first acknowledge it */
@@ -1054,61 +738,62 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1054 bool retry = false; 738 bool retry = false;
1055 unsigned long timeout = msecs_to_jiffies(1000); 739 unsigned long timeout = msecs_to_jiffies(1000);
1056 740
1057 do 741 do {
1058 {
1059#if DEBUG_DENALI 742#if DEBUG_DENALI
1060 printk("waiting for 0x%x\n", irq_mask); 743 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
1061#endif 744#endif
1062 comp_res = wait_for_completion_timeout(&denali->complete, timeout); 745 comp_res =
746 wait_for_completion_timeout(&denali->complete, timeout);
1063 spin_lock_irq(&denali->irq_lock); 747 spin_lock_irq(&denali->irq_lock);
1064 intr_status = denali->irq_status; 748 intr_status = denali->irq_status;
1065 749
1066#if DEBUG_DENALI 750#if DEBUG_DENALI
1067 denali->irq_debug_array[denali->idx++] = 0x20000000 | (irq_mask << 16) | intr_status; 751 denali->irq_debug_array[denali->idx++] =
752 0x20000000 | (irq_mask << 16) | intr_status;
1068 denali->idx %= 32; 753 denali->idx %= 32;
1069#endif 754#endif
1070 755
1071 if (intr_status & irq_mask) 756 if (intr_status & irq_mask) {
1072 {
1073 denali->irq_status &= ~irq_mask; 757 denali->irq_status &= ~irq_mask;
1074 spin_unlock_irq(&denali->irq_lock); 758 spin_unlock_irq(&denali->irq_lock);
1075#if DEBUG_DENALI 759#if DEBUG_DENALI
1076 if (retry) printk("status on retry = 0x%x\n", intr_status); 760 if (retry)
761 printk(KERN_INFO "status on retry = 0x%x\n",
762 intr_status);
1077#endif 763#endif
1078 /* our interrupt was detected */ 764 /* our interrupt was detected */
1079 break; 765 break;
1080 } 766 } else {
1081 else 767 /* these are not the interrupts you are looking for -
1082 { 768 * need to wait again */
1083 /* these are not the interrupts you are looking for -
1084 need to wait again */
1085 spin_unlock_irq(&denali->irq_lock); 769 spin_unlock_irq(&denali->irq_lock);
1086#if DEBUG_DENALI 770#if DEBUG_DENALI
1087 print_irq_log(denali); 771 print_irq_log(denali);
1088 printk("received irq nobody cared: irq_status = 0x%x," 772 printk(KERN_INFO "received irq nobody cared:"
1089 " irq_mask = 0x%x, timeout = %ld\n", intr_status, irq_mask, comp_res); 773 " irq_status = 0x%x, irq_mask = 0x%x,"
774 " timeout = %ld\n", intr_status,
775 irq_mask, comp_res);
1090#endif 776#endif
1091 retry = true; 777 retry = true;
1092 } 778 }
1093 } while (comp_res != 0); 779 } while (comp_res != 0);
1094 780
1095 if (comp_res == 0) 781 if (comp_res == 0) {
1096 {
1097 /* timeout */ 782 /* timeout */
1098 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n", 783 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
1099 intr_status, irq_mask); 784 intr_status, irq_mask);
1100 785
1101 intr_status = 0; 786 intr_status = 0;
1102 } 787 }
1103 return intr_status; 788 return intr_status;
1104} 789}
1105 790
1106/* This helper function setups the registers for ECC and whether or not 791/* This helper function setups the registers for ECC and whether or not
1107 the spare area will be transfered. */ 792 the spare area will be transfered. */
1108static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, 793static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
1109 bool transfer_spare) 794 bool transfer_spare)
1110{ 795{
1111 int ecc_en_flag = 0, transfer_spare_flag = 0; 796 int ecc_en_flag = 0, transfer_spare_flag = 0;
1112 797
1113 /* set ECC, transfer spare bits if needed */ 798 /* set ECC, transfer spare bits if needed */
1114 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; 799 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
@@ -1116,85 +801,85 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
1116 801
1117 /* Enable spare area/ECC per user's request. */ 802 /* Enable spare area/ECC per user's request. */
1118 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); 803 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
1119 denali_write32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); 804 denali_write32(transfer_spare_flag,
805 denali->flash_reg + TRANSFER_SPARE_REG);
1120} 806}
1121 807
1122/* sends a pipeline command operation to the controller. See the Denali NAND 808/* sends a pipeline command operation to the controller. See the Denali NAND
1123 controller's user guide for more information (section 4.2.3.6). 809 controller's user guide for more information (section 4.2.3.6).
1124 */ 810 */
1125static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, 811static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
1126 bool transfer_spare, int access_type, 812 bool ecc_en,
1127 int op) 813 bool transfer_spare,
814 int access_type,
815 int op)
1128{ 816{
1129 int status = PASS; 817 int status = PASS;
1130 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, 818 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
1131 irq_mask = 0; 819 irq_mask = 0;
1132 820
1133 if (op == DENALI_READ) irq_mask = INTR_STATUS0__LOAD_COMP; 821 if (op == DENALI_READ)
1134 else if (op == DENALI_WRITE) irq_mask = 0; 822 irq_mask = INTR_STATUS0__LOAD_COMP;
1135 else BUG(); 823 else if (op == DENALI_WRITE)
824 irq_mask = 0;
825 else
826 BUG();
1136 827
1137 setup_ecc_for_xfer(denali, ecc_en, transfer_spare); 828 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
1138 829
1139#if DEBUG_DENALI 830#if DEBUG_DENALI
1140 spin_lock_irq(&denali->irq_lock); 831 spin_lock_irq(&denali->irq_lock);
1141 denali->irq_debug_array[denali->idx++] = 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) | (access_type << 4); 832 denali->irq_debug_array[denali->idx++] =
833 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
834 (access_type << 4);
1142 denali->idx %= 32; 835 denali->idx %= 32;
1143 spin_unlock_irq(&denali->irq_lock); 836 spin_unlock_irq(&denali->irq_lock);
1144#endif 837#endif
1145 838
1146 839
1147 /* clear interrupts */ 840 /* clear interrupts */
1148 clear_interrupts(denali); 841 clear_interrupts(denali);
1149 842
1150 addr = BANK(denali->flash_bank) | denali->page; 843 addr = BANK(denali->flash_bank) | denali->page;
1151 844
1152 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) 845 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
1153 { 846 cmd = MODE_01 | addr;
1154 cmd = MODE_01 | addr;
1155 denali_write32(cmd, denali->flash_mem); 847 denali_write32(cmd, denali->flash_mem);
1156 } 848 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
1157 else if (op == DENALI_WRITE && access_type == SPARE_ACCESS)
1158 {
1159 /* read spare area */ 849 /* read spare area */
1160 cmd = MODE_10 | addr; 850 cmd = MODE_10 | addr;
1161 index_addr(denali, (uint32_t)cmd, access_type); 851 index_addr(denali, (uint32_t)cmd, access_type);
1162 852
1163 cmd = MODE_01 | addr; 853 cmd = MODE_01 | addr;
1164 denali_write32(cmd, denali->flash_mem); 854 denali_write32(cmd, denali->flash_mem);
1165 } 855 } else if (op == DENALI_READ) {
1166 else if (op == DENALI_READ)
1167 {
1168 /* setup page read request for access type */ 856 /* setup page read request for access type */
1169 cmd = MODE_10 | addr; 857 cmd = MODE_10 | addr;
1170 index_addr(denali, (uint32_t)cmd, access_type); 858 index_addr(denali, (uint32_t)cmd, access_type);
1171 859
1172 /* page 33 of the NAND controller spec indicates we should not 860 /* page 33 of the NAND controller spec indicates we should not
1173 use the pipeline commands in Spare area only mode. So we 861 use the pipeline commands in Spare area only mode. So we
1174 don't. 862 don't.
1175 */ 863 */
1176 if (access_type == SPARE_ACCESS) 864 if (access_type == SPARE_ACCESS) {
1177 {
1178 cmd = MODE_01 | addr; 865 cmd = MODE_01 | addr;
1179 denali_write32(cmd, denali->flash_mem); 866 denali_write32(cmd, denali->flash_mem);
1180 } 867 } else {
1181 else 868 index_addr(denali, (uint32_t)cmd,
1182 { 869 0x2000 | op | page_count);
1183 index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count); 870
1184 871 /* wait for command to be accepted
1185 /* wait for command to be accepted 872 * can always use status0 bit as the
1186 * can always use status0 bit as the mask is identical for each 873 * mask is identical for each
1187 * bank. */ 874 * bank. */
1188 irq_status = wait_for_irq(denali, irq_mask); 875 irq_status = wait_for_irq(denali, irq_mask);
1189 876
1190 if (irq_status == 0) 877 if (irq_status == 0) {
1191 {
1192 printk(KERN_ERR "cmd, page, addr on timeout " 878 printk(KERN_ERR "cmd, page, addr on timeout "
1193 "(0x%x, 0x%x, 0x%x)\n", cmd, denali->page, addr); 879 "(0x%x, 0x%x, 0x%x)\n", cmd,
880 denali->page, addr);
1194 status = FAIL; 881 status = FAIL;
1195 } 882 } else {
1196 else
1197 {
1198 cmd = MODE_01 | addr; 883 cmd = MODE_01 | addr;
1199 denali_write32(cmd, denali->flash_mem); 884 denali_write32(cmd, denali->flash_mem);
1200 } 885 }
@@ -1204,36 +889,35 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1204} 889}
1205 890
1206/* helper function that simply writes a buffer to the flash */ 891/* helper function that simply writes a buffer to the flash */
1207static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_t *buf, 892static int write_data_to_flash_mem(struct denali_nand_info *denali,
1208 int len) 893 const uint8_t *buf,
894 int len)
1209{ 895{
1210 uint32_t i = 0, *buf32; 896 uint32_t i = 0, *buf32;
1211 897
1212 /* verify that the len is a multiple of 4. see comment in 898 /* verify that the len is a multiple of 4. see comment in
1213 * read_data_from_flash_mem() */ 899 * read_data_from_flash_mem() */
1214 BUG_ON((len % 4) != 0); 900 BUG_ON((len % 4) != 0);
1215 901
1216 /* write the data to the flash memory */ 902 /* write the data to the flash memory */
1217 buf32 = (uint32_t *)buf; 903 buf32 = (uint32_t *)buf;
1218 for (i = 0; i < len / 4; i++) 904 for (i = 0; i < len / 4; i++)
1219 {
1220 denali_write32(*buf32++, denali->flash_mem + 0x10); 905 denali_write32(*buf32++, denali->flash_mem + 0x10);
1221 } 906 return i*4; /* intent is to return the number of bytes read */
1222 return i*4; /* intent is to return the number of bytes read */
1223} 907}
1224 908
1225/* helper function that simply reads a buffer from the flash */ 909/* helper function that simply reads a buffer from the flash */
1226static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *buf, 910static int read_data_from_flash_mem(struct denali_nand_info *denali,
1227 int len) 911 uint8_t *buf,
912 int len)
1228{ 913{
1229 uint32_t i = 0, *buf32; 914 uint32_t i = 0, *buf32;
1230 915
1231 /* we assume that len will be a multiple of 4, if not 916 /* we assume that len will be a multiple of 4, if not
1232 * it would be nice to know about it ASAP rather than 917 * it would be nice to know about it ASAP rather than
1233 * have random failures... 918 * have random failures...
1234 * 919 * This assumption is based on the fact that this
1235 * This assumption is based on the fact that this 920 * function is designed to be used to read flash pages,
1236 * function is designed to be used to read flash pages,
1237 * which are typically multiples of 4... 921 * which are typically multiples of 4...
1238 */ 922 */
1239 923
@@ -1242,10 +926,8 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *bu
1242 /* transfer the data from the flash */ 926 /* transfer the data from the flash */
1243 buf32 = (uint32_t *)buf; 927 buf32 = (uint32_t *)buf;
1244 for (i = 0; i < len / 4; i++) 928 for (i = 0; i < len / 4; i++)
1245 {
1246 *buf32++ = ioread32(denali->flash_mem + 0x10); 929 *buf32++ = ioread32(denali->flash_mem + 0x10);
1247 } 930 return i*4; /* intent is to return the number of bytes read */
1248 return i*4; /* intent is to return the number of bytes read */
1249} 931}
1250 932
1251/* writes OOB data to the device */ 933/* writes OOB data to the device */
@@ -1253,38 +935,35 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1253{ 935{
1254 struct denali_nand_info *denali = mtd_to_denali(mtd); 936 struct denali_nand_info *denali = mtd_to_denali(mtd);
1255 uint32_t irq_status = 0; 937 uint32_t irq_status = 0;
1256 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | 938 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
1257 INTR_STATUS0__PROGRAM_FAIL; 939 INTR_STATUS0__PROGRAM_FAIL;
1258 int status = 0; 940 int status = 0;
1259 941
1260 denali->page = page; 942 denali->page = page;
1261 943
1262 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, 944 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
1263 DENALI_WRITE) == PASS) 945 DENALI_WRITE) == PASS) {
1264 {
1265 write_data_to_flash_mem(denali, buf, mtd->oobsize); 946 write_data_to_flash_mem(denali, buf, mtd->oobsize);
1266 947
1267#if DEBUG_DENALI 948#if DEBUG_DENALI
1268 spin_lock_irq(&denali->irq_lock); 949 spin_lock_irq(&denali->irq_lock);
1269 denali->irq_debug_array[denali->idx++] = 0x80000000 | mtd->oobsize; 950 denali->irq_debug_array[denali->idx++] =
951 0x80000000 | mtd->oobsize;
1270 denali->idx %= 32; 952 denali->idx %= 32;
1271 spin_unlock_irq(&denali->irq_lock); 953 spin_unlock_irq(&denali->irq_lock);
1272#endif 954#endif
1273 955
1274 956
1275 /* wait for operation to complete */ 957 /* wait for operation to complete */
1276 irq_status = wait_for_irq(denali, irq_mask); 958 irq_status = wait_for_irq(denali, irq_mask);
1277 959
1278 if (irq_status == 0) 960 if (irq_status == 0) {
1279 {
1280 printk(KERN_ERR "OOB write failed\n"); 961 printk(KERN_ERR "OOB write failed\n");
1281 status = -EIO; 962 status = -EIO;
1282 } 963 }
1283 } 964 } else {
1284 else
1285 {
1286 printk(KERN_ERR "unable to send pipeline command\n"); 965 printk(KERN_ERR "unable to send pipeline command\n");
1287 status = -EIO; 966 status = -EIO;
1288 } 967 }
1289 return status; 968 return status;
1290} 969}
@@ -1293,60 +972,56 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1293static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) 972static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1294{ 973{
1295 struct denali_nand_info *denali = mtd_to_denali(mtd); 974 struct denali_nand_info *denali = mtd_to_denali(mtd);
1296 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, irq_status = 0, addr = 0x0, cmd = 0x0; 975 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
976 irq_status = 0, addr = 0x0, cmd = 0x0;
1297 977
1298 denali->page = page; 978 denali->page = page;
1299 979
1300#if DEBUG_DENALI 980#if DEBUG_DENALI
1301 printk("read_oob %d\n", page); 981 printk(KERN_INFO "read_oob %d\n", page);
1302#endif 982#endif
1303 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, 983 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
1304 DENALI_READ) == PASS) 984 DENALI_READ) == PASS) {
1305 { 985 read_data_from_flash_mem(denali, buf, mtd->oobsize);
1306 read_data_from_flash_mem(denali, buf, mtd->oobsize);
1307 986
1308 /* wait for command to be accepted 987 /* wait for command to be accepted
1309 * can always use status0 bit as the mask is identical for each 988 * can always use status0 bit as the mask is identical for each
1310 * bank. */ 989 * bank. */
1311 irq_status = wait_for_irq(denali, irq_mask); 990 irq_status = wait_for_irq(denali, irq_mask);
1312 991
1313 if (irq_status == 0) 992 if (irq_status == 0)
1314 { 993 printk(KERN_ERR "page on OOB timeout %d\n",
1315 printk(KERN_ERR "page on OOB timeout %d\n", denali->page); 994 denali->page);
1316 }
1317 995
1318 /* We set the device back to MAIN_ACCESS here as I observed 996 /* We set the device back to MAIN_ACCESS here as I observed
1319 * instability with the controller if you do a block erase 997 * instability with the controller if you do a block erase
1320 * and the last transaction was a SPARE_ACCESS. Block erase 998 * and the last transaction was a SPARE_ACCESS. Block erase
1321 * is reliable (according to the MTD test infrastructure) 999 * is reliable (according to the MTD test infrastructure)
1322 * if you are in MAIN_ACCESS. 1000 * if you are in MAIN_ACCESS.
1323 */ 1001 */
1324 addr = BANK(denali->flash_bank) | denali->page; 1002 addr = BANK(denali->flash_bank) | denali->page;
1325 cmd = MODE_10 | addr; 1003 cmd = MODE_10 | addr;
1326 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); 1004 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
1327 1005
1328#if DEBUG_DENALI 1006#if DEBUG_DENALI
1329 spin_lock_irq(&denali->irq_lock); 1007 spin_lock_irq(&denali->irq_lock);
1330 denali->irq_debug_array[denali->idx++] = 0x60000000 | mtd->oobsize; 1008 denali->irq_debug_array[denali->idx++] =
1009 0x60000000 | mtd->oobsize;
1331 denali->idx %= 32; 1010 denali->idx %= 32;
1332 spin_unlock_irq(&denali->irq_lock); 1011 spin_unlock_irq(&denali->irq_lock);
1333#endif 1012#endif
1334 } 1013 }
1335} 1014}
1336 1015
1337/* this function examines buffers to see if they contain data that 1016/* this function examines buffers to see if they contain data that
1338 * indicate that the buffer is part of an erased region of flash. 1017 * indicate that the buffer is part of an erased region of flash.
1339 */ 1018 */
1340bool is_erased(uint8_t *buf, int len) 1019bool is_erased(uint8_t *buf, int len)
1341{ 1020{
1342 int i = 0; 1021 int i = 0;
1343 for (i = 0; i < len; i++) 1022 for (i = 0; i < len; i++)
1344 {
1345 if (buf[i] != 0xFF) 1023 if (buf[i] != 0xFF)
1346 {
1347 return false; 1024 return false;
1348 }
1349 }
1350 return true; 1025 return true;
1351} 1026}
1352#define ECC_SECTOR_SIZE 512 1027#define ECC_SECTOR_SIZE 512
@@ -1358,65 +1033,59 @@ bool is_erased(uint8_t *buf, int len)
1358#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8) 1033#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1359#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) 1034#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1360 1035
1361static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, 1036static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1362 uint8_t *oobbuf, uint32_t irq_status) 1037 uint8_t *oobbuf, uint32_t irq_status)
1363{ 1038{
1364 bool check_erased_page = false; 1039 bool check_erased_page = false;
1365 1040
1366 if (irq_status & INTR_STATUS0__ECC_ERR) 1041 if (irq_status & INTR_STATUS0__ECC_ERR) {
1367 {
1368 /* read the ECC errors. we'll ignore them for now */ 1042 /* read the ECC errors. we'll ignore them for now */
1369 uint32_t err_address = 0, err_correction_info = 0; 1043 uint32_t err_address = 0, err_correction_info = 0;
1370 uint32_t err_byte = 0, err_sector = 0, err_device = 0; 1044 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1371 uint32_t err_correction_value = 0; 1045 uint32_t err_correction_value = 0;
1372 1046
1373 do 1047 do {
1374 { 1048 err_address = ioread32(denali->flash_reg +
1375 err_address = ioread32(denali->flash_reg +
1376 ECC_ERROR_ADDRESS); 1049 ECC_ERROR_ADDRESS);
1377 err_sector = ECC_SECTOR(err_address); 1050 err_sector = ECC_SECTOR(err_address);
1378 err_byte = ECC_BYTE(err_address); 1051 err_byte = ECC_BYTE(err_address);
1379 1052
1380 1053
1381 err_correction_info = ioread32(denali->flash_reg + 1054 err_correction_info = ioread32(denali->flash_reg +
1382 ERR_CORRECTION_INFO); 1055 ERR_CORRECTION_INFO);
1383 err_correction_value = 1056 err_correction_value =
1384 ECC_CORRECTION_VALUE(err_correction_info); 1057 ECC_CORRECTION_VALUE(err_correction_info);
1385 err_device = ECC_ERR_DEVICE(err_correction_info); 1058 err_device = ECC_ERR_DEVICE(err_correction_info);
1386 1059
1387 if (ECC_ERROR_CORRECTABLE(err_correction_info)) 1060 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
1388 {
1389 /* offset in our buffer is computed as: 1061 /* offset in our buffer is computed as:
1390 sector number * sector size + offset in 1062 sector number * sector size + offset in
1391 sector 1063 sector
1392 */ 1064 */
1393 int offset = err_sector * ECC_SECTOR_SIZE + 1065 int offset = err_sector * ECC_SECTOR_SIZE +
1394 err_byte; 1066 err_byte;
1395 if (offset < denali->mtd.writesize) 1067 if (offset < denali->mtd.writesize) {
1396 {
1397 /* correct the ECC error */ 1068 /* correct the ECC error */
1398 buf[offset] ^= err_correction_value; 1069 buf[offset] ^= err_correction_value;
1399 denali->mtd.ecc_stats.corrected++; 1070 denali->mtd.ecc_stats.corrected++;
1400 } 1071 } else {
1401 else
1402 {
1403 /* bummer, couldn't correct the error */ 1072 /* bummer, couldn't correct the error */
1404 printk(KERN_ERR "ECC offset invalid\n"); 1073 printk(KERN_ERR "ECC offset invalid\n");
1405 denali->mtd.ecc_stats.failed++; 1074 denali->mtd.ecc_stats.failed++;
1406 } 1075 }
1407 } 1076 } else {
1408 else 1077 /* if the error is not correctable, need to
1409 { 1078 * look at the page to see if it is an erased
1410 /* if the error is not correctable, need to 1079 * page. if so, then it's not a real ECC error
1411 * look at the page to see if it is an erased page. 1080 * */
1412 * if so, then it's not a real ECC error */
1413 check_erased_page = true; 1081 check_erased_page = true;
1414 } 1082 }
1415 1083
1416#if DEBUG_DENALI 1084#if DEBUG_DENALI
1417 printk("Detected ECC error in page %d: err_addr = 0x%08x," 1085 printk(KERN_INFO "Detected ECC error in page %d:"
1418 " info to fix is 0x%08x\n", denali->page, err_address, 1086 " err_addr = 0x%08x, info to fix is"
1419 err_correction_info); 1087 " 0x%08x\n", denali->page, err_address,
1088 err_correction_info);
1420#endif 1089#endif
1421 } while (!ECC_LAST_ERR(err_correction_info)); 1090 } while (!ECC_LAST_ERR(err_correction_info));
1422 } 1091 }
@@ -1428,7 +1097,8 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1428{ 1097{
1429 uint32_t reg_val = 0x0; 1098 uint32_t reg_val = 0x0;
1430 1099
1431 if (en) reg_val = DMA_ENABLE__FLAG; 1100 if (en)
1101 reg_val = DMA_ENABLE__FLAG;
1432 1102
1433 denali_write32(reg_val, denali->flash_reg + DMA_ENABLE); 1103 denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
1434 ioread32(denali->flash_reg + DMA_ENABLE); 1104 ioread32(denali->flash_reg + DMA_ENABLE);
@@ -1458,9 +1128,9 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op)
1458 index_addr(denali, mode | 0x14000, 0x2400); 1128 index_addr(denali, mode | 0x14000, 0x2400);
1459} 1129}
1460 1130
1461/* writes a page. user specifies type, and this function handles the 1131/* writes a page. user specifies type, and this function handles the
1462 configuration details. */ 1132 configuration details. */
1463static void write_page(struct mtd_info *mtd, struct nand_chip *chip, 1133static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1464 const uint8_t *buf, bool raw_xfer) 1134 const uint8_t *buf, bool raw_xfer)
1465{ 1135{
1466 struct denali_nand_info *denali = mtd_to_denali(mtd); 1136 struct denali_nand_info *denali = mtd_to_denali(mtd);
@@ -1470,7 +1140,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1470 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1140 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1471 1141
1472 uint32_t irq_status = 0; 1142 uint32_t irq_status = 0;
1473 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | 1143 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
1474 INTR_STATUS0__PROGRAM_FAIL; 1144 INTR_STATUS0__PROGRAM_FAIL;
1475 1145
1476 /* if it is a raw xfer, we want to disable ecc, and send 1146 /* if it is a raw xfer, we want to disable ecc, and send
@@ -1483,74 +1153,73 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1483 /* copy buffer into DMA buffer */ 1153 /* copy buffer into DMA buffer */
1484 memcpy(denali->buf.buf, buf, mtd->writesize); 1154 memcpy(denali->buf.buf, buf, mtd->writesize);
1485 1155
1486 if (raw_xfer) 1156 if (raw_xfer) {
1487 {
1488 /* transfer the data to the spare area */ 1157 /* transfer the data to the spare area */
1489 memcpy(denali->buf.buf + mtd->writesize, 1158 memcpy(denali->buf.buf + mtd->writesize,
1490 chip->oob_poi, 1159 chip->oob_poi,
1491 mtd->oobsize); 1160 mtd->oobsize);
1492 } 1161 }
1493 1162
1494 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); 1163 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1495 1164
1496 clear_interrupts(denali); 1165 clear_interrupts(denali);
1497 denali_enable_dma(denali, true); 1166 denali_enable_dma(denali, true);
1498 1167
1499 denali_setup_dma(denali, DENALI_WRITE); 1168 denali_setup_dma(denali, DENALI_WRITE);
1500 1169
1501 /* wait for operation to complete */ 1170 /* wait for operation to complete */
1502 irq_status = wait_for_irq(denali, irq_mask); 1171 irq_status = wait_for_irq(denali, irq_mask);
1503 1172
1504 if (irq_status == 0) 1173 if (irq_status == 0) {
1505 { 1174 printk(KERN_ERR "timeout on write_page"
1506 printk(KERN_ERR "timeout on write_page (type = %d)\n", raw_xfer); 1175 " (type = %d)\n", raw_xfer);
1507 denali->status = 1176 denali->status =
1508 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? NAND_STATUS_FAIL : 1177 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1509 PASS; 1178 NAND_STATUS_FAIL : PASS;
1510 } 1179 }
1511 1180
1512 denali_enable_dma(denali, false); 1181 denali_enable_dma(denali, false);
1513 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); 1182 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1514} 1183}
1515 1184
1516/* NAND core entry points */ 1185/* NAND core entry points */
1517 1186
1518/* this is the callback that the NAND core calls to write a page. Since 1187/* this is the callback that the NAND core calls to write a page. Since
1519 writing a page with ECC or without is similar, all the work is done 1188 writing a page with ECC or without is similar, all the work is done
1520 by write_page above. */ 1189 by write_page above. */
1521static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, 1190static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1522 const uint8_t *buf) 1191 const uint8_t *buf)
1523{ 1192{
1524 /* for regular page writes, we let HW handle all the ECC 1193 /* for regular page writes, we let HW handle all the ECC
1525 * data written to the device. */ 1194 * data written to the device. */
1526 write_page(mtd, chip, buf, false); 1195 write_page(mtd, chip, buf, false);
1527} 1196}
1528 1197
1529/* This is the callback that the NAND core calls to write a page without ECC. 1198/* This is the callback that the NAND core calls to write a page without ECC.
1530 raw access is similiar to ECC page writes, so all the work is done in the 1199 raw access is similiar to ECC page writes, so all the work is done in the
1531 write_page() function above. 1200 write_page() function above.
1532 */ 1201 */
1533static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1202static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1534 const uint8_t *buf) 1203 const uint8_t *buf)
1535{ 1204{
1536 /* for raw page writes, we want to disable ECC and simply write 1205 /* for raw page writes, we want to disable ECC and simply write
1537 whatever data is in the buffer. */ 1206 whatever data is in the buffer. */
1538 write_page(mtd, chip, buf, true); 1207 write_page(mtd, chip, buf, true);
1539} 1208}
1540 1209
1541static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 1210static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1542 int page) 1211 int page)
1543{ 1212{
1544 return write_oob_data(mtd, chip->oob_poi, page); 1213 return write_oob_data(mtd, chip->oob_poi, page);
1545} 1214}
1546 1215
1547static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 1216static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1548 int page, int sndcmd) 1217 int page, int sndcmd)
1549{ 1218{
1550 read_oob_data(mtd, chip->oob_poi, page); 1219 read_oob_data(mtd, chip->oob_poi, page);
1551 1220
1552 return 0; /* notify NAND core to send command to 1221 return 0; /* notify NAND core to send command to
1553 * NAND device. */ 1222 NAND device. */
1554} 1223}
1555 1224
1556static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, 1225static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
@@ -1563,7 +1232,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1563 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1232 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1564 1233
1565 uint32_t irq_status = 0; 1234 uint32_t irq_status = 0;
1566 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | 1235 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
1567 INTR_STATUS0__ECC_ERR; 1236 INTR_STATUS0__ECC_ERR;
1568 bool check_erased_page = false; 1237 bool check_erased_page = false;
1569 1238
@@ -1581,26 +1250,20 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1581 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1250 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1582 1251
1583 memcpy(buf, denali->buf.buf, mtd->writesize); 1252 memcpy(buf, denali->buf.buf, mtd->writesize);
1584 1253
1585 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status); 1254 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
1586 denali_enable_dma(denali, false); 1255 denali_enable_dma(denali, false);
1587 1256
1588 if (check_erased_page) 1257 if (check_erased_page) {
1589 {
1590 read_oob_data(&denali->mtd, chip->oob_poi, denali->page); 1258 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1591 1259
1592 /* check ECC failures that may have occurred on erased pages */ 1260 /* check ECC failures that may have occurred on erased pages */
1593 if (check_erased_page) 1261 if (check_erased_page) {
1594 {
1595 if (!is_erased(buf, denali->mtd.writesize)) 1262 if (!is_erased(buf, denali->mtd.writesize))
1596 {
1597 denali->mtd.ecc_stats.failed++; 1263 denali->mtd.ecc_stats.failed++;
1598 }
1599 if (!is_erased(buf, denali->mtd.oobsize)) 1264 if (!is_erased(buf, denali->mtd.oobsize))
1600 {
1601 denali->mtd.ecc_stats.failed++; 1265 denali->mtd.ecc_stats.failed++;
1602 } 1266 }
1603 }
1604 } 1267 }
1605 return 0; 1268 return 0;
1606} 1269}
@@ -1616,7 +1279,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1616 1279
1617 uint32_t irq_status = 0; 1280 uint32_t irq_status = 0;
1618 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; 1281 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1619 1282
1620 setup_ecc_for_xfer(denali, false, true); 1283 setup_ecc_for_xfer(denali, false, true);
1621 denali_enable_dma(denali, true); 1284 denali_enable_dma(denali, true);
1622 1285
@@ -1644,12 +1307,10 @@ static uint8_t denali_read_byte(struct mtd_info *mtd)
1644 uint8_t result = 0xff; 1307 uint8_t result = 0xff;
1645 1308
1646 if (denali->buf.head < denali->buf.tail) 1309 if (denali->buf.head < denali->buf.tail)
1647 {
1648 result = denali->buf.buf[denali->buf.head++]; 1310 result = denali->buf.buf[denali->buf.head++];
1649 }
1650 1311
1651#if DEBUG_DENALI 1312#if DEBUG_DENALI
1652 printk("read byte -> 0x%02x\n", result); 1313 printk(KERN_INFO "read byte -> 0x%02x\n", result);
1653#endif 1314#endif
1654 return result; 1315 return result;
1655} 1316}
@@ -1658,7 +1319,7 @@ static void denali_select_chip(struct mtd_info *mtd, int chip)
1658{ 1319{
1659 struct denali_nand_info *denali = mtd_to_denali(mtd); 1320 struct denali_nand_info *denali = mtd_to_denali(mtd);
1660#if DEBUG_DENALI 1321#if DEBUG_DENALI
1661 printk("denali select chip %d\n", chip); 1322 printk(KERN_INFO "denali select chip %d\n", chip);
1662#endif 1323#endif
1663 spin_lock_irq(&denali->irq_lock); 1324 spin_lock_irq(&denali->irq_lock);
1664 denali->flash_bank = chip; 1325 denali->flash_bank = chip;
@@ -1672,7 +1333,7 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1672 denali->status = 0; 1333 denali->status = 0;
1673 1334
1674#if DEBUG_DENALI 1335#if DEBUG_DENALI
1675 printk("waitfunc %d\n", status); 1336 printk(KERN_INFO "waitfunc %d\n", status);
1676#endif 1337#endif
1677 return status; 1338 return status;
1678} 1339}
@@ -1684,76 +1345,74 @@ static void denali_erase(struct mtd_info *mtd, int page)
1684 uint32_t cmd = 0x0, irq_status = 0; 1345 uint32_t cmd = 0x0, irq_status = 0;
1685 1346
1686#if DEBUG_DENALI 1347#if DEBUG_DENALI
1687 printk("erase page: %d\n", page); 1348 printk(KERN_INFO "erase page: %d\n", page);
1688#endif 1349#endif
1689 /* clear interrupts */ 1350 /* clear interrupts */
1690 clear_interrupts(denali); 1351 clear_interrupts(denali);
1691 1352
1692 /* setup page read request for access type */ 1353 /* setup page read request for access type */
1693 cmd = MODE_10 | BANK(denali->flash_bank) | page; 1354 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1694 index_addr(denali, (uint32_t)cmd, 0x1); 1355 index_addr(denali, (uint32_t)cmd, 0x1);
1695 1356
1696 /* wait for erase to complete or failure to occur */ 1357 /* wait for erase to complete or failure to occur */
1697 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | 1358 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1698 INTR_STATUS0__ERASE_FAIL); 1359 INTR_STATUS0__ERASE_FAIL);
1699 1360
1700 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? NAND_STATUS_FAIL : 1361 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1701 PASS; 1362 NAND_STATUS_FAIL : PASS;
1702} 1363}
1703 1364
1704static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, 1365static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1705 int page) 1366 int page)
1706{ 1367{
1707 struct denali_nand_info *denali = mtd_to_denali(mtd); 1368 struct denali_nand_info *denali = mtd_to_denali(mtd);
1369 uint32_t addr, id;
1370 int i;
1708 1371
1709#if DEBUG_DENALI 1372#if DEBUG_DENALI
1710 printk("cmdfunc: 0x%x %d %d\n", cmd, col, page); 1373 printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
1711#endif 1374#endif
1712 switch (cmd) 1375 switch (cmd) {
1713 { 1376 case NAND_CMD_PAGEPROG:
1714 case NAND_CMD_PAGEPROG: 1377 break;
1715 break; 1378 case NAND_CMD_STATUS:
1716 case NAND_CMD_STATUS: 1379 read_status(denali);
1717 read_status(denali); 1380 break;
1718 break; 1381 case NAND_CMD_READID:
1719 case NAND_CMD_READID: 1382 reset_buf(denali);
1720 reset_buf(denali); 1383 /*sometimes ManufactureId read from register is not right
1721 if (denali->flash_bank < denali->total_used_banks) 1384 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1722 { 1385 * So here we send READID cmd to NAND insteand
1723 /* write manufacturer information into nand 1386 * */
1724 buffer for NAND subsystem to fetch. 1387 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1725 */ 1388 index_addr(denali, (uint32_t)addr | 0, 0x90);
1726 write_byte_to_buf(denali, denali->dev_info.wDeviceMaker); 1389 index_addr(denali, (uint32_t)addr | 1, 0);
1727 write_byte_to_buf(denali, denali->dev_info.wDeviceID); 1390 for (i = 0; i < 5; i++) {
1728 write_byte_to_buf(denali, denali->dev_info.bDeviceParam0); 1391 index_addr_read_data(denali,
1729 write_byte_to_buf(denali, denali->dev_info.bDeviceParam1); 1392 (uint32_t)addr | 2,
1730 write_byte_to_buf(denali, denali->dev_info.bDeviceParam2); 1393 &id);
1731 } 1394 write_byte_to_buf(denali, id);
1732 else 1395 }
1733 { 1396 break;
1734 int i; 1397 case NAND_CMD_READ0:
1735 for (i = 0; i < 5; i++) 1398 case NAND_CMD_SEQIN:
1736 write_byte_to_buf(denali, 0xff); 1399 denali->page = page;
1737 } 1400 break;
1738 break; 1401 case NAND_CMD_RESET:
1739 case NAND_CMD_READ0: 1402 reset_bank(denali);
1740 case NAND_CMD_SEQIN: 1403 break;
1741 denali->page = page; 1404 case NAND_CMD_READOOB:
1742 break; 1405 /* TODO: Read OOB data */
1743 case NAND_CMD_RESET: 1406 break;
1744 reset_bank(denali); 1407 default:
1745 break; 1408 printk(KERN_ERR ": unsupported command"
1746 case NAND_CMD_READOOB: 1409 " received 0x%x\n", cmd);
1747 /* TODO: Read OOB data */ 1410 break;
1748 break;
1749 default:
1750 printk(KERN_ERR ": unsupported command received 0x%x\n", cmd);
1751 break;
1752 } 1411 }
1753} 1412}
1754 1413
1755/* stubs for ECC functions not used by the NAND core */ 1414/* stubs for ECC functions not used by the NAND core */
1756static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, 1415static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1757 uint8_t *ecc_code) 1416 uint8_t *ecc_code)
1758{ 1417{
1759 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n"); 1418 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
@@ -1761,7 +1420,7 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1761 return -EIO; 1420 return -EIO;
1762} 1421}
1763 1422
1764static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, 1423static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1765 uint8_t *read_ecc, uint8_t *calc_ecc) 1424 uint8_t *read_ecc, uint8_t *calc_ecc)
1766{ 1425{
1767 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n"); 1426 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
@@ -1779,10 +1438,18 @@ static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1779/* Initialization code to bring the device up to a known good state */ 1438/* Initialization code to bring the device up to a known good state */
1780static void denali_hw_init(struct denali_nand_info *denali) 1439static void denali_hw_init(struct denali_nand_info *denali)
1781{ 1440{
1441 /* tell driver how many bit controller will skip before
1442 * writing ECC code in OOB, this register may be already
1443 * set by firmware. So we read this value out.
1444 * if this value is 0, just let it be.
1445 * */
1446 denali->bbtskipbytes = ioread32(denali->flash_reg +
1447 SPARE_AREA_SKIP_BYTES);
1782 denali_irq_init(denali); 1448 denali_irq_init(denali);
1783 NAND_Flash_Reset(denali); 1449 denali_nand_reset(denali);
1784 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED); 1450 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1785 denali_write32(CHIP_EN_DONT_CARE__FLAG, denali->flash_reg + CHIP_ENABLE_DONT_CARE); 1451 denali_write32(CHIP_EN_DONT_CARE__FLAG,
1452 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1786 1453
1787 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES); 1454 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1788 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); 1455 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
@@ -1792,25 +1459,18 @@ static void denali_hw_init(struct denali_nand_info *denali)
1792 denali_write32(1, denali->flash_reg + ECC_ENABLE); 1459 denali_write32(1, denali->flash_reg + ECC_ENABLE);
1793} 1460}
1794 1461
1795/* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */ 1462/* Althogh controller spec said SLC ECC is forceb to be 4bit,
1796#define ECC_BYTES_SLC 4 * (2048 / ECC_SECTOR_SIZE) 1463 * but denali controller in MRST only support 15bit and 8bit ECC
1797static struct nand_ecclayout nand_oob_slc = { 1464 * correction
1798 .eccbytes = 4, 1465 * */
1799 .eccpos = { 0, 1, 2, 3 }, /* not used */ 1466#define ECC_8BITS 14
1800 .oobfree = {{ 1467static struct nand_ecclayout nand_8bit_oob = {
1801 .offset = ECC_BYTES_SLC, 1468 .eccbytes = 14,
1802 .length = 64 - ECC_BYTES_SLC
1803 }}
1804}; 1469};
1805 1470
1806#define ECC_BYTES_MLC 14 * (2048 / ECC_SECTOR_SIZE) 1471#define ECC_15BITS 26
1807static struct nand_ecclayout nand_oob_mlc_14bit = { 1472static struct nand_ecclayout nand_15bit_oob = {
1808 .eccbytes = 14, 1473 .eccbytes = 26,
1809 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
1810 .oobfree = {{
1811 .offset = ECC_BYTES_MLC,
1812 .length = 64 - ECC_BYTES_MLC
1813 }}
1814}; 1474};
1815 1475
1816static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; 1476static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
@@ -1842,12 +1502,12 @@ void denali_drv_init(struct denali_nand_info *denali)
1842 denali->idx = 0; 1502 denali->idx = 0;
1843 1503
1844 /* setup interrupt handler */ 1504 /* setup interrupt handler */
1845 /* the completion object will be used to notify 1505 /* the completion object will be used to notify
1846 * the callee that the interrupt is done */ 1506 * the callee that the interrupt is done */
1847 init_completion(&denali->complete); 1507 init_completion(&denali->complete);
1848 1508
1849 /* the spinlock will be used to synchronize the ISR 1509 /* the spinlock will be used to synchronize the ISR
1850 * with any element that might be access shared 1510 * with any element that might be access shared
1851 * data (interrupt status) */ 1511 * data (interrupt status) */
1852 spin_lock_init(&denali->irq_lock); 1512 spin_lock_init(&denali->irq_lock);
1853 1513
@@ -1880,13 +1540,12 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1880 } 1540 }
1881 1541
1882 if (id->driver_data == INTEL_CE4100) { 1542 if (id->driver_data == INTEL_CE4100) {
1883 /* Due to a silicon limitation, we can only support 1543 /* Due to a silicon limitation, we can only support
1884 * ONFI timing mode 1 and below. 1544 * ONFI timing mode 1 and below.
1885 */ 1545 */
1886 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) 1546 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1887 { 1547 printk(KERN_ERR "Intel CE4100 only supports"
1888 printk("Intel CE4100 only supports ONFI timing mode 1 " 1548 " ONFI timing mode 1 or below\n");
1889 "or below\n");
1890 ret = -EINVAL; 1549 ret = -EINVAL;
1891 goto failed_enable; 1550 goto failed_enable;
1892 } 1551 }
@@ -1905,7 +1564,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1905 mem_base = csr_base + csr_len; 1564 mem_base = csr_base + csr_len;
1906 mem_len = csr_len; 1565 mem_len = csr_len;
1907 nand_dbg_print(NAND_DBG_WARN, 1566 nand_dbg_print(NAND_DBG_WARN,
1908 "Spectra: No second BAR for PCI device; assuming %08Lx\n", 1567 "Spectra: No second"
1568 " BAR for PCI device;"
1569 " assuming %08Lx\n",
1909 (uint64_t)csr_base); 1570 (uint64_t)csr_base);
1910 } 1571 }
1911 } 1572 }
@@ -1913,16 +1574,16 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1913 /* Is 32-bit DMA supported? */ 1574 /* Is 32-bit DMA supported? */
1914 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32)); 1575 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1915 1576
1916 if (ret) 1577 if (ret) {
1917 {
1918 printk(KERN_ERR "Spectra: no usable DMA configuration\n"); 1578 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1919 goto failed_enable; 1579 goto failed_enable;
1920 } 1580 }
1921 denali->buf.dma_buf = pci_map_single(dev, denali->buf.buf, DENALI_BUF_SIZE, 1581 denali->buf.dma_buf =
1922 PCI_DMA_BIDIRECTIONAL); 1582 pci_map_single(dev, denali->buf.buf,
1583 DENALI_BUF_SIZE,
1584 PCI_DMA_BIDIRECTIONAL);
1923 1585
1924 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) 1586 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1925 {
1926 printk(KERN_ERR "Spectra: failed to map DMA buffer\n"); 1587 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1927 goto failed_enable; 1588 goto failed_enable;
1928 } 1589 }
@@ -1970,22 +1631,11 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1970 } 1631 }
1971 1632
1972 /* now that our ISR is registered, we can enable interrupts */ 1633 /* now that our ISR is registered, we can enable interrupts */
1973 NAND_LLD_Enable_Disable_Interrupts(denali, true); 1634 denali_set_intr_modes(denali, true);
1974 1635
1975 pci_set_drvdata(dev, denali); 1636 pci_set_drvdata(dev, denali);
1976 1637
1977 NAND_Read_Device_ID(denali); 1638 denali_nand_timing_set(denali);
1978
1979 /* MTD supported page sizes vary by kernel. We validate our
1980 kernel supports the device here.
1981 */
1982 if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
1983 {
1984 ret = -ENODEV;
1985 printk(KERN_ERR "Spectra: device size not supported by this "
1986 "version of MTD.");
1987 goto failed_nand;
1988 }
1989 1639
1990 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" 1640 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1991 "acc_clks: %d, re_2_we: %d, we_2_re: %d," 1641 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
@@ -2009,18 +1659,46 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2009 denali->nand.read_byte = denali_read_byte; 1659 denali->nand.read_byte = denali_read_byte;
2010 denali->nand.waitfunc = denali_waitfunc; 1660 denali->nand.waitfunc = denali_waitfunc;
2011 1661
2012 /* scan for NAND devices attached to the controller 1662 /* scan for NAND devices attached to the controller
2013 * this is the first stage in a two step process to register 1663 * this is the first stage in a two step process to register
2014 * with the nand subsystem */ 1664 * with the nand subsystem */
2015 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) 1665 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
2016 {
2017 ret = -ENXIO; 1666 ret = -ENXIO;
2018 goto failed_nand; 1667 goto failed_nand;
2019 } 1668 }
2020 1669
2021 /* second stage of the NAND scan 1670 /* MTD supported page sizes vary by kernel. We validate our
2022 * this stage requires information regarding ECC and 1671 * kernel supports the device here.
2023 * bad block management. */ 1672 */
1673 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1674 ret = -ENODEV;
1675 printk(KERN_ERR "Spectra: device size not supported by this "
1676 "version of MTD.");
1677 goto failed_nand;
1678 }
1679
1680 /* support for multi nand
1681 * MTD known nothing about multi nand,
1682 * so we should tell it the real pagesize
1683 * and anything necessery
1684 */
1685 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1686 denali->nand.chipsize <<= (denali->devnum - 1);
1687 denali->nand.page_shift += (denali->devnum - 1);
1688 denali->nand.pagemask = (denali->nand.chipsize >>
1689 denali->nand.page_shift) - 1;
1690 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1691 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1692 denali->nand.chip_shift += (denali->devnum - 1);
1693 denali->mtd.writesize <<= (denali->devnum - 1);
1694 denali->mtd.oobsize <<= (denali->devnum - 1);
1695 denali->mtd.erasesize <<= (denali->devnum - 1);
1696 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1697 denali->bbtskipbytes *= denali->devnum;
1698
1699 /* second stage of the NAND scan
1700 * this stage requires information regarding ECC and
1701 * bad block management. */
2024 1702
2025 /* Bad block management */ 1703 /* Bad block management */
2026 denali->nand.bbt_td = &bbt_main_descr; 1704 denali->nand.bbt_td = &bbt_main_descr;
@@ -2030,26 +1708,57 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2030 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN; 1708 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
2031 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 1709 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
2032 1710
2033 if (denali->dev_info.MLCDevice) 1711 /* Denali Controller only support 15bit and 8bit ECC in MRST,
2034 { 1712 * so just let controller do 15bit ECC for MLC and 8bit ECC for
2035 denali->nand.ecc.layout = &nand_oob_mlc_14bit; 1713 * SLC if possible.
2036 denali->nand.ecc.bytes = ECC_BYTES_MLC; 1714 * */
2037 } 1715 if (denali->nand.cellinfo & 0xc &&
2038 else /* SLC */ 1716 (denali->mtd.oobsize > (denali->bbtskipbytes +
2039 { 1717 ECC_15BITS * (denali->mtd.writesize /
2040 denali->nand.ecc.layout = &nand_oob_slc; 1718 ECC_SECTOR_SIZE)))) {
2041 denali->nand.ecc.bytes = ECC_BYTES_SLC; 1719 /* if MLC OOB size is large enough, use 15bit ECC*/
1720 denali->nand.ecc.layout = &nand_15bit_oob;
1721 denali->nand.ecc.bytes = ECC_15BITS;
1722 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
1723 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1724 ECC_8BITS * (denali->mtd.writesize /
1725 ECC_SECTOR_SIZE))) {
1726 printk(KERN_ERR "Your NAND chip OOB is not large enough to"
1727 " contain 8bit ECC correction codes");
1728 goto failed_nand;
1729 } else {
1730 denali->nand.ecc.layout = &nand_8bit_oob;
1731 denali->nand.ecc.bytes = ECC_8BITS;
1732 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
2042 } 1733 }
2043 1734
2044 /* These functions are required by the NAND core framework, otherwise, 1735 denali->nand.ecc.bytes *= denali->devnum;
2045 the NAND core will assert. However, we don't need them, so we'll stub 1736 denali->nand.ecc.layout->eccbytes *=
2046 them out. */ 1737 denali->mtd.writesize / ECC_SECTOR_SIZE;
1738 denali->nand.ecc.layout->oobfree[0].offset =
1739 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1740 denali->nand.ecc.layout->oobfree[0].length =
1741 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1742 denali->bbtskipbytes;
1743
1744 /* Let driver know the total blocks number and
1745 * how many blocks contained by each nand chip.
1746 * blksperchip will help driver to know how many
1747 * blocks is taken by FW.
1748 * */
1749 denali->totalblks = denali->mtd.size >>
1750 denali->nand.phys_erase_shift;
1751 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1752
1753 /* These functions are required by the NAND core framework, otherwise,
1754 * the NAND core will assert. However, we don't need them, so we'll stub
1755 * them out. */
2047 denali->nand.ecc.calculate = denali_ecc_calculate; 1756 denali->nand.ecc.calculate = denali_ecc_calculate;
2048 denali->nand.ecc.correct = denali_ecc_correct; 1757 denali->nand.ecc.correct = denali_ecc_correct;
2049 denali->nand.ecc.hwctl = denali_ecc_hwctl; 1758 denali->nand.ecc.hwctl = denali_ecc_hwctl;
2050 1759
2051 /* override the default read operations */ 1760 /* override the default read operations */
2052 denali->nand.ecc.size = denali->mtd.writesize; 1761 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
2053 denali->nand.ecc.read_page = denali_read_page; 1762 denali->nand.ecc.read_page = denali_read_page;
2054 denali->nand.ecc.read_page_raw = denali_read_page_raw; 1763 denali->nand.ecc.read_page_raw = denali_read_page_raw;
2055 denali->nand.ecc.write_page = denali_write_page; 1764 denali->nand.ecc.write_page = denali_write_page;
@@ -2058,15 +1767,15 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2058 denali->nand.ecc.write_oob = denali_write_oob; 1767 denali->nand.ecc.write_oob = denali_write_oob;
2059 denali->nand.erase_cmd = denali_erase; 1768 denali->nand.erase_cmd = denali_erase;
2060 1769
2061 if (nand_scan_tail(&denali->mtd)) 1770 if (nand_scan_tail(&denali->mtd)) {
2062 {
2063 ret = -ENXIO; 1771 ret = -ENXIO;
2064 goto failed_nand; 1772 goto failed_nand;
2065 } 1773 }
2066 1774
2067 ret = add_mtd_device(&denali->mtd); 1775 ret = add_mtd_device(&denali->mtd);
2068 if (ret) { 1776 if (ret) {
2069 printk(KERN_ERR "Spectra: Failed to register MTD device: %d\n", ret); 1777 printk(KERN_ERR "Spectra: Failed to register"
1778 " MTD device: %d\n", ret);
2070 goto failed_nand; 1779 goto failed_nand;
2071 } 1780 }
2072 return 0; 1781 return 0;
@@ -2079,7 +1788,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
2079 failed_remap_csr: 1788 failed_remap_csr:
2080 pci_release_regions(dev); 1789 pci_release_regions(dev);
2081 failed_req_csr: 1790 failed_req_csr:
2082 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 1791 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
2083 PCI_DMA_BIDIRECTIONAL); 1792 PCI_DMA_BIDIRECTIONAL);
2084 failed_enable: 1793 failed_enable:
2085 kfree(denali); 1794 kfree(denali);
@@ -2103,7 +1812,7 @@ static void denali_pci_remove(struct pci_dev *dev)
2103 iounmap(denali->flash_mem); 1812 iounmap(denali->flash_mem);
2104 pci_release_regions(dev); 1813 pci_release_regions(dev);
2105 pci_disable_device(dev); 1814 pci_disable_device(dev);
2106 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 1815 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
2107 PCI_DMA_BIDIRECTIONAL); 1816 PCI_DMA_BIDIRECTIONAL);
2108 pci_set_drvdata(dev, NULL); 1817 pci_set_drvdata(dev, NULL);
2109 kfree(denali); 1818 kfree(denali);
@@ -2120,7 +1829,8 @@ static struct pci_driver denali_pci_driver = {
2120 1829
2121static int __devinit denali_init(void) 1830static int __devinit denali_init(void)
2122{ 1831{
2123 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n", __DATE__, __TIME__); 1832 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
1833 __DATE__, __TIME__);
2124 return pci_register_driver(&denali_pci_driver); 1834 return pci_register_driver(&denali_pci_driver);
2125} 1835}
2126 1836
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 10:34:40 -0500