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path: root/drivers/mtd/nand/denali.c
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Diffstat (limited to 'drivers/mtd/nand/denali.c')
-rw-r--r--drivers/mtd/nand/denali.c247
1 files changed, 113 insertions, 134 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 4633f094c510..d5276218945f 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
22#include <linux/wait.h> 23#include <linux/wait.h>
23#include <linux/mutex.h> 24#include <linux/mutex.h>
24#include <linux/slab.h> 25#include <linux/slab.h>
@@ -44,16 +45,16 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
44 45
45/* We define a macro here that combines all interrupts this driver uses into 46/* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */ 47 * a single constant value, for convenience. */
47#define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \ 48#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \ 49 INTR_STATUS__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \ 50 INTR_STATUS__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \ 51 INTR_STATUS__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \ 52 INTR_STATUS__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \ 53 INTR_STATUS__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \ 54 INTR_STATUS__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \ 55 INTR_STATUS__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \ 56 INTR_STATUS__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP) 57 INTR_STATUS__ERASE_COMP)
57 58
58/* indicates whether or not the internal value for the flash bank is 59/* indicates whether or not the internal value for the flash bank is
59 * valid or not */ 60 * valid or not */
@@ -95,30 +96,6 @@ static const struct pci_device_id denali_pci_ids[] = {
95 { /* end: all zeroes */ } 96 { /* end: all zeroes */ }
96}; 97};
97 98
98
99/* these are static lookup tables that give us easy access to
100 * registers in the NAND controller.
101 */
102static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103 INTR_STATUS1,
104 INTR_STATUS2,
105 INTR_STATUS3};
106
107static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
108 DEVICE_RESET__BANK1,
109 DEVICE_RESET__BANK2,
110 DEVICE_RESET__BANK3};
111
112static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
113 INTR_STATUS1__TIME_OUT,
114 INTR_STATUS2__TIME_OUT,
115 INTR_STATUS3__TIME_OUT};
116
117static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
118 INTR_STATUS1__RST_COMP,
119 INTR_STATUS2__RST_COMP,
120 INTR_STATUS3__RST_COMP};
121
122/* forward declarations */ 99/* forward declarations */
123static void clear_interrupts(struct denali_nand_info *denali); 100static void clear_interrupts(struct denali_nand_info *denali);
124static uint32_t wait_for_irq(struct denali_nand_info *denali, 101static uint32_t wait_for_irq(struct denali_nand_info *denali,
@@ -180,19 +157,17 @@ static void read_status(struct denali_nand_info *denali)
180static void reset_bank(struct denali_nand_info *denali) 157static void reset_bank(struct denali_nand_info *denali)
181{ 158{
182 uint32_t irq_status = 0; 159 uint32_t irq_status = 0;
183 uint32_t irq_mask = reset_complete[denali->flash_bank] | 160 uint32_t irq_mask = INTR_STATUS__RST_COMP |
184 operation_timeout[denali->flash_bank]; 161 INTR_STATUS__TIME_OUT;
185 int bank = 0;
186 162
187 clear_interrupts(denali); 163 clear_interrupts(denali);
188 164
189 bank = device_reset_banks[denali->flash_bank]; 165 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
190 iowrite32(bank, denali->flash_reg + DEVICE_RESET);
191 166
192 irq_status = wait_for_irq(denali, irq_mask); 167 irq_status = wait_for_irq(denali, irq_mask);
193 168
194 if (irq_status & operation_timeout[denali->flash_bank]) 169 if (irq_status & INTR_STATUS__TIME_OUT)
195 dev_err(&denali->dev->dev, "reset bank failed.\n"); 170 dev_err(denali->dev, "reset bank failed.\n");
196} 171}
197 172
198/* Reset the flash controller */ 173/* Reset the flash controller */
@@ -200,29 +175,28 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
200{ 175{
201 uint32_t i; 176 uint32_t i;
202 177
203 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", 178 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
204 __FILE__, __LINE__, __func__); 179 __FILE__, __LINE__, __func__);
205 180
206 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) 181 for (i = 0 ; i < denali->max_banks; i++)
207 iowrite32(reset_complete[i] | operation_timeout[i], 182 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
208 denali->flash_reg + intr_status_addresses[i]); 183 denali->flash_reg + INTR_STATUS(i));
209 184
210 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { 185 for (i = 0 ; i < denali->max_banks; i++) {
211 iowrite32(device_reset_banks[i], 186 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
212 denali->flash_reg + DEVICE_RESET);
213 while (!(ioread32(denali->flash_reg + 187 while (!(ioread32(denali->flash_reg +
214 intr_status_addresses[i]) & 188 INTR_STATUS(i)) &
215 (reset_complete[i] | operation_timeout[i]))) 189 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
216 cpu_relax(); 190 cpu_relax();
217 if (ioread32(denali->flash_reg + intr_status_addresses[i]) & 191 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
218 operation_timeout[i]) 192 INTR_STATUS__TIME_OUT)
219 dev_dbg(&denali->dev->dev, 193 dev_dbg(denali->dev,
220 "NAND Reset operation timed out on bank %d\n", i); 194 "NAND Reset operation timed out on bank %d\n", i);
221 } 195 }
222 196
223 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) 197 for (i = 0; i < denali->max_banks; i++)
224 iowrite32(reset_complete[i] | operation_timeout[i], 198 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
225 denali->flash_reg + intr_status_addresses[i]); 199 denali->flash_reg + INTR_STATUS(i));
226 200
227 return PASS; 201 return PASS;
228} 202}
@@ -254,7 +228,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
254 uint16_t acc_clks; 228 uint16_t acc_clks;
255 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; 229 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
256 230
257 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", 231 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
258 __FILE__, __LINE__, __func__); 232 __FILE__, __LINE__, __func__);
259 233
260 en_lo = CEIL_DIV(Trp[mode], CLK_X); 234 en_lo = CEIL_DIV(Trp[mode], CLK_X);
@@ -291,7 +265,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
291 acc_clks++; 265 acc_clks++;
292 266
293 if ((data_invalid - acc_clks * CLK_X) < 2) 267 if ((data_invalid - acc_clks * CLK_X) < 2)
294 dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n", 268 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
295 __FILE__, __LINE__); 269 __FILE__, __LINE__);
296 270
297 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); 271 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
@@ -419,7 +393,7 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
419#endif 393#endif
420 break; 394 break;
421 default: 395 default:
422 dev_warn(&denali->dev->dev, 396 dev_warn(denali->dev,
423 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." 397 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
424 "Will use default parameter values instead.\n", 398 "Will use default parameter values instead.\n",
425 device_id); 399 device_id);
@@ -431,17 +405,17 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
431 */ 405 */
432static void find_valid_banks(struct denali_nand_info *denali) 406static void find_valid_banks(struct denali_nand_info *denali)
433{ 407{
434 uint32_t id[LLD_MAX_FLASH_BANKS]; 408 uint32_t id[denali->max_banks];
435 int i; 409 int i;
436 410
437 denali->total_used_banks = 1; 411 denali->total_used_banks = 1;
438 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { 412 for (i = 0; i < denali->max_banks; i++) {
439 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); 413 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
440 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); 414 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
441 index_addr_read_data(denali, 415 index_addr_read_data(denali,
442 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); 416 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
443 417
444 dev_dbg(&denali->dev->dev, 418 dev_dbg(denali->dev,
445 "Return 1st ID for bank[%d]: %x\n", i, id[i]); 419 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
446 420
447 if (i == 0) { 421 if (i == 0) {
@@ -461,16 +435,27 @@ static void find_valid_banks(struct denali_nand_info *denali)
461 * Multichip support is not enabled. 435 * Multichip support is not enabled.
462 */ 436 */
463 if (denali->total_used_banks != 1) { 437 if (denali->total_used_banks != 1) {
464 dev_err(&denali->dev->dev, 438 dev_err(denali->dev,
465 "Sorry, Intel CE4100 only supports " 439 "Sorry, Intel CE4100 only supports "
466 "a single NAND device.\n"); 440 "a single NAND device.\n");
467 BUG(); 441 BUG();
468 } 442 }
469 } 443 }
470 dev_dbg(&denali->dev->dev, 444 dev_dbg(denali->dev,
471 "denali->total_used_banks: %d\n", denali->total_used_banks); 445 "denali->total_used_banks: %d\n", denali->total_used_banks);
472} 446}
473 447
448/*
449 * Use the configuration feature register to determine the maximum number of
450 * banks that the hardware supports.
451 */
452static void detect_max_banks(struct denali_nand_info *denali)
453{
454 uint32_t features = ioread32(denali->flash_reg + FEATURES);
455
456 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
457}
458
474static void detect_partition_feature(struct denali_nand_info *denali) 459static void detect_partition_feature(struct denali_nand_info *denali)
475{ 460{
476 /* For MRST platform, denali->fwblks represent the 461 /* For MRST platform, denali->fwblks represent the
@@ -480,15 +465,15 @@ static void detect_partition_feature(struct denali_nand_info *denali)
480 * blocks it can't touch. 465 * blocks it can't touch.
481 * */ 466 * */
482 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { 467 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
483 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & 468 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
484 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { 469 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
485 denali->fwblks = 470 denali->fwblks =
486 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & 471 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
487 MIN_MAX_BANK_1__MIN_VALUE) * 472 MIN_MAX_BANK__MIN_VALUE) *
488 denali->blksperchip) 473 denali->blksperchip)
489 + 474 +
490 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & 475 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
491 MIN_BLK_ADDR_1__VALUE); 476 MIN_BLK_ADDR__VALUE);
492 } else 477 } else
493 denali->fwblks = SPECTRA_START_BLOCK; 478 denali->fwblks = SPECTRA_START_BLOCK;
494 } else 479 } else
@@ -501,7 +486,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
501 uint32_t id_bytes[5], addr; 486 uint32_t id_bytes[5], addr;
502 uint8_t i, maf_id, device_id; 487 uint8_t i, maf_id, device_id;
503 488
504 dev_dbg(&denali->dev->dev, 489 dev_dbg(denali->dev,
505 "%s, Line %d, Function: %s\n", 490 "%s, Line %d, Function: %s\n",
506 __FILE__, __LINE__, __func__); 491 __FILE__, __LINE__, __func__);
507 492
@@ -530,7 +515,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
530 get_hynix_nand_para(denali, device_id); 515 get_hynix_nand_para(denali, device_id);
531 } 516 }
532 517
533 dev_info(&denali->dev->dev, 518 dev_info(denali->dev,
534 "Dump timing register values:" 519 "Dump timing register values:"
535 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" 520 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
536 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" 521 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
@@ -560,7 +545,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
560static void denali_set_intr_modes(struct denali_nand_info *denali, 545static void denali_set_intr_modes(struct denali_nand_info *denali,
561 uint16_t INT_ENABLE) 546 uint16_t INT_ENABLE)
562{ 547{
563 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", 548 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
564 __FILE__, __LINE__, __func__); 549 __FILE__, __LINE__, __func__);
565 550
566 if (INT_ENABLE) 551 if (INT_ENABLE)
@@ -580,6 +565,7 @@ static inline bool is_flash_bank_valid(int flash_bank)
580static void denali_irq_init(struct denali_nand_info *denali) 565static void denali_irq_init(struct denali_nand_info *denali)
581{ 566{
582 uint32_t int_mask = 0; 567 uint32_t int_mask = 0;
568 int i;
583 569
584 /* Disable global interrupts */ 570 /* Disable global interrupts */
585 denali_set_intr_modes(denali, false); 571 denali_set_intr_modes(denali, false);
@@ -587,10 +573,8 @@ static void denali_irq_init(struct denali_nand_info *denali)
587 int_mask = DENALI_IRQ_ALL; 573 int_mask = DENALI_IRQ_ALL;
588 574
589 /* Clear all status bits */ 575 /* Clear all status bits */
590 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0); 576 for (i = 0; i < denali->max_banks; ++i)
591 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1); 577 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
592 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
593 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
594 578
595 denali_irq_enable(denali, int_mask); 579 denali_irq_enable(denali, int_mask);
596} 580}
@@ -604,10 +588,10 @@ static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
604static void denali_irq_enable(struct denali_nand_info *denali, 588static void denali_irq_enable(struct denali_nand_info *denali,
605 uint32_t int_mask) 589 uint32_t int_mask)
606{ 590{
607 iowrite32(int_mask, denali->flash_reg + INTR_EN0); 591 int i;
608 iowrite32(int_mask, denali->flash_reg + INTR_EN1); 592
609 iowrite32(int_mask, denali->flash_reg + INTR_EN2); 593 for (i = 0; i < denali->max_banks; ++i)
610 iowrite32(int_mask, denali->flash_reg + INTR_EN3); 594 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
611} 595}
612 596
613/* This function only returns when an interrupt that this driver cares about 597/* This function only returns when an interrupt that this driver cares about
@@ -624,7 +608,7 @@ static inline void clear_interrupt(struct denali_nand_info *denali,
624{ 608{
625 uint32_t intr_status_reg = 0; 609 uint32_t intr_status_reg = 0;
626 610
627 intr_status_reg = intr_status_addresses[denali->flash_bank]; 611 intr_status_reg = INTR_STATUS(denali->flash_bank);
628 612
629 iowrite32(irq_mask, denali->flash_reg + intr_status_reg); 613 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
630} 614}
@@ -645,7 +629,7 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali)
645{ 629{
646 uint32_t intr_status_reg = 0; 630 uint32_t intr_status_reg = 0;
647 631
648 intr_status_reg = intr_status_addresses[denali->flash_bank]; 632 intr_status_reg = INTR_STATUS(denali->flash_bank);
649 633
650 return ioread32(denali->flash_reg + intr_status_reg); 634 return ioread32(denali->flash_reg + intr_status_reg);
651} 635}
@@ -754,7 +738,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
754 irq_mask = 0; 738 irq_mask = 0;
755 739
756 if (op == DENALI_READ) 740 if (op == DENALI_READ)
757 irq_mask = INTR_STATUS0__LOAD_COMP; 741 irq_mask = INTR_STATUS__LOAD_COMP;
758 else if (op == DENALI_WRITE) 742 else if (op == DENALI_WRITE)
759 irq_mask = 0; 743 irq_mask = 0;
760 else 744 else
@@ -800,7 +784,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
800 irq_status = wait_for_irq(denali, irq_mask); 784 irq_status = wait_for_irq(denali, irq_mask);
801 785
802 if (irq_status == 0) { 786 if (irq_status == 0) {
803 dev_err(&denali->dev->dev, 787 dev_err(denali->dev,
804 "cmd, page, addr on timeout " 788 "cmd, page, addr on timeout "
805 "(0x%x, 0x%x, 0x%x)\n", 789 "(0x%x, 0x%x, 0x%x)\n",
806 cmd, denali->page, addr); 790 cmd, denali->page, addr);
@@ -861,8 +845,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
861{ 845{
862 struct denali_nand_info *denali = mtd_to_denali(mtd); 846 struct denali_nand_info *denali = mtd_to_denali(mtd);
863 uint32_t irq_status = 0; 847 uint32_t irq_status = 0;
864 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | 848 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
865 INTR_STATUS0__PROGRAM_FAIL; 849 INTR_STATUS__PROGRAM_FAIL;
866 int status = 0; 850 int status = 0;
867 851
868 denali->page = page; 852 denali->page = page;
@@ -875,11 +859,11 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
875 irq_status = wait_for_irq(denali, irq_mask); 859 irq_status = wait_for_irq(denali, irq_mask);
876 860
877 if (irq_status == 0) { 861 if (irq_status == 0) {
878 dev_err(&denali->dev->dev, "OOB write failed\n"); 862 dev_err(denali->dev, "OOB write failed\n");
879 status = -EIO; 863 status = -EIO;
880 } 864 }
881 } else { 865 } else {
882 dev_err(&denali->dev->dev, "unable to send pipeline command\n"); 866 dev_err(denali->dev, "unable to send pipeline command\n");
883 status = -EIO; 867 status = -EIO;
884 } 868 }
885 return status; 869 return status;
@@ -889,7 +873,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
889static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) 873static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
890{ 874{
891 struct denali_nand_info *denali = mtd_to_denali(mtd); 875 struct denali_nand_info *denali = mtd_to_denali(mtd);
892 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, 876 uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
893 irq_status = 0, addr = 0x0, cmd = 0x0; 877 irq_status = 0, addr = 0x0, cmd = 0x0;
894 878
895 denali->page = page; 879 denali->page = page;
@@ -904,7 +888,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
904 irq_status = wait_for_irq(denali, irq_mask); 888 irq_status = wait_for_irq(denali, irq_mask);
905 889
906 if (irq_status == 0) 890 if (irq_status == 0)
907 dev_err(&denali->dev->dev, "page on OOB timeout %d\n", 891 dev_err(denali->dev, "page on OOB timeout %d\n",
908 denali->page); 892 denali->page);
909 893
910 /* We set the device back to MAIN_ACCESS here as I observed 894 /* We set the device back to MAIN_ACCESS here as I observed
@@ -944,7 +928,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
944{ 928{
945 bool check_erased_page = false; 929 bool check_erased_page = false;
946 930
947 if (irq_status & INTR_STATUS0__ECC_ERR) { 931 if (irq_status & INTR_STATUS__ECC_ERR) {
948 /* read the ECC errors. we'll ignore them for now */ 932 /* read the ECC errors. we'll ignore them for now */
949 uint32_t err_address = 0, err_correction_info = 0; 933 uint32_t err_address = 0, err_correction_info = 0;
950 uint32_t err_byte = 0, err_sector = 0, err_device = 0; 934 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
@@ -995,7 +979,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
995 * for a while for this interrupt 979 * for a while for this interrupt
996 * */ 980 * */
997 while (!(read_interrupt_status(denali) & 981 while (!(read_interrupt_status(denali) &
998 INTR_STATUS0__ECC_TRANSACTION_DONE)) 982 INTR_STATUS__ECC_TRANSACTION_DONE))
999 cpu_relax(); 983 cpu_relax();
1000 clear_interrupts(denali); 984 clear_interrupts(denali);
1001 denali_set_intr_modes(denali, true); 985 denali_set_intr_modes(denali, true);
@@ -1045,14 +1029,13 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1045 const uint8_t *buf, bool raw_xfer) 1029 const uint8_t *buf, bool raw_xfer)
1046{ 1030{
1047 struct denali_nand_info *denali = mtd_to_denali(mtd); 1031 struct denali_nand_info *denali = mtd_to_denali(mtd);
1048 struct pci_dev *pci_dev = denali->dev;
1049 1032
1050 dma_addr_t addr = denali->buf.dma_buf; 1033 dma_addr_t addr = denali->buf.dma_buf;
1051 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1034 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1052 1035
1053 uint32_t irq_status = 0; 1036 uint32_t irq_status = 0;
1054 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | 1037 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1055 INTR_STATUS0__PROGRAM_FAIL; 1038 INTR_STATUS__PROGRAM_FAIL;
1056 1039
1057 /* if it is a raw xfer, we want to disable ecc, and send 1040 /* if it is a raw xfer, we want to disable ecc, and send
1058 * the spare area. 1041 * the spare area.
@@ -1071,7 +1054,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1071 mtd->oobsize); 1054 mtd->oobsize);
1072 } 1055 }
1073 1056
1074 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); 1057 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1075 1058
1076 clear_interrupts(denali); 1059 clear_interrupts(denali);
1077 denali_enable_dma(denali, true); 1060 denali_enable_dma(denali, true);
@@ -1082,16 +1065,16 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1082 irq_status = wait_for_irq(denali, irq_mask); 1065 irq_status = wait_for_irq(denali, irq_mask);
1083 1066
1084 if (irq_status == 0) { 1067 if (irq_status == 0) {
1085 dev_err(&denali->dev->dev, 1068 dev_err(denali->dev,
1086 "timeout on write_page (type = %d)\n", 1069 "timeout on write_page (type = %d)\n",
1087 raw_xfer); 1070 raw_xfer);
1088 denali->status = 1071 denali->status =
1089 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? 1072 (irq_status & INTR_STATUS__PROGRAM_FAIL) ?
1090 NAND_STATUS_FAIL : PASS; 1073 NAND_STATUS_FAIL : PASS;
1091 } 1074 }
1092 1075
1093 denali_enable_dma(denali, false); 1076 denali_enable_dma(denali, false);
1094 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); 1077 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1095} 1078}
1096 1079
1097/* NAND core entry points */ 1080/* NAND core entry points */
@@ -1139,18 +1122,17 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1139 uint8_t *buf, int page) 1122 uint8_t *buf, int page)
1140{ 1123{
1141 struct denali_nand_info *denali = mtd_to_denali(mtd); 1124 struct denali_nand_info *denali = mtd_to_denali(mtd);
1142 struct pci_dev *pci_dev = denali->dev;
1143 1125
1144 dma_addr_t addr = denali->buf.dma_buf; 1126 dma_addr_t addr = denali->buf.dma_buf;
1145 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1127 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1146 1128
1147 uint32_t irq_status = 0; 1129 uint32_t irq_status = 0;
1148 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | 1130 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1149 INTR_STATUS0__ECC_ERR; 1131 INTR_STATUS__ECC_ERR;
1150 bool check_erased_page = false; 1132 bool check_erased_page = false;
1151 1133
1152 if (page != denali->page) { 1134 if (page != denali->page) {
1153 dev_err(&denali->dev->dev, "IN %s: page %d is not" 1135 dev_err(denali->dev, "IN %s: page %d is not"
1154 " equal to denali->page %d, investigate!!", 1136 " equal to denali->page %d, investigate!!",
1155 __func__, page, denali->page); 1137 __func__, page, denali->page);
1156 BUG(); 1138 BUG();
@@ -1159,7 +1141,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1159 setup_ecc_for_xfer(denali, true, false); 1141 setup_ecc_for_xfer(denali, true, false);
1160 1142
1161 denali_enable_dma(denali, true); 1143 denali_enable_dma(denali, true);
1162 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1144 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1163 1145
1164 clear_interrupts(denali); 1146 clear_interrupts(denali);
1165 denali_setup_dma(denali, DENALI_READ); 1147 denali_setup_dma(denali, DENALI_READ);
@@ -1167,7 +1149,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1167 /* wait for operation to complete */ 1149 /* wait for operation to complete */
1168 irq_status = wait_for_irq(denali, irq_mask); 1150 irq_status = wait_for_irq(denali, irq_mask);
1169 1151
1170 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1152 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1171 1153
1172 memcpy(buf, denali->buf.buf, mtd->writesize); 1154 memcpy(buf, denali->buf.buf, mtd->writesize);
1173 1155
@@ -1192,16 +1174,15 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1192 uint8_t *buf, int page) 1174 uint8_t *buf, int page)
1193{ 1175{
1194 struct denali_nand_info *denali = mtd_to_denali(mtd); 1176 struct denali_nand_info *denali = mtd_to_denali(mtd);
1195 struct pci_dev *pci_dev = denali->dev;
1196 1177
1197 dma_addr_t addr = denali->buf.dma_buf; 1178 dma_addr_t addr = denali->buf.dma_buf;
1198 size_t size = denali->mtd.writesize + denali->mtd.oobsize; 1179 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1199 1180
1200 uint32_t irq_status = 0; 1181 uint32_t irq_status = 0;
1201 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; 1182 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1202 1183
1203 if (page != denali->page) { 1184 if (page != denali->page) {
1204 dev_err(&denali->dev->dev, "IN %s: page %d is not" 1185 dev_err(denali->dev, "IN %s: page %d is not"
1205 " equal to denali->page %d, investigate!!", 1186 " equal to denali->page %d, investigate!!",
1206 __func__, page, denali->page); 1187 __func__, page, denali->page);
1207 BUG(); 1188 BUG();
@@ -1210,7 +1191,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1210 setup_ecc_for_xfer(denali, false, true); 1191 setup_ecc_for_xfer(denali, false, true);
1211 denali_enable_dma(denali, true); 1192 denali_enable_dma(denali, true);
1212 1193
1213 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1194 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1214 1195
1215 clear_interrupts(denali); 1196 clear_interrupts(denali);
1216 denali_setup_dma(denali, DENALI_READ); 1197 denali_setup_dma(denali, DENALI_READ);
@@ -1218,7 +1199,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1218 /* wait for operation to complete */ 1199 /* wait for operation to complete */
1219 irq_status = wait_for_irq(denali, irq_mask); 1200 irq_status = wait_for_irq(denali, irq_mask);
1220 1201
1221 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); 1202 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1222 1203
1223 denali_enable_dma(denali, false); 1204 denali_enable_dma(denali, false);
1224 1205
@@ -1271,10 +1252,10 @@ static void denali_erase(struct mtd_info *mtd, int page)
1271 index_addr(denali, (uint32_t)cmd, 0x1); 1252 index_addr(denali, (uint32_t)cmd, 0x1);
1272 1253
1273 /* wait for erase to complete or failure to occur */ 1254 /* wait for erase to complete or failure to occur */
1274 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | 1255 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1275 INTR_STATUS0__ERASE_FAIL); 1256 INTR_STATUS__ERASE_FAIL);
1276 1257
1277 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? 1258 denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ?
1278 NAND_STATUS_FAIL : PASS; 1259 NAND_STATUS_FAIL : PASS;
1279} 1260}
1280 1261
@@ -1330,7 +1311,7 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1330 uint8_t *ecc_code) 1311 uint8_t *ecc_code)
1331{ 1312{
1332 struct denali_nand_info *denali = mtd_to_denali(mtd); 1313 struct denali_nand_info *denali = mtd_to_denali(mtd);
1333 dev_err(&denali->dev->dev, 1314 dev_err(denali->dev,
1334 "denali_ecc_calculate called unexpectedly\n"); 1315 "denali_ecc_calculate called unexpectedly\n");
1335 BUG(); 1316 BUG();
1336 return -EIO; 1317 return -EIO;
@@ -1340,7 +1321,7 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1340 uint8_t *read_ecc, uint8_t *calc_ecc) 1321 uint8_t *read_ecc, uint8_t *calc_ecc)
1341{ 1322{
1342 struct denali_nand_info *denali = mtd_to_denali(mtd); 1323 struct denali_nand_info *denali = mtd_to_denali(mtd);
1343 dev_err(&denali->dev->dev, 1324 dev_err(denali->dev,
1344 "denali_ecc_correct called unexpectedly\n"); 1325 "denali_ecc_correct called unexpectedly\n");
1345 BUG(); 1326 BUG();
1346 return -EIO; 1327 return -EIO;
@@ -1349,7 +1330,7 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1349static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) 1330static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1350{ 1331{
1351 struct denali_nand_info *denali = mtd_to_denali(mtd); 1332 struct denali_nand_info *denali = mtd_to_denali(mtd);
1352 dev_err(&denali->dev->dev, 1333 dev_err(denali->dev,
1353 "denali_ecc_hwctl called unexpectedly\n"); 1334 "denali_ecc_hwctl called unexpectedly\n");
1354 BUG(); 1335 BUG();
1355} 1336}
@@ -1375,6 +1356,7 @@ static void denali_hw_init(struct denali_nand_info *denali)
1375 /* Should set value for these registers when init */ 1356 /* Should set value for these registers when init */
1376 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); 1357 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1377 iowrite32(1, denali->flash_reg + ECC_ENABLE); 1358 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1359 detect_max_banks(denali);
1378 denali_nand_timing_set(denali); 1360 denali_nand_timing_set(denali);
1379 denali_irq_init(denali); 1361 denali_irq_init(denali);
1380} 1362}
@@ -1484,24 +1466,22 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1484 } 1466 }
1485 1467
1486 /* Is 32-bit DMA supported? */ 1468 /* Is 32-bit DMA supported? */
1487 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32)); 1469 ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
1488
1489 if (ret) { 1470 if (ret) {
1490 printk(KERN_ERR "Spectra: no usable DMA configuration\n"); 1471 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1491 goto failed_enable_dev; 1472 goto failed_enable_dev;
1492 } 1473 }
1493 denali->buf.dma_buf = 1474 denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf,
1494 pci_map_single(dev, denali->buf.buf, 1475 DENALI_BUF_SIZE,
1495 DENALI_BUF_SIZE, 1476 DMA_BIDIRECTIONAL);
1496 PCI_DMA_BIDIRECTIONAL);
1497 1477
1498 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { 1478 if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) {
1499 dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n"); 1479 dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
1500 goto failed_enable_dev; 1480 goto failed_enable_dev;
1501 } 1481 }
1502 1482
1503 pci_set_master(dev); 1483 pci_set_master(dev);
1504 denali->dev = dev; 1484 denali->dev = &dev->dev;
1505 denali->mtd.dev.parent = &dev->dev; 1485 denali->mtd.dev.parent = &dev->dev;
1506 1486
1507 ret = pci_request_regions(dev, DENALI_NAND_NAME); 1487 ret = pci_request_regions(dev, DENALI_NAND_NAME);
@@ -1554,7 +1534,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1554 /* scan for NAND devices attached to the controller 1534 /* scan for NAND devices attached to the controller
1555 * this is the first stage in a two step process to register 1535 * this is the first stage in a two step process to register
1556 * with the nand subsystem */ 1536 * with the nand subsystem */
1557 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) { 1537 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1558 ret = -ENXIO; 1538 ret = -ENXIO;
1559 goto failed_req_irq; 1539 goto failed_req_irq;
1560 } 1540 }
@@ -1664,7 +1644,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1664 goto failed_req_irq; 1644 goto failed_req_irq;
1665 } 1645 }
1666 1646
1667 ret = add_mtd_device(&denali->mtd); 1647 ret = mtd_device_register(&denali->mtd, NULL, 0);
1668 if (ret) { 1648 if (ret) {
1669 dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n", 1649 dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
1670 ret); 1650 ret);
@@ -1681,8 +1661,8 @@ failed_remap_reg:
1681failed_req_regions: 1661failed_req_regions:
1682 pci_release_regions(dev); 1662 pci_release_regions(dev);
1683failed_dma_map: 1663failed_dma_map:
1684 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 1664 dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1685 PCI_DMA_BIDIRECTIONAL); 1665 DMA_BIDIRECTIONAL);
1686failed_enable_dev: 1666failed_enable_dev:
1687 pci_disable_device(dev); 1667 pci_disable_device(dev);
1688failed_alloc_memery: 1668failed_alloc_memery:
@@ -1696,7 +1676,7 @@ static void denali_pci_remove(struct pci_dev *dev)
1696 struct denali_nand_info *denali = pci_get_drvdata(dev); 1676 struct denali_nand_info *denali = pci_get_drvdata(dev);
1697 1677
1698 nand_release(&denali->mtd); 1678 nand_release(&denali->mtd);
1699 del_mtd_device(&denali->mtd); 1679 mtd_device_unregister(&denali->mtd);
1700 1680
1701 denali_irq_cleanup(dev->irq, denali); 1681 denali_irq_cleanup(dev->irq, denali);
1702 1682
@@ -1704,8 +1684,8 @@ static void denali_pci_remove(struct pci_dev *dev)
1704 iounmap(denali->flash_mem); 1684 iounmap(denali->flash_mem);
1705 pci_release_regions(dev); 1685 pci_release_regions(dev);
1706 pci_disable_device(dev); 1686 pci_disable_device(dev);
1707 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, 1687 dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1708 PCI_DMA_BIDIRECTIONAL); 1688 DMA_BIDIRECTIONAL);
1709 pci_set_drvdata(dev, NULL); 1689 pci_set_drvdata(dev, NULL);
1710 kfree(denali); 1690 kfree(denali);
1711} 1691}
@@ -1721,8 +1701,7 @@ static struct pci_driver denali_pci_driver = {
1721 1701
1722static int __devinit denali_init(void) 1702static int __devinit denali_init(void)
1723{ 1703{
1724 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n", 1704 printk(KERN_INFO "Spectra MTD driver\n");
1725 __DATE__, __TIME__);
1726 return pci_register_driver(&denali_pci_driver); 1705 return pci_register_driver(&denali_pci_driver);
1727} 1706}
1728 1707