diff options
Diffstat (limited to 'drivers/mtd/nand/davinci_nand.c')
-rw-r--r-- | drivers/mtd/nand/davinci_nand.c | 342 |
1 files changed, 302 insertions, 40 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 02700f769b8a..0fad6487e6f4 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c | |||
@@ -44,7 +44,7 @@ | |||
44 | * and some flavors of secondary chipselect (e.g. based on A12) as used | 44 | * and some flavors of secondary chipselect (e.g. based on A12) as used |
45 | * with multichip packages. | 45 | * with multichip packages. |
46 | * | 46 | * |
47 | * The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC | 47 | * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC |
48 | * available on chips like the DM355 and OMAP-L137 and needed with the | 48 | * available on chips like the DM355 and OMAP-L137 and needed with the |
49 | * more error-prone MLC NAND chips. | 49 | * more error-prone MLC NAND chips. |
50 | * | 50 | * |
@@ -54,11 +54,14 @@ | |||
54 | struct davinci_nand_info { | 54 | struct davinci_nand_info { |
55 | struct mtd_info mtd; | 55 | struct mtd_info mtd; |
56 | struct nand_chip chip; | 56 | struct nand_chip chip; |
57 | struct nand_ecclayout ecclayout; | ||
57 | 58 | ||
58 | struct device *dev; | 59 | struct device *dev; |
59 | struct clk *clk; | 60 | struct clk *clk; |
60 | bool partitioned; | 61 | bool partitioned; |
61 | 62 | ||
63 | bool is_readmode; | ||
64 | |||
62 | void __iomem *base; | 65 | void __iomem *base; |
63 | void __iomem *vaddr; | 66 | void __iomem *vaddr; |
64 | 67 | ||
@@ -73,6 +76,7 @@ struct davinci_nand_info { | |||
73 | }; | 76 | }; |
74 | 77 | ||
75 | static DEFINE_SPINLOCK(davinci_nand_lock); | 78 | static DEFINE_SPINLOCK(davinci_nand_lock); |
79 | static bool ecc4_busy; | ||
76 | 80 | ||
77 | #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) | 81 | #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) |
78 | 82 | ||
@@ -218,6 +222,192 @@ static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, | |||
218 | /*----------------------------------------------------------------------*/ | 222 | /*----------------------------------------------------------------------*/ |
219 | 223 | ||
220 | /* | 224 | /* |
225 | * 4-bit hardware ECC ... context maintained over entire AEMIF | ||
226 | * | ||
227 | * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME | ||
228 | * since that forces use of a problematic "infix OOB" layout. | ||
229 | * Among other things, it trashes manufacturer bad block markers. | ||
230 | * Also, and specific to this hardware, it ECC-protects the "prepad" | ||
231 | * in the OOB ... while having ECC protection for parts of OOB would | ||
232 | * seem useful, the current MTD stack sometimes wants to update the | ||
233 | * OOB without recomputing ECC. | ||
234 | */ | ||
235 | |||
236 | static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) | ||
237 | { | ||
238 | struct davinci_nand_info *info = to_davinci_nand(mtd); | ||
239 | unsigned long flags; | ||
240 | u32 val; | ||
241 | |||
242 | spin_lock_irqsave(&davinci_nand_lock, flags); | ||
243 | |||
244 | /* Start 4-bit ECC calculation for read/write */ | ||
245 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | ||
246 | val &= ~(0x03 << 4); | ||
247 | val |= (info->core_chipsel << 4) | BIT(12); | ||
248 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | ||
249 | |||
250 | info->is_readmode = (mode == NAND_ECC_READ); | ||
251 | |||
252 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | ||
253 | } | ||
254 | |||
255 | /* Read raw ECC code after writing to NAND. */ | ||
256 | static void | ||
257 | nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) | ||
258 | { | ||
259 | const u32 mask = 0x03ff03ff; | ||
260 | |||
261 | code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; | ||
262 | code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; | ||
263 | code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; | ||
264 | code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; | ||
265 | } | ||
266 | |||
267 | /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ | ||
268 | static int nand_davinci_calculate_4bit(struct mtd_info *mtd, | ||
269 | const u_char *dat, u_char *ecc_code) | ||
270 | { | ||
271 | struct davinci_nand_info *info = to_davinci_nand(mtd); | ||
272 | u32 raw_ecc[4], *p; | ||
273 | unsigned i; | ||
274 | |||
275 | /* After a read, terminate ECC calculation by a dummy read | ||
276 | * of some 4-bit ECC register. ECC covers everything that | ||
277 | * was read; correct() just uses the hardware state, so | ||
278 | * ecc_code is not needed. | ||
279 | */ | ||
280 | if (info->is_readmode) { | ||
281 | davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); | ||
282 | return 0; | ||
283 | } | ||
284 | |||
285 | /* Pack eight raw 10-bit ecc values into ten bytes, making | ||
286 | * two passes which each convert four values (in upper and | ||
287 | * lower halves of two 32-bit words) into five bytes. The | ||
288 | * ROM boot loader uses this same packing scheme. | ||
289 | */ | ||
290 | nand_davinci_readecc_4bit(info, raw_ecc); | ||
291 | for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { | ||
292 | *ecc_code++ = p[0] & 0xff; | ||
293 | *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); | ||
294 | *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); | ||
295 | *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); | ||
296 | *ecc_code++ = (p[1] >> 18) & 0xff; | ||
297 | } | ||
298 | |||
299 | return 0; | ||
300 | } | ||
301 | |||
302 | /* Correct up to 4 bits in data we just read, using state left in the | ||
303 | * hardware plus the ecc_code computed when it was first written. | ||
304 | */ | ||
305 | static int nand_davinci_correct_4bit(struct mtd_info *mtd, | ||
306 | u_char *data, u_char *ecc_code, u_char *null) | ||
307 | { | ||
308 | int i; | ||
309 | struct davinci_nand_info *info = to_davinci_nand(mtd); | ||
310 | unsigned short ecc10[8]; | ||
311 | unsigned short *ecc16; | ||
312 | u32 syndrome[4]; | ||
313 | unsigned num_errors, corrected; | ||
314 | |||
315 | /* All bytes 0xff? It's an erased page; ignore its ECC. */ | ||
316 | for (i = 0; i < 10; i++) { | ||
317 | if (ecc_code[i] != 0xff) | ||
318 | goto compare; | ||
319 | } | ||
320 | return 0; | ||
321 | |||
322 | compare: | ||
323 | /* Unpack ten bytes into eight 10 bit values. We know we're | ||
324 | * little-endian, and use type punning for less shifting/masking. | ||
325 | */ | ||
326 | if (WARN_ON(0x01 & (unsigned) ecc_code)) | ||
327 | return -EINVAL; | ||
328 | ecc16 = (unsigned short *)ecc_code; | ||
329 | |||
330 | ecc10[0] = (ecc16[0] >> 0) & 0x3ff; | ||
331 | ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); | ||
332 | ecc10[2] = (ecc16[1] >> 4) & 0x3ff; | ||
333 | ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); | ||
334 | ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); | ||
335 | ecc10[5] = (ecc16[3] >> 2) & 0x3ff; | ||
336 | ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); | ||
337 | ecc10[7] = (ecc16[4] >> 6) & 0x3ff; | ||
338 | |||
339 | /* Tell ECC controller about the expected ECC codes. */ | ||
340 | for (i = 7; i >= 0; i--) | ||
341 | davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); | ||
342 | |||
343 | /* Allow time for syndrome calculation ... then read it. | ||
344 | * A syndrome of all zeroes 0 means no detected errors. | ||
345 | */ | ||
346 | davinci_nand_readl(info, NANDFSR_OFFSET); | ||
347 | nand_davinci_readecc_4bit(info, syndrome); | ||
348 | if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) | ||
349 | return 0; | ||
350 | |||
351 | /* Start address calculation, and wait for it to complete. | ||
352 | * We _could_ start reading more data while this is working, | ||
353 | * to speed up the overall page read. | ||
354 | */ | ||
355 | davinci_nand_writel(info, NANDFCR_OFFSET, | ||
356 | davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); | ||
357 | for (;;) { | ||
358 | u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); | ||
359 | |||
360 | switch ((fsr >> 8) & 0x0f) { | ||
361 | case 0: /* no error, should not happen */ | ||
362 | return 0; | ||
363 | case 1: /* five or more errors detected */ | ||
364 | return -EIO; | ||
365 | case 2: /* error addresses computed */ | ||
366 | case 3: | ||
367 | num_errors = 1 + ((fsr >> 16) & 0x03); | ||
368 | goto correct; | ||
369 | default: /* still working on it */ | ||
370 | cpu_relax(); | ||
371 | continue; | ||
372 | } | ||
373 | } | ||
374 | |||
375 | correct: | ||
376 | /* correct each error */ | ||
377 | for (i = 0, corrected = 0; i < num_errors; i++) { | ||
378 | int error_address, error_value; | ||
379 | |||
380 | if (i > 1) { | ||
381 | error_address = davinci_nand_readl(info, | ||
382 | NAND_ERR_ADD2_OFFSET); | ||
383 | error_value = davinci_nand_readl(info, | ||
384 | NAND_ERR_ERRVAL2_OFFSET); | ||
385 | } else { | ||
386 | error_address = davinci_nand_readl(info, | ||
387 | NAND_ERR_ADD1_OFFSET); | ||
388 | error_value = davinci_nand_readl(info, | ||
389 | NAND_ERR_ERRVAL1_OFFSET); | ||
390 | } | ||
391 | |||
392 | if (i & 1) { | ||
393 | error_address >>= 16; | ||
394 | error_value >>= 16; | ||
395 | } | ||
396 | error_address &= 0x3ff; | ||
397 | error_address = (512 + 7) - error_address; | ||
398 | |||
399 | if (error_address < 512) { | ||
400 | data[error_address] ^= error_value; | ||
401 | corrected++; | ||
402 | } | ||
403 | } | ||
404 | |||
405 | return corrected; | ||
406 | } | ||
407 | |||
408 | /*----------------------------------------------------------------------*/ | ||
409 | |||
410 | /* | ||
221 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's | 411 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's |
222 | * how these chips are normally wired. This translates to both 8 and 16 | 412 | * how these chips are normally wired. This translates to both 8 and 16 |
223 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). | 413 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). |
@@ -294,6 +484,23 @@ static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) | |||
294 | 484 | ||
295 | /*----------------------------------------------------------------------*/ | 485 | /*----------------------------------------------------------------------*/ |
296 | 486 | ||
487 | /* An ECC layout for using 4-bit ECC with small-page flash, storing | ||
488 | * ten ECC bytes plus the manufacturer's bad block marker byte, and | ||
489 | * and not overlapping the default BBT markers. | ||
490 | */ | ||
491 | static struct nand_ecclayout hwecc4_small __initconst = { | ||
492 | .eccbytes = 10, | ||
493 | .eccpos = { 0, 1, 2, 3, 4, | ||
494 | /* offset 5 holds the badblock marker */ | ||
495 | 6, 7, | ||
496 | 13, 14, 15, }, | ||
497 | .oobfree = { | ||
498 | {.offset = 8, .length = 5, }, | ||
499 | {.offset = 16, }, | ||
500 | }, | ||
501 | }; | ||
502 | |||
503 | |||
297 | static int __init nand_davinci_probe(struct platform_device *pdev) | 504 | static int __init nand_davinci_probe(struct platform_device *pdev) |
298 | { | 505 | { |
299 | struct davinci_nand_pdata *pdata = pdev->dev.platform_data; | 506 | struct davinci_nand_pdata *pdata = pdev->dev.platform_data; |
@@ -306,6 +513,10 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
306 | uint32_t val; | 513 | uint32_t val; |
307 | nand_ecc_modes_t ecc_mode; | 514 | nand_ecc_modes_t ecc_mode; |
308 | 515 | ||
516 | /* insist on board-specific configuration */ | ||
517 | if (!pdata) | ||
518 | return -ENODEV; | ||
519 | |||
309 | /* which external chipselect will we be managing? */ | 520 | /* which external chipselect will we be managing? */ |
310 | if (pdev->id < 0 || pdev->id > 3) | 521 | if (pdev->id < 0 || pdev->id > 3) |
311 | return -ENODEV; | 522 | return -ENODEV; |
@@ -351,7 +562,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
351 | info->chip.select_chip = nand_davinci_select_chip; | 562 | info->chip.select_chip = nand_davinci_select_chip; |
352 | 563 | ||
353 | /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ | 564 | /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ |
354 | info->chip.options = pdata ? pdata->options : 0; | 565 | info->chip.options = pdata->options; |
355 | 566 | ||
356 | info->ioaddr = (uint32_t __force) vaddr; | 567 | info->ioaddr = (uint32_t __force) vaddr; |
357 | 568 | ||
@@ -360,14 +571,8 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
360 | info->mask_chipsel = pdata->mask_chipsel; | 571 | info->mask_chipsel = pdata->mask_chipsel; |
361 | 572 | ||
362 | /* use nandboot-capable ALE/CLE masks by default */ | 573 | /* use nandboot-capable ALE/CLE masks by default */ |
363 | if (pdata && pdata->mask_ale) | 574 | info->mask_ale = pdata->mask_cle ? : MASK_ALE; |
364 | info->mask_ale = pdata->mask_cle; | 575 | info->mask_cle = pdata->mask_cle ? : MASK_CLE; |
365 | else | ||
366 | info->mask_ale = MASK_ALE; | ||
367 | if (pdata && pdata->mask_cle) | ||
368 | info->mask_cle = pdata->mask_cle; | ||
369 | else | ||
370 | info->mask_cle = MASK_CLE; | ||
371 | 576 | ||
372 | /* Set address of hardware control function */ | 577 | /* Set address of hardware control function */ |
373 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; | 578 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; |
@@ -377,30 +582,44 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
377 | info->chip.read_buf = nand_davinci_read_buf; | 582 | info->chip.read_buf = nand_davinci_read_buf; |
378 | info->chip.write_buf = nand_davinci_write_buf; | 583 | info->chip.write_buf = nand_davinci_write_buf; |
379 | 584 | ||
380 | /* use board-specific ECC config; else, the best available */ | 585 | /* Use board-specific ECC config */ |
381 | if (pdata) | 586 | ecc_mode = pdata->ecc_mode; |
382 | ecc_mode = pdata->ecc_mode; | ||
383 | else | ||
384 | ecc_mode = NAND_ECC_HW; | ||
385 | 587 | ||
588 | ret = -EINVAL; | ||
386 | switch (ecc_mode) { | 589 | switch (ecc_mode) { |
387 | case NAND_ECC_NONE: | 590 | case NAND_ECC_NONE: |
388 | case NAND_ECC_SOFT: | 591 | case NAND_ECC_SOFT: |
592 | pdata->ecc_bits = 0; | ||
389 | break; | 593 | break; |
390 | case NAND_ECC_HW: | 594 | case NAND_ECC_HW: |
391 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | 595 | if (pdata->ecc_bits == 4) { |
392 | info->chip.ecc.correct = nand_davinci_correct_1bit; | 596 | /* No sanity checks: CPUs must support this, |
393 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | 597 | * and the chips may not use NAND_BUSWIDTH_16. |
598 | */ | ||
599 | |||
600 | /* No sharing 4-bit hardware between chipselects yet */ | ||
601 | spin_lock_irq(&davinci_nand_lock); | ||
602 | if (ecc4_busy) | ||
603 | ret = -EBUSY; | ||
604 | else | ||
605 | ecc4_busy = true; | ||
606 | spin_unlock_irq(&davinci_nand_lock); | ||
607 | |||
608 | if (ret == -EBUSY) | ||
609 | goto err_ecc; | ||
610 | |||
611 | info->chip.ecc.calculate = nand_davinci_calculate_4bit; | ||
612 | info->chip.ecc.correct = nand_davinci_correct_4bit; | ||
613 | info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; | ||
614 | info->chip.ecc.bytes = 10; | ||
615 | } else { | ||
616 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | ||
617 | info->chip.ecc.correct = nand_davinci_correct_1bit; | ||
618 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | ||
619 | info->chip.ecc.bytes = 3; | ||
620 | } | ||
394 | info->chip.ecc.size = 512; | 621 | info->chip.ecc.size = 512; |
395 | info->chip.ecc.bytes = 3; | ||
396 | break; | 622 | break; |
397 | case NAND_ECC_HW_SYNDROME: | ||
398 | /* FIXME implement */ | ||
399 | info->chip.ecc.size = 512; | ||
400 | info->chip.ecc.bytes = 10; | ||
401 | |||
402 | dev_warn(&pdev->dev, "4-bit ECC nyet supported\n"); | ||
403 | /* FALL THROUGH */ | ||
404 | default: | 623 | default: |
405 | ret = -EINVAL; | 624 | ret = -EINVAL; |
406 | goto err_ecc; | 625 | goto err_ecc; |
@@ -441,12 +660,56 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
441 | spin_unlock_irq(&davinci_nand_lock); | 660 | spin_unlock_irq(&davinci_nand_lock); |
442 | 661 | ||
443 | /* Scan to find existence of the device(s) */ | 662 | /* Scan to find existence of the device(s) */ |
444 | ret = nand_scan(&info->mtd, pdata->mask_chipsel ? 2 : 1); | 663 | ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1); |
445 | if (ret < 0) { | 664 | if (ret < 0) { |
446 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); | 665 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); |
447 | goto err_scan; | 666 | goto err_scan; |
448 | } | 667 | } |
449 | 668 | ||
669 | /* Update ECC layout if needed ... for 1-bit HW ECC, the default | ||
670 | * is OK, but it allocates 6 bytes when only 3 are needed (for | ||
671 | * each 512 bytes). For the 4-bit HW ECC, that default is not | ||
672 | * usable: 10 bytes are needed, not 6. | ||
673 | */ | ||
674 | if (pdata->ecc_bits == 4) { | ||
675 | int chunks = info->mtd.writesize / 512; | ||
676 | |||
677 | if (!chunks || info->mtd.oobsize < 16) { | ||
678 | dev_dbg(&pdev->dev, "too small\n"); | ||
679 | ret = -EINVAL; | ||
680 | goto err_scan; | ||
681 | } | ||
682 | |||
683 | /* For small page chips, preserve the manufacturer's | ||
684 | * badblock marking data ... and make sure a flash BBT | ||
685 | * table marker fits in the free bytes. | ||
686 | */ | ||
687 | if (chunks == 1) { | ||
688 | info->ecclayout = hwecc4_small; | ||
689 | info->ecclayout.oobfree[1].length = | ||
690 | info->mtd.oobsize - 16; | ||
691 | goto syndrome_done; | ||
692 | } | ||
693 | |||
694 | /* For large page chips we'll be wanting to use a | ||
695 | * not-yet-implemented mode that reads OOB data | ||
696 | * before reading the body of the page, to avoid | ||
697 | * the "infix OOB" model of NAND_ECC_HW_SYNDROME | ||
698 | * (and preserve manufacturer badblock markings). | ||
699 | */ | ||
700 | dev_warn(&pdev->dev, "no 4-bit ECC support yet " | ||
701 | "for large page NAND\n"); | ||
702 | ret = -EIO; | ||
703 | goto err_scan; | ||
704 | |||
705 | syndrome_done: | ||
706 | info->chip.ecc.layout = &info->ecclayout; | ||
707 | } | ||
708 | |||
709 | ret = nand_scan_tail(&info->mtd); | ||
710 | if (ret < 0) | ||
711 | goto err_scan; | ||
712 | |||
450 | if (mtd_has_partitions()) { | 713 | if (mtd_has_partitions()) { |
451 | struct mtd_partition *mtd_parts = NULL; | 714 | struct mtd_partition *mtd_parts = NULL; |
452 | int mtd_parts_nb = 0; | 715 | int mtd_parts_nb = 0; |
@@ -455,22 +718,11 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
455 | static const char *probes[] __initconst = | 718 | static const char *probes[] __initconst = |
456 | { "cmdlinepart", NULL }; | 719 | { "cmdlinepart", NULL }; |
457 | 720 | ||
458 | const char *master_name; | ||
459 | |||
460 | /* Set info->mtd.name = 0 temporarily */ | ||
461 | master_name = info->mtd.name; | ||
462 | info->mtd.name = (char *)0; | ||
463 | |||
464 | /* info->mtd.name == 0, means: don't bother checking | ||
465 | <mtd-id> */ | ||
466 | mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, | 721 | mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, |
467 | &mtd_parts, 0); | 722 | &mtd_parts, 0); |
468 | |||
469 | /* Restore info->mtd.name */ | ||
470 | info->mtd.name = master_name; | ||
471 | } | 723 | } |
472 | 724 | ||
473 | if (mtd_parts_nb <= 0 && pdata) { | 725 | if (mtd_parts_nb <= 0) { |
474 | mtd_parts = pdata->parts; | 726 | mtd_parts = pdata->parts; |
475 | mtd_parts_nb = pdata->nr_parts; | 727 | mtd_parts_nb = pdata->nr_parts; |
476 | } | 728 | } |
@@ -483,7 +735,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) | |||
483 | info->partitioned = true; | 735 | info->partitioned = true; |
484 | } | 736 | } |
485 | 737 | ||
486 | } else if (pdata && pdata->nr_parts) { | 738 | } else if (pdata->nr_parts) { |
487 | dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", | 739 | dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", |
488 | pdata->nr_parts, info->mtd.name); | 740 | pdata->nr_parts, info->mtd.name); |
489 | } | 741 | } |
@@ -509,6 +761,11 @@ err_scan: | |||
509 | err_clk_enable: | 761 | err_clk_enable: |
510 | clk_put(info->clk); | 762 | clk_put(info->clk); |
511 | 763 | ||
764 | spin_lock_irq(&davinci_nand_lock); | ||
765 | if (ecc_mode == NAND_ECC_HW_SYNDROME) | ||
766 | ecc4_busy = false; | ||
767 | spin_unlock_irq(&davinci_nand_lock); | ||
768 | |||
512 | err_ecc: | 769 | err_ecc: |
513 | err_clk: | 770 | err_clk: |
514 | err_ioremap: | 771 | err_ioremap: |
@@ -532,6 +789,11 @@ static int __exit nand_davinci_remove(struct platform_device *pdev) | |||
532 | else | 789 | else |
533 | status = del_mtd_device(&info->mtd); | 790 | status = del_mtd_device(&info->mtd); |
534 | 791 | ||
792 | spin_lock_irq(&davinci_nand_lock); | ||
793 | if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) | ||
794 | ecc4_busy = false; | ||
795 | spin_unlock_irq(&davinci_nand_lock); | ||
796 | |||
535 | iounmap(info->base); | 797 | iounmap(info->base); |
536 | iounmap(info->vaddr); | 798 | iounmap(info->vaddr); |
537 | 799 | ||