1 files changed, 8 insertions, 3 deletions

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 8beb0d0233b5..a90fde3ede28 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -316,7 +316,7 @@ static int nand_davinci_correct_4bit(struct mtd_info *mtd,
         u32 syndrome[4];
         u32 ecc_state;
         unsigned num_errors, corrected;
-        unsigned long timeo = jiffies + msecs_to_jiffies(100);
+        unsigned long timeo;
 
         /* All bytes 0xff?  It's an erased page; ignore its ECC. */
         for (i = 0; i < 10; i++) {
@@ -372,9 +372,11 @@ compare:
          * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
          * begin trying to poll for the state, you may fall right out of your
          * loop without any of the correction calculations having taken place.
-         * The recommendation from the hardware team is to wait till ECC_STATE
-         * reads less than 4, which means ECC HW has entered correction state.
+         * The recommendation from the hardware team is to initially delay as
+         * long as ECC_STATE reads less than 4. After that, ECC HW has entered
+         * correction state.
          */
+        timeo = jiffies + usecs_to_jiffies(100);
         do {
                 ecc_state = (davinci_nand_readl(info,
                                 NANDFSR_OFFSET) >> 8) & 0x0f;
@@ -733,6 +735,9 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
                  * breaks userspace ioctl interface with mtd-utils. Once we
                  * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
                  * for the 4KiB page chips.
+                 *
+                 * TODO: Note that nand_ecclayout has now been expanded and can
+                 *  hold plenty of OOB entries.
                  */
                 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
                                 "for 4KiB-page NAND\n");