diff options
Diffstat (limited to 'drivers/mtd/nand/bf5xx_nand.c')
-rw-r--r-- | drivers/mtd/nand/bf5xx_nand.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c index 8506e7e606fd..2974995e194d 100644 --- a/drivers/mtd/nand/bf5xx_nand.c +++ b/drivers/mtd/nand/bf5xx_nand.c | |||
@@ -68,6 +68,27 @@ | |||
68 | #define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>" | 68 | #define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>" |
69 | #define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver" | 69 | #define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver" |
70 | 70 | ||
71 | /* NFC_STAT Masks */ | ||
72 | #define NBUSY 0x01 /* Not Busy */ | ||
73 | #define WB_FULL 0x02 /* Write Buffer Full */ | ||
74 | #define PG_WR_STAT 0x04 /* Page Write Pending */ | ||
75 | #define PG_RD_STAT 0x08 /* Page Read Pending */ | ||
76 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | ||
77 | |||
78 | /* NFC_IRQSTAT Masks */ | ||
79 | #define NBUSYIRQ 0x01 /* Not Busy IRQ */ | ||
80 | #define WB_OVF 0x02 /* Write Buffer Overflow */ | ||
81 | #define WB_EDGE 0x04 /* Write Buffer Edge Detect */ | ||
82 | #define RD_RDY 0x08 /* Read Data Ready */ | ||
83 | #define WR_DONE 0x10 /* Page Write Done */ | ||
84 | |||
85 | /* NFC_RST Masks */ | ||
86 | #define ECC_RST 0x01 /* ECC (and NFC counters) Reset */ | ||
87 | |||
88 | /* NFC_PGCTL Masks */ | ||
89 | #define PG_RD_START 0x01 /* Page Read Start */ | ||
90 | #define PG_WR_START 0x02 /* Page Write Start */ | ||
91 | |||
71 | #ifdef CONFIG_MTD_NAND_BF5XX_HWECC | 92 | #ifdef CONFIG_MTD_NAND_BF5XX_HWECC |
72 | static int hardware_ecc = 1; | 93 | static int hardware_ecc = 1; |
73 | #else | 94 | #else |
@@ -487,7 +508,7 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd, | |||
487 | * transferred to generate the correct ECC register | 508 | * transferred to generate the correct ECC register |
488 | * values. | 509 | * values. |
489 | */ | 510 | */ |
490 | bfin_write_NFC_RST(0x1); | 511 | bfin_write_NFC_RST(ECC_RST); |
491 | SSYNC(); | 512 | SSYNC(); |
492 | 513 | ||
493 | disable_dma(CH_NFC); | 514 | disable_dma(CH_NFC); |
@@ -497,7 +518,7 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd, | |||
497 | set_dma_config(CH_NFC, 0x0); | 518 | set_dma_config(CH_NFC, 0x0); |
498 | set_dma_start_addr(CH_NFC, (unsigned long) buf); | 519 | set_dma_start_addr(CH_NFC, (unsigned long) buf); |
499 | 520 | ||
500 | /* The DMAs have different size on BF52x and BF54x */ | 521 | /* The DMAs have different size on BF52x and BF54x */ |
501 | #ifdef CONFIG_BF52x | 522 | #ifdef CONFIG_BF52x |
502 | set_dma_x_count(CH_NFC, (page_size >> 1)); | 523 | set_dma_x_count(CH_NFC, (page_size >> 1)); |
503 | set_dma_x_modify(CH_NFC, 2); | 524 | set_dma_x_modify(CH_NFC, 2); |
@@ -517,9 +538,9 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd, | |||
517 | 538 | ||
518 | /* Start PAGE read/write operation */ | 539 | /* Start PAGE read/write operation */ |
519 | if (is_read) | 540 | if (is_read) |
520 | bfin_write_NFC_PGCTL(0x1); | 541 | bfin_write_NFC_PGCTL(PG_RD_START); |
521 | else | 542 | else |
522 | bfin_write_NFC_PGCTL(0x2); | 543 | bfin_write_NFC_PGCTL(PG_WR_START); |
523 | wait_for_completion(&info->dma_completion); | 544 | wait_for_completion(&info->dma_completion); |
524 | } | 545 | } |
525 | 546 | ||