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path: root/drivers/mtd/nand/au1550nd.c
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Diffstat (limited to 'drivers/mtd/nand/au1550nd.c')
-rw-r--r--drivers/mtd/nand/au1550nd.c321
1 files changed, 228 insertions, 93 deletions
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index bde3550910a2..31228334da12 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -14,6 +14,7 @@
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h>
17#include <linux/mtd/mtd.h> 18#include <linux/mtd/mtd.h>
18#include <linux/mtd/nand.h> 19#include <linux/mtd/nand.h>
19#include <linux/mtd/partitions.h> 20#include <linux/mtd/partitions.h>
@@ -38,22 +39,21 @@
38 */ 39 */
39static struct mtd_info *au1550_mtd = NULL; 40static struct mtd_info *au1550_mtd = NULL;
40static void __iomem *p_nand; 41static void __iomem *p_nand;
41static int nand_width = 1; /* default x8*/ 42static int nand_width = 1; /* default x8 */
43static void (*au1550_write_byte)(struct mtd_info *, u_char);
42 44
43/* 45/*
44 * Define partitions for flash device 46 * Define partitions for flash device
45 */ 47 */
46static const struct mtd_partition partition_info[] = { 48static const struct mtd_partition partition_info[] = {
47 { 49 {
48 .name = "NAND FS 0", 50 .name = "NAND FS 0",
49 .offset = 0, 51 .offset = 0,
50 .size = 8*1024*1024 52 .size = 8 * 1024 * 1024},
51 },
52 { 53 {
53 .name = "NAND FS 1", 54 .name = "NAND FS 1",
54 .offset = MTDPART_OFS_APPEND, 55 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL 56 .size = MTDPART_SIZ_FULL}
56 }
57}; 57};
58 58
59/** 59/**
@@ -130,21 +130,6 @@ static u16 au_read_word(struct mtd_info *mtd)
130} 130}
131 131
132/** 132/**
133 * au_write_word - write one word to the chip
134 * @mtd: MTD device structure
135 * @word: data word to write
136 *
137 * write function for 16bit buswith without
138 * endianess conversion
139 */
140static void au_write_word(struct mtd_info *mtd, u16 word)
141{
142 struct nand_chip *this = mtd->priv;
143 writew(word, this->IO_ADDR_W);
144 au_sync();
145}
146
147/**
148 * au_write_buf - write buffer to chip 133 * au_write_buf - write buffer to chip
149 * @mtd: MTD device structure 134 * @mtd: MTD device structure
150 * @buf: data buffer 135 * @buf: data buffer
@@ -157,7 +142,7 @@ static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
157 int i; 142 int i;
158 struct nand_chip *this = mtd->priv; 143 struct nand_chip *this = mtd->priv;
159 144
160 for (i=0; i<len; i++) { 145 for (i = 0; i < len; i++) {
161 writeb(buf[i], this->IO_ADDR_W); 146 writeb(buf[i], this->IO_ADDR_W);
162 au_sync(); 147 au_sync();
163 } 148 }
@@ -176,7 +161,7 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
176 int i; 161 int i;
177 struct nand_chip *this = mtd->priv; 162 struct nand_chip *this = mtd->priv;
178 163
179 for (i=0; i<len; i++) { 164 for (i = 0; i < len; i++) {
180 buf[i] = readb(this->IO_ADDR_R); 165 buf[i] = readb(this->IO_ADDR_R);
181 au_sync(); 166 au_sync();
182 } 167 }
@@ -195,7 +180,7 @@ static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
195 int i; 180 int i;
196 struct nand_chip *this = mtd->priv; 181 struct nand_chip *this = mtd->priv;
197 182
198 for (i=0; i<len; i++) { 183 for (i = 0; i < len; i++) {
199 if (buf[i] != readb(this->IO_ADDR_R)) 184 if (buf[i] != readb(this->IO_ADDR_R))
200 return -EFAULT; 185 return -EFAULT;
201 au_sync(); 186 au_sync();
@@ -219,7 +204,7 @@ static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
219 u16 *p = (u16 *) buf; 204 u16 *p = (u16 *) buf;
220 len >>= 1; 205 len >>= 1;
221 206
222 for (i=0; i<len; i++) { 207 for (i = 0; i < len; i++) {
223 writew(p[i], this->IO_ADDR_W); 208 writew(p[i], this->IO_ADDR_W);
224 au_sync(); 209 au_sync();
225 } 210 }
@@ -241,7 +226,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
241 u16 *p = (u16 *) buf; 226 u16 *p = (u16 *) buf;
242 len >>= 1; 227 len >>= 1;
243 228
244 for (i=0; i<len; i++) { 229 for (i = 0; i < len; i++) {
245 p[i] = readw(this->IO_ADDR_R); 230 p[i] = readw(this->IO_ADDR_R);
246 au_sync(); 231 au_sync();
247 } 232 }
@@ -262,7 +247,7 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
262 u16 *p = (u16 *) buf; 247 u16 *p = (u16 *) buf;
263 len >>= 1; 248 len >>= 1;
264 249
265 for (i=0; i<len; i++) { 250 for (i = 0; i < len; i++) {
266 if (p[i] != readw(this->IO_ADDR_R)) 251 if (p[i] != readw(this->IO_ADDR_R))
267 return -EFAULT; 252 return -EFAULT;
268 au_sync(); 253 au_sync();
@@ -270,32 +255,52 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
270 return 0; 255 return 0;
271} 256}
272 257
258/* Select the chip by setting nCE to low */
259#define NAND_CTL_SETNCE 1
260/* Deselect the chip by setting nCE to high */
261#define NAND_CTL_CLRNCE 2
262/* Select the command latch by setting CLE to high */
263#define NAND_CTL_SETCLE 3
264/* Deselect the command latch by setting CLE to low */
265#define NAND_CTL_CLRCLE 4
266/* Select the address latch by setting ALE to high */
267#define NAND_CTL_SETALE 5
268/* Deselect the address latch by setting ALE to low */
269#define NAND_CTL_CLRALE 6
273 270
274static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 271static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
275{ 272{
276 register struct nand_chip *this = mtd->priv; 273 register struct nand_chip *this = mtd->priv;
277 274
278 switch(cmd){ 275 switch (cmd) {
279 276
280 case NAND_CTL_SETCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; break; 277 case NAND_CTL_SETCLE:
281 case NAND_CTL_CLRCLE: this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; break; 278 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
279 break;
280
281 case NAND_CTL_CLRCLE:
282 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
283 break;
284
285 case NAND_CTL_SETALE:
286 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
287 break;
282 288
283 case NAND_CTL_SETALE: this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; break;
284 case NAND_CTL_CLRALE: 289 case NAND_CTL_CLRALE:
285 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 290 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
286 /* FIXME: Nobody knows why this is neccecary, 291 /* FIXME: Nobody knows why this is necessary,
287 * but it works only that way */ 292 * but it works only that way */
288 udelay(1); 293 udelay(1);
289 break; 294 break;
290 295
291 case NAND_CTL_SETNCE: 296 case NAND_CTL_SETNCE:
292 /* assert (force assert) chip enable */ 297 /* assert (force assert) chip enable */
293 au_writel((1<<(4+NAND_CS)) , MEM_STNDCTL); break; 298 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
294 break; 299 break;
295 300
296 case NAND_CTL_CLRNCE: 301 case NAND_CTL_CLRNCE:
297 /* deassert chip enable */ 302 /* deassert chip enable */
298 au_writel(0, MEM_STNDCTL); break; 303 au_writel(0, MEM_STNDCTL);
299 break; 304 break;
300 } 305 }
301 306
@@ -312,69 +317,200 @@ int au1550_device_ready(struct mtd_info *mtd)
312 return ret; 317 return ret;
313} 318}
314 319
320/**
321 * au1550_select_chip - control -CE line
322 * Forbid driving -CE manually permitting the NAND controller to do this.
323 * Keeping -CE asserted during the whole sector reads interferes with the
324 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
325 * We only have to hold -CE low for the NAND read commands since the flash
326 * chip needs it to be asserted during chip not ready time but the NAND
327 * controller keeps it released.
328 *
329 * @mtd: MTD device structure
330 * @chip: chipnumber to select, -1 for deselect
331 */
332static void au1550_select_chip(struct mtd_info *mtd, int chip)
333{
334}
335
336/**
337 * au1550_command - Send command to NAND device
338 * @mtd: MTD device structure
339 * @command: the command to be sent
340 * @column: the column address for this command, -1 if none
341 * @page_addr: the page address for this command, -1 if none
342 */
343static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
344{
345 register struct nand_chip *this = mtd->priv;
346 int ce_override = 0, i;
347 ulong flags;
348
349 /* Begin command latch cycle */
350 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
351 /*
352 * Write out the command to the device.
353 */
354 if (command == NAND_CMD_SEQIN) {
355 int readcmd;
356
357 if (column >= mtd->writesize) {
358 /* OOB area */
359 column -= mtd->writesize;
360 readcmd = NAND_CMD_READOOB;
361 } else if (column < 256) {
362 /* First 256 bytes --> READ0 */
363 readcmd = NAND_CMD_READ0;
364 } else {
365 column -= 256;
366 readcmd = NAND_CMD_READ1;
367 }
368 au1550_write_byte(mtd, readcmd);
369 }
370 au1550_write_byte(mtd, command);
371
372 /* Set ALE and clear CLE to start address cycle */
373 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
374
375 if (column != -1 || page_addr != -1) {
376 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
377
378 /* Serially input address */
379 if (column != -1) {
380 /* Adjust columns for 16 bit buswidth */
381 if (this->options & NAND_BUSWIDTH_16)
382 column >>= 1;
383 au1550_write_byte(mtd, column);
384 }
385 if (page_addr != -1) {
386 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
387
388 if (command == NAND_CMD_READ0 ||
389 command == NAND_CMD_READ1 ||
390 command == NAND_CMD_READOOB) {
391 /*
392 * NAND controller will release -CE after
393 * the last address byte is written, so we'll
394 * have to forcibly assert it. No interrupts
395 * are allowed while we do this as we don't
396 * want the NOR flash or PCMCIA drivers to
397 * steal our precious bytes of data...
398 */
399 ce_override = 1;
400 local_irq_save(flags);
401 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
402 }
403
404 au1550_write_byte(mtd, (u8)(page_addr >> 8));
405
406 /* One more address cycle for devices > 32MiB */
407 if (this->chipsize > (32 << 20))
408 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
409 }
410 /* Latch in address */
411 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
412 }
413
414 /*
415 * Program and erase have their own busy handlers.
416 * Status and sequential in need no delay.
417 */
418 switch (command) {
419
420 case NAND_CMD_PAGEPROG:
421 case NAND_CMD_ERASE1:
422 case NAND_CMD_ERASE2:
423 case NAND_CMD_SEQIN:
424 case NAND_CMD_STATUS:
425 return;
426
427 case NAND_CMD_RESET:
428 break;
429
430 case NAND_CMD_READ0:
431 case NAND_CMD_READ1:
432 case NAND_CMD_READOOB:
433 /* Check if we're really driving -CE low (just in case) */
434 if (unlikely(!ce_override))
435 break;
436
437 /* Apply a short delay always to ensure that we do wait tWB. */
438 ndelay(100);
439 /* Wait for a chip to become ready... */
440 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
441 udelay(1);
442
443 /* Release -CE and re-enable interrupts. */
444 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
445 local_irq_restore(flags);
446 return;
447 }
448 /* Apply this short delay always to ensure that we do wait tWB. */
449 ndelay(100);
450
451 while(!this->dev_ready(mtd));
452}
453
454
315/* 455/*
316 * Main initialization routine 456 * Main initialization routine
317 */ 457 */
318int __init au1xxx_nand_init (void) 458static int __init au1xxx_nand_init(void)
319{ 459{
320 struct nand_chip *this; 460 struct nand_chip *this;
321 u16 boot_swapboot = 0; /* default value */ 461 u16 boot_swapboot = 0; /* default value */
322 int retval; 462 int retval;
323 u32 mem_staddr; 463 u32 mem_staddr;
324 u32 nand_phys; 464 u32 nand_phys;
325 465
326 /* Allocate memory for MTD device structure and private data */ 466 /* Allocate memory for MTD device structure and private data */
327 au1550_mtd = kmalloc (sizeof(struct mtd_info) + 467 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
328 sizeof (struct nand_chip), GFP_KERNEL);
329 if (!au1550_mtd) { 468 if (!au1550_mtd) {
330 printk ("Unable to allocate NAND MTD dev structure.\n"); 469 printk("Unable to allocate NAND MTD dev structure.\n");
331 return -ENOMEM; 470 return -ENOMEM;
332 } 471 }
333 472
334 /* Get pointer to private data */ 473 /* Get pointer to private data */
335 this = (struct nand_chip *) (&au1550_mtd[1]); 474 this = (struct nand_chip *)(&au1550_mtd[1]);
336 475
337 /* Initialize structures */ 476 /* Initialize structures */
338 memset((char *) au1550_mtd, 0, sizeof(struct mtd_info)); 477 memset(au1550_mtd, 0, sizeof(struct mtd_info));
339 memset((char *) this, 0, sizeof(struct nand_chip)); 478 memset(this, 0, sizeof(struct nand_chip));
340 479
341 /* Link the private data with the MTD structure */ 480 /* Link the private data with the MTD structure */
342 au1550_mtd->priv = this; 481 au1550_mtd->priv = this;
482 au1550_mtd->owner = THIS_MODULE;
343 483
344 484
345 /* disable interrupts */ 485 /* MEM_STNDCTL: disable ints, disable nand boot */
346 au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL); 486 au_writel(0, MEM_STNDCTL);
347
348 /* disable NAND boot */
349 au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
350 487
351#ifdef CONFIG_MIPS_PB1550 488#ifdef CONFIG_MIPS_PB1550
352 /* set gpio206 high */ 489 /* set gpio206 high */
353 au_writel(au_readl(GPIO2_DIR) & ~(1<<6), GPIO2_DIR); 490 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
354 491
355 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7<<1)) | 492 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
356 ((bcsr->status >> 6) & 0x1);
357 switch (boot_swapboot) { 493 switch (boot_swapboot) {
358 case 0: 494 case 0:
359 case 2: 495 case 2:
360 case 8: 496 case 8:
361 case 0xC: 497 case 0xC:
362 case 0xD: 498 case 0xD:
363 /* x16 NAND Flash */ 499 /* x16 NAND Flash */
364 nand_width = 0; 500 nand_width = 0;
365 break; 501 break;
366 case 1: 502 case 1:
367 case 9: 503 case 9:
368 case 3: 504 case 3:
369 case 0xE: 505 case 0xE:
370 case 0xF: 506 case 0xF:
371 /* x8 NAND Flash */ 507 /* x8 NAND Flash */
372 nand_width = 1; 508 nand_width = 1;
373 break; 509 break;
374 default: 510 default:
375 printk("Pb1550 NAND: bad boot:swap\n"); 511 printk("Pb1550 NAND: bad boot:swap\n");
376 retval = -EINVAL; 512 retval = -EINVAL;
377 goto outmem; 513 goto outmem;
378 } 514 }
379#endif 515#endif
380 516
@@ -424,21 +560,22 @@ int __init au1xxx_nand_init (void)
424 560
425 /* make controller and MTD agree */ 561 /* make controller and MTD agree */
426 if (NAND_CS == 0) 562 if (NAND_CS == 0)
427 nand_width = au_readl(MEM_STCFG0) & (1<<22); 563 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
428 if (NAND_CS == 1) 564 if (NAND_CS == 1)
429 nand_width = au_readl(MEM_STCFG1) & (1<<22); 565 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
430 if (NAND_CS == 2) 566 if (NAND_CS == 2)
431 nand_width = au_readl(MEM_STCFG2) & (1<<22); 567 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
432 if (NAND_CS == 3) 568 if (NAND_CS == 3)
433 nand_width = au_readl(MEM_STCFG3) & (1<<22); 569 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
434
435 570
436 /* Set address of hardware control function */ 571 /* Set address of hardware control function */
437 this->hwcontrol = au1550_hwcontrol;
438 this->dev_ready = au1550_device_ready; 572 this->dev_ready = au1550_device_ready;
573 this->select_chip = au1550_select_chip;
574 this->cmdfunc = au1550_command;
575
439 /* 30 us command delay time */ 576 /* 30 us command delay time */
440 this->chip_delay = 30; 577 this->chip_delay = 30;
441 this->eccmode = NAND_ECC_SOFT; 578 this->ecc.mode = NAND_ECC_SOFT;
442 579
443 this->options = NAND_NO_AUTOINCR; 580 this->options = NAND_NO_AUTOINCR;
444 581
@@ -446,15 +583,14 @@ int __init au1xxx_nand_init (void)
446 this->options |= NAND_BUSWIDTH_16; 583 this->options |= NAND_BUSWIDTH_16;
447 584
448 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; 585 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
449 this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; 586 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
450 this->write_word = au_write_word;
451 this->read_word = au_read_word; 587 this->read_word = au_read_word;
452 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; 588 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
453 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; 589 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
454 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; 590 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
455 591
456 /* Scan to find existence of the device */ 592 /* Scan to find existence of the device */
457 if (nand_scan (au1550_mtd, 1)) { 593 if (nand_scan(au1550_mtd, 1)) {
458 retval = -ENXIO; 594 retval = -ENXIO;
459 goto outio; 595 goto outio;
460 } 596 }
@@ -465,10 +601,10 @@ int __init au1xxx_nand_init (void)
465 return 0; 601 return 0;
466 602
467 outio: 603 outio:
468 iounmap ((void *)p_nand); 604 iounmap((void *)p_nand);
469 605
470 outmem: 606 outmem:
471 kfree (au1550_mtd); 607 kfree(au1550_mtd);
472 return retval; 608 return retval;
473} 609}
474 610
@@ -477,22 +613,21 @@ module_init(au1xxx_nand_init);
477/* 613/*
478 * Clean up routine 614 * Clean up routine
479 */ 615 */
480#ifdef MODULE 616static void __exit au1550_cleanup(void)
481static void __exit au1550_cleanup (void)
482{ 617{
483 struct nand_chip *this = (struct nand_chip *) &au1550_mtd[1]; 618 struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1];
484 619
485 /* Release resources, unregister device */ 620 /* Release resources, unregister device */
486 nand_release (au1550_mtd); 621 nand_release(au1550_mtd);
487 622
488 /* Free the MTD device structure */ 623 /* Free the MTD device structure */
489 kfree (au1550_mtd); 624 kfree(au1550_mtd);
490 625
491 /* Unmap */ 626 /* Unmap */
492 iounmap ((void *)p_nand); 627 iounmap((void *)p_nand);
493} 628}
629
494module_exit(au1550_cleanup); 630module_exit(au1550_cleanup);
495#endif
496 631
497MODULE_LICENSE("GPL"); 632MODULE_LICENSE("GPL");
498MODULE_AUTHOR("Embedded Edge, LLC"); 633MODULE_AUTHOR("Embedded Edge, LLC");