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-rw-r--r--drivers/mtd/nand/atmel_nand.c987
1 files changed, 924 insertions, 63 deletions
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 97ac6712bb19..914455783302 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1,20 +1,22 @@
1/* 1/*
2 * Copyright (C) 2003 Rick Bronson 2 * Copyright © 2003 Rick Bronson
3 * 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c 4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 * 6 *
7 * Derived from drivers/mtd/spia.c 7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 * 9 *
10 * 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 * 13 *
14 * Derived from Das U-Boot source code 14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) 15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 * 17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
18 * 20 *
19 * This program is free software; you can redistribute it and/or modify 21 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as 22 * it under the terms of the GNU General Public License version 2 as
@@ -93,8 +95,36 @@ struct atmel_nand_host {
93 95
94 struct completion comp; 96 struct completion comp;
95 struct dma_chan *dma_chan; 97 struct dma_chan *dma_chan;
98
99 bool has_pmecc;
100 u8 pmecc_corr_cap;
101 u16 pmecc_sector_size;
102 u32 pmecc_lookup_table_offset;
103
104 int pmecc_bytes_per_sector;
105 int pmecc_sector_number;
106 int pmecc_degree; /* Degree of remainders */
107 int pmecc_cw_len; /* Length of codeword */
108
109 void __iomem *pmerrloc_base;
110 void __iomem *pmecc_rom_base;
111
112 /* lookup table for alpha_to and index_of */
113 void __iomem *pmecc_alpha_to;
114 void __iomem *pmecc_index_of;
115
116 /* data for pmecc computation */
117 int16_t *pmecc_partial_syn;
118 int16_t *pmecc_si;
119 int16_t *pmecc_smu; /* Sigma table */
120 int16_t *pmecc_lmu; /* polynomal order */
121 int *pmecc_mu;
122 int *pmecc_dmu;
123 int *pmecc_delta;
96}; 124};
97 125
126static struct nand_ecclayout atmel_pmecc_oobinfo;
127
98static int cpu_has_dma(void) 128static int cpu_has_dma(void)
99{ 129{
100 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); 130 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
@@ -288,6 +318,703 @@ static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
288} 318}
289 319
290/* 320/*
321 * Return number of ecc bytes per sector according to sector size and
322 * correction capability
323 *
324 * Following table shows what at91 PMECC supported:
325 * Correction Capability Sector_512_bytes Sector_1024_bytes
326 * ===================== ================ =================
327 * 2-bits 4-bytes 4-bytes
328 * 4-bits 7-bytes 7-bytes
329 * 8-bits 13-bytes 14-bytes
330 * 12-bits 20-bytes 21-bytes
331 * 24-bits 39-bytes 42-bytes
332 */
333static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size)
334{
335 int m = 12 + sector_size / 512;
336 return (m * cap + 7) / 8;
337}
338
339static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout,
340 int oobsize, int ecc_len)
341{
342 int i;
343
344 layout->eccbytes = ecc_len;
345
346 /* ECC will occupy the last ecc_len bytes continuously */
347 for (i = 0; i < ecc_len; i++)
348 layout->eccpos[i] = oobsize - ecc_len + i;
349
350 layout->oobfree[0].offset = 2;
351 layout->oobfree[0].length =
352 oobsize - ecc_len - layout->oobfree[0].offset;
353}
354
355static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
356{
357 int table_size;
358
359 table_size = host->pmecc_sector_size == 512 ?
360 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
361
362 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
363 table_size * sizeof(int16_t);
364}
365
366static void pmecc_data_free(struct atmel_nand_host *host)
367{
368 kfree(host->pmecc_partial_syn);
369 kfree(host->pmecc_si);
370 kfree(host->pmecc_lmu);
371 kfree(host->pmecc_smu);
372 kfree(host->pmecc_mu);
373 kfree(host->pmecc_dmu);
374 kfree(host->pmecc_delta);
375}
376
377static int __devinit pmecc_data_alloc(struct atmel_nand_host *host)
378{
379 const int cap = host->pmecc_corr_cap;
380
381 host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
382 GFP_KERNEL);
383 host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
384 host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
385 host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
386 GFP_KERNEL);
387 host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
388 host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
389 host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
390
391 if (host->pmecc_partial_syn &&
392 host->pmecc_si &&
393 host->pmecc_lmu &&
394 host->pmecc_smu &&
395 host->pmecc_mu &&
396 host->pmecc_dmu &&
397 host->pmecc_delta)
398 return 0;
399
400 /* error happened */
401 pmecc_data_free(host);
402 return -ENOMEM;
403}
404
405static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
406{
407 struct nand_chip *nand_chip = mtd->priv;
408 struct atmel_nand_host *host = nand_chip->priv;
409 int i;
410 uint32_t value;
411
412 /* Fill odd syndromes */
413 for (i = 0; i < host->pmecc_corr_cap; i++) {
414 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
415 if (i & 1)
416 value >>= 16;
417 value &= 0xffff;
418 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
419 }
420}
421
422static void pmecc_substitute(struct mtd_info *mtd)
423{
424 struct nand_chip *nand_chip = mtd->priv;
425 struct atmel_nand_host *host = nand_chip->priv;
426 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
427 int16_t __iomem *index_of = host->pmecc_index_of;
428 int16_t *partial_syn = host->pmecc_partial_syn;
429 const int cap = host->pmecc_corr_cap;
430 int16_t *si;
431 int i, j;
432
433 /* si[] is a table that holds the current syndrome value,
434 * an element of that table belongs to the field
435 */
436 si = host->pmecc_si;
437
438 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
439
440 /* Computation 2t syndromes based on S(x) */
441 /* Odd syndromes */
442 for (i = 1; i < 2 * cap; i += 2) {
443 for (j = 0; j < host->pmecc_degree; j++) {
444 if (partial_syn[i] & ((unsigned short)0x1 << j))
445 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
446 }
447 }
448 /* Even syndrome = (Odd syndrome) ** 2 */
449 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
450 if (si[j] == 0) {
451 si[i] = 0;
452 } else {
453 int16_t tmp;
454
455 tmp = readw_relaxed(index_of + si[j]);
456 tmp = (tmp * 2) % host->pmecc_cw_len;
457 si[i] = readw_relaxed(alpha_to + tmp);
458 }
459 }
460
461 return;
462}
463
464static void pmecc_get_sigma(struct mtd_info *mtd)
465{
466 struct nand_chip *nand_chip = mtd->priv;
467 struct atmel_nand_host *host = nand_chip->priv;
468
469 int16_t *lmu = host->pmecc_lmu;
470 int16_t *si = host->pmecc_si;
471 int *mu = host->pmecc_mu;
472 int *dmu = host->pmecc_dmu; /* Discrepancy */
473 int *delta = host->pmecc_delta; /* Delta order */
474 int cw_len = host->pmecc_cw_len;
475 const int16_t cap = host->pmecc_corr_cap;
476 const int num = 2 * cap + 1;
477 int16_t __iomem *index_of = host->pmecc_index_of;
478 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
479 int i, j, k;
480 uint32_t dmu_0_count, tmp;
481 int16_t *smu = host->pmecc_smu;
482
483 /* index of largest delta */
484 int ro;
485 int largest;
486 int diff;
487
488 dmu_0_count = 0;
489
490 /* First Row */
491
492 /* Mu */
493 mu[0] = -1;
494
495 memset(smu, 0, sizeof(int16_t) * num);
496 smu[0] = 1;
497
498 /* discrepancy set to 1 */
499 dmu[0] = 1;
500 /* polynom order set to 0 */
501 lmu[0] = 0;
502 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
503
504 /* Second Row */
505
506 /* Mu */
507 mu[1] = 0;
508 /* Sigma(x) set to 1 */
509 memset(&smu[num], 0, sizeof(int16_t) * num);
510 smu[num] = 1;
511
512 /* discrepancy set to S1 */
513 dmu[1] = si[1];
514
515 /* polynom order set to 0 */
516 lmu[1] = 0;
517
518 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
519
520 /* Init the Sigma(x) last row */
521 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
522
523 for (i = 1; i <= cap; i++) {
524 mu[i + 1] = i << 1;
525 /* Begin Computing Sigma (Mu+1) and L(mu) */
526 /* check if discrepancy is set to 0 */
527 if (dmu[i] == 0) {
528 dmu_0_count++;
529
530 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
531 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
532 tmp += 2;
533 else
534 tmp += 1;
535
536 if (dmu_0_count == tmp) {
537 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
538 smu[(cap + 1) * num + j] =
539 smu[i * num + j];
540
541 lmu[cap + 1] = lmu[i];
542 return;
543 }
544
545 /* copy polynom */
546 for (j = 0; j <= lmu[i] >> 1; j++)
547 smu[(i + 1) * num + j] = smu[i * num + j];
548
549 /* copy previous polynom order to the next */
550 lmu[i + 1] = lmu[i];
551 } else {
552 ro = 0;
553 largest = -1;
554 /* find largest delta with dmu != 0 */
555 for (j = 0; j < i; j++) {
556 if ((dmu[j]) && (delta[j] > largest)) {
557 largest = delta[j];
558 ro = j;
559 }
560 }
561
562 /* compute difference */
563 diff = (mu[i] - mu[ro]);
564
565 /* Compute degree of the new smu polynomial */
566 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
567 lmu[i + 1] = lmu[i];
568 else
569 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
570
571 /* Init smu[i+1] with 0 */
572 for (k = 0; k < num; k++)
573 smu[(i + 1) * num + k] = 0;
574
575 /* Compute smu[i+1] */
576 for (k = 0; k <= lmu[ro] >> 1; k++) {
577 int16_t a, b, c;
578
579 if (!(smu[ro * num + k] && dmu[i]))
580 continue;
581 a = readw_relaxed(index_of + dmu[i]);
582 b = readw_relaxed(index_of + dmu[ro]);
583 c = readw_relaxed(index_of + smu[ro * num + k]);
584 tmp = a + (cw_len - b) + c;
585 a = readw_relaxed(alpha_to + tmp % cw_len);
586 smu[(i + 1) * num + (k + diff)] = a;
587 }
588
589 for (k = 0; k <= lmu[i] >> 1; k++)
590 smu[(i + 1) * num + k] ^= smu[i * num + k];
591 }
592
593 /* End Computing Sigma (Mu+1) and L(mu) */
594 /* In either case compute delta */
595 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
596
597 /* Do not compute discrepancy for the last iteration */
598 if (i >= cap)
599 continue;
600
601 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
602 tmp = 2 * (i - 1);
603 if (k == 0) {
604 dmu[i + 1] = si[tmp + 3];
605 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
606 int16_t a, b, c;
607 a = readw_relaxed(index_of +
608 smu[(i + 1) * num + k]);
609 b = si[2 * (i - 1) + 3 - k];
610 c = readw_relaxed(index_of + b);
611 tmp = a + c;
612 tmp %= cw_len;
613 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
614 dmu[i + 1];
615 }
616 }
617 }
618
619 return;
620}
621
622static int pmecc_err_location(struct mtd_info *mtd)
623{
624 struct nand_chip *nand_chip = mtd->priv;
625 struct atmel_nand_host *host = nand_chip->priv;
626 unsigned long end_time;
627 const int cap = host->pmecc_corr_cap;
628 const int num = 2 * cap + 1;
629 int sector_size = host->pmecc_sector_size;
630 int err_nbr = 0; /* number of error */
631 int roots_nbr; /* number of roots */
632 int i;
633 uint32_t val;
634 int16_t *smu = host->pmecc_smu;
635
636 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
637
638 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
639 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
640 smu[(cap + 1) * num + i]);
641 err_nbr++;
642 }
643
644 val = (err_nbr - 1) << 16;
645 if (sector_size == 1024)
646 val |= 1;
647
648 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
649 pmerrloc_writel(host->pmerrloc_base, ELEN,
650 sector_size * 8 + host->pmecc_degree * cap);
651
652 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
653 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
654 & PMERRLOC_CALC_DONE)) {
655 if (unlikely(time_after(jiffies, end_time))) {
656 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
657 return -1;
658 }
659 cpu_relax();
660 }
661
662 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
663 & PMERRLOC_ERR_NUM_MASK) >> 8;
664 /* Number of roots == degree of smu hence <= cap */
665 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
666 return err_nbr - 1;
667
668 /* Number of roots does not match the degree of smu
669 * unable to correct error */
670 return -1;
671}
672
673static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
674 int sector_num, int extra_bytes, int err_nbr)
675{
676 struct nand_chip *nand_chip = mtd->priv;
677 struct atmel_nand_host *host = nand_chip->priv;
678 int i = 0;
679 int byte_pos, bit_pos, sector_size, pos;
680 uint32_t tmp;
681 uint8_t err_byte;
682
683 sector_size = host->pmecc_sector_size;
684
685 while (err_nbr) {
686 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
687 byte_pos = tmp / 8;
688 bit_pos = tmp % 8;
689
690 if (byte_pos >= (sector_size + extra_bytes))
691 BUG(); /* should never happen */
692
693 if (byte_pos < sector_size) {
694 err_byte = *(buf + byte_pos);
695 *(buf + byte_pos) ^= (1 << bit_pos);
696
697 pos = sector_num * host->pmecc_sector_size + byte_pos;
698 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
699 pos, bit_pos, err_byte, *(buf + byte_pos));
700 } else {
701 /* Bit flip in OOB area */
702 tmp = sector_num * host->pmecc_bytes_per_sector
703 + (byte_pos - sector_size);
704 err_byte = ecc[tmp];
705 ecc[tmp] ^= (1 << bit_pos);
706
707 pos = tmp + nand_chip->ecc.layout->eccpos[0];
708 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
709 pos, bit_pos, err_byte, ecc[tmp]);
710 }
711
712 i++;
713 err_nbr--;
714 }
715
716 return;
717}
718
719static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
720 u8 *ecc)
721{
722 struct nand_chip *nand_chip = mtd->priv;
723 struct atmel_nand_host *host = nand_chip->priv;
724 int i, err_nbr, eccbytes;
725 uint8_t *buf_pos;
726
727 eccbytes = nand_chip->ecc.bytes;
728 for (i = 0; i < eccbytes; i++)
729 if (ecc[i] != 0xff)
730 goto normal_check;
731 /* Erased page, return OK */
732 return 0;
733
734normal_check:
735 for (i = 0; i < host->pmecc_sector_number; i++) {
736 err_nbr = 0;
737 if (pmecc_stat & 0x1) {
738 buf_pos = buf + i * host->pmecc_sector_size;
739
740 pmecc_gen_syndrome(mtd, i);
741 pmecc_substitute(mtd);
742 pmecc_get_sigma(mtd);
743
744 err_nbr = pmecc_err_location(mtd);
745 if (err_nbr == -1) {
746 dev_err(host->dev, "PMECC: Too many errors\n");
747 mtd->ecc_stats.failed++;
748 return -EIO;
749 } else {
750 pmecc_correct_data(mtd, buf_pos, ecc, i,
751 host->pmecc_bytes_per_sector, err_nbr);
752 mtd->ecc_stats.corrected += err_nbr;
753 }
754 }
755 pmecc_stat >>= 1;
756 }
757
758 return 0;
759}
760
761static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
762 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
763{
764 struct atmel_nand_host *host = chip->priv;
765 int eccsize = chip->ecc.size;
766 uint8_t *oob = chip->oob_poi;
767 uint32_t *eccpos = chip->ecc.layout->eccpos;
768 uint32_t stat;
769 unsigned long end_time;
770
771 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
772 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
773 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
774 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
775
776 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
777 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
778
779 chip->read_buf(mtd, buf, eccsize);
780 chip->read_buf(mtd, oob, mtd->oobsize);
781
782 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
783 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
784 if (unlikely(time_after(jiffies, end_time))) {
785 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
786 return -EIO;
787 }
788 cpu_relax();
789 }
790
791 stat = pmecc_readl_relaxed(host->ecc, ISR);
792 if (stat != 0)
793 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
794 return -EIO;
795
796 return 0;
797}
798
799static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
800 struct nand_chip *chip, const uint8_t *buf, int oob_required)
801{
802 struct atmel_nand_host *host = chip->priv;
803 uint32_t *eccpos = chip->ecc.layout->eccpos;
804 int i, j;
805 unsigned long end_time;
806
807 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
808 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
809
810 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
811 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
812
813 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
814 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
815
816 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
817
818 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
819 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
820 if (unlikely(time_after(jiffies, end_time))) {
821 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
822 return -EIO;
823 }
824 cpu_relax();
825 }
826
827 for (i = 0; i < host->pmecc_sector_number; i++) {
828 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
829 int pos;
830
831 pos = i * host->pmecc_bytes_per_sector + j;
832 chip->oob_poi[eccpos[pos]] =
833 pmecc_readb_ecc_relaxed(host->ecc, i, j);
834 }
835 }
836 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
837
838 return 0;
839}
840
841static void atmel_pmecc_core_init(struct mtd_info *mtd)
842{
843 struct nand_chip *nand_chip = mtd->priv;
844 struct atmel_nand_host *host = nand_chip->priv;
845 uint32_t val = 0;
846 struct nand_ecclayout *ecc_layout;
847
848 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
849 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
850
851 switch (host->pmecc_corr_cap) {
852 case 2:
853 val = PMECC_CFG_BCH_ERR2;
854 break;
855 case 4:
856 val = PMECC_CFG_BCH_ERR4;
857 break;
858 case 8:
859 val = PMECC_CFG_BCH_ERR8;
860 break;
861 case 12:
862 val = PMECC_CFG_BCH_ERR12;
863 break;
864 case 24:
865 val = PMECC_CFG_BCH_ERR24;
866 break;
867 }
868
869 if (host->pmecc_sector_size == 512)
870 val |= PMECC_CFG_SECTOR512;
871 else if (host->pmecc_sector_size == 1024)
872 val |= PMECC_CFG_SECTOR1024;
873
874 switch (host->pmecc_sector_number) {
875 case 1:
876 val |= PMECC_CFG_PAGE_1SECTOR;
877 break;
878 case 2:
879 val |= PMECC_CFG_PAGE_2SECTORS;
880 break;
881 case 4:
882 val |= PMECC_CFG_PAGE_4SECTORS;
883 break;
884 case 8:
885 val |= PMECC_CFG_PAGE_8SECTORS;
886 break;
887 }
888
889 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
890 | PMECC_CFG_AUTO_DISABLE);
891 pmecc_writel(host->ecc, CFG, val);
892
893 ecc_layout = nand_chip->ecc.layout;
894 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
895 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
896 pmecc_writel(host->ecc, EADDR,
897 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
898 /* See datasheet about PMECC Clock Control Register */
899 pmecc_writel(host->ecc, CLK, 2);
900 pmecc_writel(host->ecc, IDR, 0xff);
901 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
902}
903
904static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
905 struct atmel_nand_host *host)
906{
907 struct mtd_info *mtd = &host->mtd;
908 struct nand_chip *nand_chip = &host->nand_chip;
909 struct resource *regs, *regs_pmerr, *regs_rom;
910 int cap, sector_size, err_no;
911
912 cap = host->pmecc_corr_cap;
913 sector_size = host->pmecc_sector_size;
914 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
915 cap, sector_size);
916
917 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
918 if (!regs) {
919 dev_warn(host->dev,
920 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
921 nand_chip->ecc.mode = NAND_ECC_SOFT;
922 return 0;
923 }
924
925 host->ecc = ioremap(regs->start, resource_size(regs));
926 if (host->ecc == NULL) {
927 dev_err(host->dev, "ioremap failed\n");
928 err_no = -EIO;
929 goto err_pmecc_ioremap;
930 }
931
932 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
933 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
934 if (regs_pmerr && regs_rom) {
935 host->pmerrloc_base = ioremap(regs_pmerr->start,
936 resource_size(regs_pmerr));
937 host->pmecc_rom_base = ioremap(regs_rom->start,
938 resource_size(regs_rom));
939 }
940
941 if (!host->pmerrloc_base || !host->pmecc_rom_base) {
942 dev_err(host->dev,
943 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
944 err_no = -EIO;
945 goto err_pmloc_ioremap;
946 }
947
948 /* ECC is calculated for the whole page (1 step) */
949 nand_chip->ecc.size = mtd->writesize;
950
951 /* set ECC page size and oob layout */
952 switch (mtd->writesize) {
953 case 2048:
954 host->pmecc_degree = PMECC_GF_DIMENSION_13;
955 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
956 host->pmecc_sector_number = mtd->writesize / sector_size;
957 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
958 cap, sector_size);
959 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
960 host->pmecc_index_of = host->pmecc_rom_base +
961 host->pmecc_lookup_table_offset;
962
963 nand_chip->ecc.steps = 1;
964 nand_chip->ecc.strength = cap;
965 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
966 host->pmecc_sector_number;
967 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
968 dev_err(host->dev, "No room for ECC bytes\n");
969 err_no = -EINVAL;
970 goto err_no_ecc_room;
971 }
972 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
973 mtd->oobsize,
974 nand_chip->ecc.bytes);
975 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
976 break;
977 case 512:
978 case 1024:
979 case 4096:
980 /* TODO */
981 dev_warn(host->dev,
982 "Unsupported page size for PMECC, use Software ECC\n");
983 default:
984 /* page size not handled by HW ECC */
985 /* switching back to soft ECC */
986 nand_chip->ecc.mode = NAND_ECC_SOFT;
987 return 0;
988 }
989
990 /* Allocate data for PMECC computation */
991 err_no = pmecc_data_alloc(host);
992 if (err_no) {
993 dev_err(host->dev,
994 "Cannot allocate memory for PMECC computation!\n");
995 goto err_pmecc_data_alloc;
996 }
997
998 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
999 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1000
1001 atmel_pmecc_core_init(mtd);
1002
1003 return 0;
1004
1005err_pmecc_data_alloc:
1006err_no_ecc_room:
1007err_pmloc_ioremap:
1008 iounmap(host->ecc);
1009 if (host->pmerrloc_base)
1010 iounmap(host->pmerrloc_base);
1011 if (host->pmecc_rom_base)
1012 iounmap(host->pmecc_rom_base);
1013err_pmecc_ioremap:
1014 return err_no;
1015}
1016
1017/*
291 * Calculate HW ECC 1018 * Calculate HW ECC
292 * 1019 *
293 * function called after a write 1020 * function called after a write
@@ -481,7 +1208,8 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
481static int __devinit atmel_of_init_port(struct atmel_nand_host *host, 1208static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
482 struct device_node *np) 1209 struct device_node *np)
483{ 1210{
484 u32 val; 1211 u32 val, table_offset;
1212 u32 offset[2];
485 int ecc_mode; 1213 int ecc_mode;
486 struct atmel_nand_data *board = &host->board; 1214 struct atmel_nand_data *board = &host->board;
487 enum of_gpio_flags flags; 1215 enum of_gpio_flags flags;
@@ -517,6 +1245,50 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
517 board->enable_pin = of_get_gpio(np, 1); 1245 board->enable_pin = of_get_gpio(np, 1);
518 board->det_pin = of_get_gpio(np, 2); 1246 board->det_pin = of_get_gpio(np, 2);
519 1247
1248 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1249
1250 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1251 return 0; /* Not using PMECC */
1252
1253 /* use PMECC, get correction capability, sector size and lookup
1254 * table offset.
1255 */
1256 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) {
1257 dev_err(host->dev, "Cannot decide PMECC Capability\n");
1258 return -EINVAL;
1259 } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1260 (val != 24)) {
1261 dev_err(host->dev,
1262 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1263 val);
1264 return -EINVAL;
1265 }
1266 host->pmecc_corr_cap = (u8)val;
1267
1268 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) {
1269 dev_err(host->dev, "Cannot decide PMECC Sector Size\n");
1270 return -EINVAL;
1271 } else if ((val != 512) && (val != 1024)) {
1272 dev_err(host->dev,
1273 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1274 val);
1275 return -EINVAL;
1276 }
1277 host->pmecc_sector_size = (u16)val;
1278
1279 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1280 offset, 2) != 0) {
1281 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1282 return -EINVAL;
1283 }
1284 table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1];
1285
1286 if (!table_offset) {
1287 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1288 return -EINVAL;
1289 }
1290 host->pmecc_lookup_table_offset = table_offset;
1291
520 return 0; 1292 return 0;
521} 1293}
522#else 1294#else
@@ -527,6 +1299,66 @@ static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
527} 1299}
528#endif 1300#endif
529 1301
1302static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1303 struct atmel_nand_host *host)
1304{
1305 struct mtd_info *mtd = &host->mtd;
1306 struct nand_chip *nand_chip = &host->nand_chip;
1307 struct resource *regs;
1308
1309 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1310 if (!regs) {
1311 dev_err(host->dev,
1312 "Can't get I/O resource regs, use software ECC\n");
1313 nand_chip->ecc.mode = NAND_ECC_SOFT;
1314 return 0;
1315 }
1316
1317 host->ecc = ioremap(regs->start, resource_size(regs));
1318 if (host->ecc == NULL) {
1319 dev_err(host->dev, "ioremap failed\n");
1320 return -EIO;
1321 }
1322
1323 /* ECC is calculated for the whole page (1 step) */
1324 nand_chip->ecc.size = mtd->writesize;
1325
1326 /* set ECC page size and oob layout */
1327 switch (mtd->writesize) {
1328 case 512:
1329 nand_chip->ecc.layout = &atmel_oobinfo_small;
1330 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1331 break;
1332 case 1024:
1333 nand_chip->ecc.layout = &atmel_oobinfo_large;
1334 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1335 break;
1336 case 2048:
1337 nand_chip->ecc.layout = &atmel_oobinfo_large;
1338 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1339 break;
1340 case 4096:
1341 nand_chip->ecc.layout = &atmel_oobinfo_large;
1342 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1343 break;
1344 default:
1345 /* page size not handled by HW ECC */
1346 /* switching back to soft ECC */
1347 nand_chip->ecc.mode = NAND_ECC_SOFT;
1348 return 0;
1349 }
1350
1351 /* set up for HW ECC */
1352 nand_chip->ecc.calculate = atmel_nand_calculate;
1353 nand_chip->ecc.correct = atmel_nand_correct;
1354 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1355 nand_chip->ecc.read_page = atmel_nand_read_page;
1356 nand_chip->ecc.bytes = 4;
1357 nand_chip->ecc.strength = 1;
1358
1359 return 0;
1360}
1361
530/* 1362/*
531 * Probe for the NAND device. 1363 * Probe for the NAND device.
532 */ 1364 */
@@ -535,7 +1367,6 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
535 struct atmel_nand_host *host; 1367 struct atmel_nand_host *host;
536 struct mtd_info *mtd; 1368 struct mtd_info *mtd;
537 struct nand_chip *nand_chip; 1369 struct nand_chip *nand_chip;
538 struct resource *regs;
539 struct resource *mem; 1370 struct resource *mem;
540 struct mtd_part_parser_data ppdata = {}; 1371 struct mtd_part_parser_data ppdata = {};
541 int res; 1372 int res;
@@ -568,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
568 if (pdev->dev.of_node) { 1399 if (pdev->dev.of_node) {
569 res = atmel_of_init_port(host, pdev->dev.of_node); 1400 res = atmel_of_init_port(host, pdev->dev.of_node);
570 if (res) 1401 if (res)
571 goto err_nand_ioremap; 1402 goto err_ecc_ioremap;
572 } else { 1403 } else {
573 memcpy(&host->board, pdev->dev.platform_data, 1404 memcpy(&host->board, pdev->dev.platform_data,
574 sizeof(struct atmel_nand_data)); 1405 sizeof(struct atmel_nand_data));
@@ -583,33 +1414,45 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
583 nand_chip->IO_ADDR_W = host->io_base; 1414 nand_chip->IO_ADDR_W = host->io_base;
584 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; 1415 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
585 1416
586 if (gpio_is_valid(host->board.rdy_pin)) 1417 if (gpio_is_valid(host->board.rdy_pin)) {
587 nand_chip->dev_ready = atmel_nand_device_ready; 1418 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1419 if (res < 0) {
1420 dev_err(&pdev->dev,
1421 "can't request rdy gpio %d\n",
1422 host->board.rdy_pin);
1423 goto err_ecc_ioremap;
1424 }
588 1425
589 nand_chip->ecc.mode = host->board.ecc_mode; 1426 res = gpio_direction_input(host->board.rdy_pin);
1427 if (res < 0) {
1428 dev_err(&pdev->dev,
1429 "can't request input direction rdy gpio %d\n",
1430 host->board.rdy_pin);
1431 goto err_ecc_ioremap;
1432 }
590 1433
591 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1434 nand_chip->dev_ready = atmel_nand_device_ready;
592 if (!regs && nand_chip->ecc.mode == NAND_ECC_HW) {
593 printk(KERN_ERR "atmel_nand: can't get I/O resource "
594 "regs\nFalling back on software ECC\n");
595 nand_chip->ecc.mode = NAND_ECC_SOFT;
596 } 1435 }
597 1436
598 if (nand_chip->ecc.mode == NAND_ECC_HW) { 1437 if (gpio_is_valid(host->board.enable_pin)) {
599 host->ecc = ioremap(regs->start, resource_size(regs)); 1438 res = gpio_request(host->board.enable_pin, "nand_enable");
600 if (host->ecc == NULL) { 1439 if (res < 0) {
601 printk(KERN_ERR "atmel_nand: ioremap failed\n"); 1440 dev_err(&pdev->dev,
602 res = -EIO; 1441 "can't request enable gpio %d\n",
1442 host->board.enable_pin);
1443 goto err_ecc_ioremap;
1444 }
1445
1446 res = gpio_direction_output(host->board.enable_pin, 1);
1447 if (res < 0) {
1448 dev_err(&pdev->dev,
1449 "can't request output direction enable gpio %d\n",
1450 host->board.enable_pin);
603 goto err_ecc_ioremap; 1451 goto err_ecc_ioremap;
604 } 1452 }
605 nand_chip->ecc.calculate = atmel_nand_calculate;
606 nand_chip->ecc.correct = atmel_nand_correct;
607 nand_chip->ecc.hwctl = atmel_nand_hwctl;
608 nand_chip->ecc.read_page = atmel_nand_read_page;
609 nand_chip->ecc.bytes = 4;
610 nand_chip->ecc.strength = 1;
611 } 1453 }
612 1454
1455 nand_chip->ecc.mode = host->board.ecc_mode;
613 nand_chip->chip_delay = 20; /* 20us command delay time */ 1456 nand_chip->chip_delay = 20; /* 20us command delay time */
614 1457
615 if (host->board.bus_width_16) /* 16-bit bus width */ 1458 if (host->board.bus_width_16) /* 16-bit bus width */
@@ -622,6 +1465,22 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
622 atmel_nand_enable(host); 1465 atmel_nand_enable(host);
623 1466
624 if (gpio_is_valid(host->board.det_pin)) { 1467 if (gpio_is_valid(host->board.det_pin)) {
1468 res = gpio_request(host->board.det_pin, "nand_det");
1469 if (res < 0) {
1470 dev_err(&pdev->dev,
1471 "can't request det gpio %d\n",
1472 host->board.det_pin);
1473 goto err_no_card;
1474 }
1475
1476 res = gpio_direction_input(host->board.det_pin);
1477 if (res < 0) {
1478 dev_err(&pdev->dev,
1479 "can't request input direction det gpio %d\n",
1480 host->board.det_pin);
1481 goto err_no_card;
1482 }
1483
625 if (gpio_get_value(host->board.det_pin)) { 1484 if (gpio_get_value(host->board.det_pin)) {
626 printk(KERN_INFO "No SmartMedia card inserted.\n"); 1485 printk(KERN_INFO "No SmartMedia card inserted.\n");
627 res = -ENXIO; 1486 res = -ENXIO;
@@ -661,40 +1520,13 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
661 } 1520 }
662 1521
663 if (nand_chip->ecc.mode == NAND_ECC_HW) { 1522 if (nand_chip->ecc.mode == NAND_ECC_HW) {
664 /* ECC is calculated for the whole page (1 step) */ 1523 if (host->has_pmecc)
665 nand_chip->ecc.size = mtd->writesize; 1524 res = atmel_pmecc_nand_init_params(pdev, host);
666 1525 else
667 /* set ECC page size and oob layout */ 1526 res = atmel_hw_nand_init_params(pdev, host);
668 switch (mtd->writesize) { 1527
669 case 512: 1528 if (res != 0)
670 nand_chip->ecc.layout = &atmel_oobinfo_small; 1529 goto err_hw_ecc;
671 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
672 break;
673 case 1024:
674 nand_chip->ecc.layout = &atmel_oobinfo_large;
675 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
676 break;
677 case 2048:
678 nand_chip->ecc.layout = &atmel_oobinfo_large;
679 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
680 break;
681 case 4096:
682 nand_chip->ecc.layout = &atmel_oobinfo_large;
683 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
684 break;
685 default:
686 /* page size not handled by HW ECC */
687 /* switching back to soft ECC */
688 nand_chip->ecc.mode = NAND_ECC_SOFT;
689 nand_chip->ecc.calculate = NULL;
690 nand_chip->ecc.correct = NULL;
691 nand_chip->ecc.hwctl = NULL;
692 nand_chip->ecc.read_page = NULL;
693 nand_chip->ecc.postpad = 0;
694 nand_chip->ecc.prepad = 0;
695 nand_chip->ecc.bytes = 0;
696 break;
697 }
698 } 1530 }
699 1531
700 /* second phase scan */ 1532 /* second phase scan */
@@ -711,14 +1543,23 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
711 return res; 1543 return res;
712 1544
713err_scan_tail: 1545err_scan_tail:
1546 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1547 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1548 pmecc_data_free(host);
1549 }
1550 if (host->ecc)
1551 iounmap(host->ecc);
1552 if (host->pmerrloc_base)
1553 iounmap(host->pmerrloc_base);
1554 if (host->pmecc_rom_base)
1555 iounmap(host->pmecc_rom_base);
1556err_hw_ecc:
714err_scan_ident: 1557err_scan_ident:
715err_no_card: 1558err_no_card:
716 atmel_nand_disable(host); 1559 atmel_nand_disable(host);
717 platform_set_drvdata(pdev, NULL); 1560 platform_set_drvdata(pdev, NULL);
718 if (host->dma_chan) 1561 if (host->dma_chan)
719 dma_release_channel(host->dma_chan); 1562 dma_release_channel(host->dma_chan);
720 if (host->ecc)
721 iounmap(host->ecc);
722err_ecc_ioremap: 1563err_ecc_ioremap:
723 iounmap(host->io_base); 1564 iounmap(host->io_base);
724err_nand_ioremap: 1565err_nand_ioremap:
@@ -738,8 +1579,28 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
738 1579
739 atmel_nand_disable(host); 1580 atmel_nand_disable(host);
740 1581
1582 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1583 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1584 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1585 PMERRLOC_DISABLE);
1586 pmecc_data_free(host);
1587 }
1588
1589 if (gpio_is_valid(host->board.det_pin))
1590 gpio_free(host->board.det_pin);
1591
1592 if (gpio_is_valid(host->board.enable_pin))
1593 gpio_free(host->board.enable_pin);
1594
1595 if (gpio_is_valid(host->board.rdy_pin))
1596 gpio_free(host->board.rdy_pin);
1597
741 if (host->ecc) 1598 if (host->ecc)
742 iounmap(host->ecc); 1599 iounmap(host->ecc);
1600 if (host->pmecc_rom_base)
1601 iounmap(host->pmecc_rom_base);
1602 if (host->pmerrloc_base)
1603 iounmap(host->pmerrloc_base);
743 1604
744 if (host->dma_chan) 1605 if (host->dma_chan)
745 dma_release_channel(host->dma_chan); 1606 dma_release_channel(host->dma_chan);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 00:29:50 -0500