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path: root/drivers/mtd/chips/jedec_probe.c
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Diffstat (limited to 'drivers/mtd/chips/jedec_probe.c')
-rw-r--r--drivers/mtd/chips/jedec_probe.c1376
1 files changed, 596 insertions, 780 deletions
diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c
index a67b23b87fc0..4be51a86a85c 100644
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -194,8 +194,8 @@ enum uaddr {
194 194
195 195
196struct unlock_addr { 196struct unlock_addr {
197 u32 addr1; 197 uint32_t addr1;
198 u32 addr2; 198 uint32_t addr2;
199}; 199};
200 200
201 201
@@ -246,16 +246,16 @@ static const struct unlock_addr unlock_addrs[] = {
246 } 246 }
247}; 247};
248 248
249
250struct amd_flash_info { 249struct amd_flash_info {
251 const __u16 mfr_id;
252 const __u16 dev_id;
253 const char *name; 250 const char *name;
254 const int DevSize; 251 const uint16_t mfr_id;
255 const int NumEraseRegions; 252 const uint16_t dev_id;
256 const int CmdSet; 253 const uint8_t dev_size;
257 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */ 254 const uint8_t nr_regions;
258 const ulong regions[6]; 255 const uint16_t cmd_set;
256 const uint32_t regions[6];
257 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */
258 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */
259}; 259};
260 260
261#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 261#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
@@ -280,12 +280,11 @@ static const struct amd_flash_info jedec_table[] = {
280 .mfr_id = MANUFACTURER_AMD, 280 .mfr_id = MANUFACTURER_AMD,
281 .dev_id = AM29F032B, 281 .dev_id = AM29F032B,
282 .name = "AMD AM29F032B", 282 .name = "AMD AM29F032B",
283 .uaddr = { 283 .uaddr = MTD_UADDR_0x0555_0x02AA,
284 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 284 .devtypes = CFI_DEVICETYPE_X8,
285 }, 285 .dev_size = SIZE_4MiB,
286 .DevSize = SIZE_4MiB, 286 .cmd_set = P_ID_AMD_STD,
287 .CmdSet = P_ID_AMD_STD, 287 .nr_regions = 1,
288 .NumEraseRegions= 1,
289 .regions = { 288 .regions = {
290 ERASEINFO(0x10000,64) 289 ERASEINFO(0x10000,64)
291 } 290 }
@@ -293,13 +292,11 @@ static const struct amd_flash_info jedec_table[] = {
293 .mfr_id = MANUFACTURER_AMD, 292 .mfr_id = MANUFACTURER_AMD,
294 .dev_id = AM29LV160DT, 293 .dev_id = AM29LV160DT,
295 .name = "AMD AM29LV160DT", 294 .name = "AMD AM29LV160DT",
296 .uaddr = { 295 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
297 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 296 .uaddr = MTD_UADDR_0x0AAA_0x0555,
298 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 297 .dev_size = SIZE_2MiB,
299 }, 298 .cmd_set = P_ID_AMD_STD,
300 .DevSize = SIZE_2MiB, 299 .nr_regions = 4,
301 .CmdSet = P_ID_AMD_STD,
302 .NumEraseRegions= 4,
303 .regions = { 300 .regions = {
304 ERASEINFO(0x10000,31), 301 ERASEINFO(0x10000,31),
305 ERASEINFO(0x08000,1), 302 ERASEINFO(0x08000,1),
@@ -310,13 +307,11 @@ static const struct amd_flash_info jedec_table[] = {
310 .mfr_id = MANUFACTURER_AMD, 307 .mfr_id = MANUFACTURER_AMD,
311 .dev_id = AM29LV160DB, 308 .dev_id = AM29LV160DB,
312 .name = "AMD AM29LV160DB", 309 .name = "AMD AM29LV160DB",
313 .uaddr = { 310 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
314 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 311 .uaddr = MTD_UADDR_0x0AAA_0x0555,
315 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 312 .dev_size = SIZE_2MiB,
316 }, 313 .cmd_set = P_ID_AMD_STD,
317 .DevSize = SIZE_2MiB, 314 .nr_regions = 4,
318 .CmdSet = P_ID_AMD_STD,
319 .NumEraseRegions= 4,
320 .regions = { 315 .regions = {
321 ERASEINFO(0x04000,1), 316 ERASEINFO(0x04000,1),
322 ERASEINFO(0x02000,2), 317 ERASEINFO(0x02000,2),
@@ -327,13 +322,11 @@ static const struct amd_flash_info jedec_table[] = {
327 .mfr_id = MANUFACTURER_AMD, 322 .mfr_id = MANUFACTURER_AMD,
328 .dev_id = AM29LV400BB, 323 .dev_id = AM29LV400BB,
329 .name = "AMD AM29LV400BB", 324 .name = "AMD AM29LV400BB",
330 .uaddr = { 325 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
331 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 326 .uaddr = MTD_UADDR_0x0AAA_0x0555,
332 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 327 .dev_size = SIZE_512KiB,
333 }, 328 .cmd_set = P_ID_AMD_STD,
334 .DevSize = SIZE_512KiB, 329 .nr_regions = 4,
335 .CmdSet = P_ID_AMD_STD,
336 .NumEraseRegions= 4,
337 .regions = { 330 .regions = {
338 ERASEINFO(0x04000,1), 331 ERASEINFO(0x04000,1),
339 ERASEINFO(0x02000,2), 332 ERASEINFO(0x02000,2),
@@ -344,13 +337,11 @@ static const struct amd_flash_info jedec_table[] = {
344 .mfr_id = MANUFACTURER_AMD, 337 .mfr_id = MANUFACTURER_AMD,
345 .dev_id = AM29LV400BT, 338 .dev_id = AM29LV400BT,
346 .name = "AMD AM29LV400BT", 339 .name = "AMD AM29LV400BT",
347 .uaddr = { 340 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
348 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 341 .uaddr = MTD_UADDR_0x0AAA_0x0555,
349 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 342 .dev_size = SIZE_512KiB,
350 }, 343 .cmd_set = P_ID_AMD_STD,
351 .DevSize = SIZE_512KiB, 344 .nr_regions = 4,
352 .CmdSet = P_ID_AMD_STD,
353 .NumEraseRegions= 4,
354 .regions = { 345 .regions = {
355 ERASEINFO(0x10000,7), 346 ERASEINFO(0x10000,7),
356 ERASEINFO(0x08000,1), 347 ERASEINFO(0x08000,1),
@@ -361,13 +352,11 @@ static const struct amd_flash_info jedec_table[] = {
361 .mfr_id = MANUFACTURER_AMD, 352 .mfr_id = MANUFACTURER_AMD,
362 .dev_id = AM29LV800BB, 353 .dev_id = AM29LV800BB,
363 .name = "AMD AM29LV800BB", 354 .name = "AMD AM29LV800BB",
364 .uaddr = { 355 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
365 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 356 .uaddr = MTD_UADDR_0x0AAA_0x0555,
366 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 357 .dev_size = SIZE_1MiB,
367 }, 358 .cmd_set = P_ID_AMD_STD,
368 .DevSize = SIZE_1MiB, 359 .nr_regions = 4,
369 .CmdSet = P_ID_AMD_STD,
370 .NumEraseRegions= 4,
371 .regions = { 360 .regions = {
372 ERASEINFO(0x04000,1), 361 ERASEINFO(0x04000,1),
373 ERASEINFO(0x02000,2), 362 ERASEINFO(0x02000,2),
@@ -379,13 +368,11 @@ static const struct amd_flash_info jedec_table[] = {
379 .mfr_id = MANUFACTURER_AMD, 368 .mfr_id = MANUFACTURER_AMD,
380 .dev_id = AM29DL800BB, 369 .dev_id = AM29DL800BB,
381 .name = "AMD AM29DL800BB", 370 .name = "AMD AM29DL800BB",
382 .uaddr = { 371 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
383 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 372 .uaddr = MTD_UADDR_0x0AAA_0x0555,
384 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 373 .dev_size = SIZE_1MiB,
385 }, 374 .cmd_set = P_ID_AMD_STD,
386 .DevSize = SIZE_1MiB, 375 .nr_regions = 6,
387 .CmdSet = P_ID_AMD_STD,
388 .NumEraseRegions= 6,
389 .regions = { 376 .regions = {
390 ERASEINFO(0x04000,1), 377 ERASEINFO(0x04000,1),
391 ERASEINFO(0x08000,1), 378 ERASEINFO(0x08000,1),
@@ -398,13 +385,11 @@ static const struct amd_flash_info jedec_table[] = {
398 .mfr_id = MANUFACTURER_AMD, 385 .mfr_id = MANUFACTURER_AMD,
399 .dev_id = AM29DL800BT, 386 .dev_id = AM29DL800BT,
400 .name = "AMD AM29DL800BT", 387 .name = "AMD AM29DL800BT",
401 .uaddr = { 388 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
402 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 389 .uaddr = MTD_UADDR_0x0AAA_0x0555,
403 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 390 .dev_size = SIZE_1MiB,
404 }, 391 .cmd_set = P_ID_AMD_STD,
405 .DevSize = SIZE_1MiB, 392 .nr_regions = 6,
406 .CmdSet = P_ID_AMD_STD,
407 .NumEraseRegions= 6,
408 .regions = { 393 .regions = {
409 ERASEINFO(0x10000,14), 394 ERASEINFO(0x10000,14),
410 ERASEINFO(0x04000,1), 395 ERASEINFO(0x04000,1),
@@ -417,13 +402,11 @@ static const struct amd_flash_info jedec_table[] = {
417 .mfr_id = MANUFACTURER_AMD, 402 .mfr_id = MANUFACTURER_AMD,
418 .dev_id = AM29F800BB, 403 .dev_id = AM29F800BB,
419 .name = "AMD AM29F800BB", 404 .name = "AMD AM29F800BB",
420 .uaddr = { 405 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
421 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 406 .uaddr = MTD_UADDR_0x0AAA_0x0555,
422 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 407 .dev_size = SIZE_1MiB,
423 }, 408 .cmd_set = P_ID_AMD_STD,
424 .DevSize = SIZE_1MiB, 409 .nr_regions = 4,
425 .CmdSet = P_ID_AMD_STD,
426 .NumEraseRegions= 4,
427 .regions = { 410 .regions = {
428 ERASEINFO(0x04000,1), 411 ERASEINFO(0x04000,1),
429 ERASEINFO(0x02000,2), 412 ERASEINFO(0x02000,2),
@@ -434,13 +417,11 @@ static const struct amd_flash_info jedec_table[] = {
434 .mfr_id = MANUFACTURER_AMD, 417 .mfr_id = MANUFACTURER_AMD,
435 .dev_id = AM29LV800BT, 418 .dev_id = AM29LV800BT,
436 .name = "AMD AM29LV800BT", 419 .name = "AMD AM29LV800BT",
437 .uaddr = { 420 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
438 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 421 .uaddr = MTD_UADDR_0x0AAA_0x0555,
439 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 422 .dev_size = SIZE_1MiB,
440 }, 423 .cmd_set = P_ID_AMD_STD,
441 .DevSize = SIZE_1MiB, 424 .nr_regions = 4,
442 .CmdSet = P_ID_AMD_STD,
443 .NumEraseRegions= 4,
444 .regions = { 425 .regions = {
445 ERASEINFO(0x10000,15), 426 ERASEINFO(0x10000,15),
446 ERASEINFO(0x08000,1), 427 ERASEINFO(0x08000,1),
@@ -451,13 +432,11 @@ static const struct amd_flash_info jedec_table[] = {
451 .mfr_id = MANUFACTURER_AMD, 432 .mfr_id = MANUFACTURER_AMD,
452 .dev_id = AM29F800BT, 433 .dev_id = AM29F800BT,
453 .name = "AMD AM29F800BT", 434 .name = "AMD AM29F800BT",
454 .uaddr = { 435 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
455 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 436 .uaddr = MTD_UADDR_0x0AAA_0x0555,
456 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 437 .dev_size = SIZE_1MiB,
457 }, 438 .cmd_set = P_ID_AMD_STD,
458 .DevSize = SIZE_1MiB, 439 .nr_regions = 4,
459 .CmdSet = P_ID_AMD_STD,
460 .NumEraseRegions= 4,
461 .regions = { 440 .regions = {
462 ERASEINFO(0x10000,15), 441 ERASEINFO(0x10000,15),
463 ERASEINFO(0x08000,1), 442 ERASEINFO(0x08000,1),
@@ -468,12 +447,11 @@ static const struct amd_flash_info jedec_table[] = {
468 .mfr_id = MANUFACTURER_AMD, 447 .mfr_id = MANUFACTURER_AMD,
469 .dev_id = AM29F017D, 448 .dev_id = AM29F017D,
470 .name = "AMD AM29F017D", 449 .name = "AMD AM29F017D",
471 .uaddr = { 450 .devtypes = CFI_DEVICETYPE_X8,
472 [0] = MTD_UADDR_DONT_CARE /* x8 */ 451 .uaddr = MTD_UADDR_DONT_CARE,
473 }, 452 .dev_size = SIZE_2MiB,
474 .DevSize = SIZE_2MiB, 453 .cmd_set = P_ID_AMD_STD,
475 .CmdSet = P_ID_AMD_STD, 454 .nr_regions = 1,
476 .NumEraseRegions= 1,
477 .regions = { 455 .regions = {
478 ERASEINFO(0x10000,32), 456 ERASEINFO(0x10000,32),
479 } 457 }
@@ -481,12 +459,11 @@ static const struct amd_flash_info jedec_table[] = {
481 .mfr_id = MANUFACTURER_AMD, 459 .mfr_id = MANUFACTURER_AMD,
482 .dev_id = AM29F016D, 460 .dev_id = AM29F016D,
483 .name = "AMD AM29F016D", 461 .name = "AMD AM29F016D",
484 .uaddr = { 462 .devtypes = CFI_DEVICETYPE_X8,
485 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 463 .uaddr = MTD_UADDR_0x0555_0x02AA,
486 }, 464 .dev_size = SIZE_2MiB,
487 .DevSize = SIZE_2MiB, 465 .cmd_set = P_ID_AMD_STD,
488 .CmdSet = P_ID_AMD_STD, 466 .nr_regions = 1,
489 .NumEraseRegions= 1,
490 .regions = { 467 .regions = {
491 ERASEINFO(0x10000,32), 468 ERASEINFO(0x10000,32),
492 } 469 }
@@ -494,12 +471,11 @@ static const struct amd_flash_info jedec_table[] = {
494 .mfr_id = MANUFACTURER_AMD, 471 .mfr_id = MANUFACTURER_AMD,
495 .dev_id = AM29F080, 472 .dev_id = AM29F080,
496 .name = "AMD AM29F080", 473 .name = "AMD AM29F080",
497 .uaddr = { 474 .devtypes = CFI_DEVICETYPE_X8,
498 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 475 .uaddr = MTD_UADDR_0x0555_0x02AA,
499 }, 476 .dev_size = SIZE_1MiB,
500 .DevSize = SIZE_1MiB, 477 .cmd_set = P_ID_AMD_STD,
501 .CmdSet = P_ID_AMD_STD, 478 .nr_regions = 1,
502 .NumEraseRegions= 1,
503 .regions = { 479 .regions = {
504 ERASEINFO(0x10000,16), 480 ERASEINFO(0x10000,16),
505 } 481 }
@@ -507,12 +483,11 @@ static const struct amd_flash_info jedec_table[] = {
507 .mfr_id = MANUFACTURER_AMD, 483 .mfr_id = MANUFACTURER_AMD,
508 .dev_id = AM29F040, 484 .dev_id = AM29F040,
509 .name = "AMD AM29F040", 485 .name = "AMD AM29F040",
510 .uaddr = { 486 .devtypes = CFI_DEVICETYPE_X8,
511 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 487 .uaddr = MTD_UADDR_0x0555_0x02AA,
512 }, 488 .dev_size = SIZE_512KiB,
513 .DevSize = SIZE_512KiB, 489 .cmd_set = P_ID_AMD_STD,
514 .CmdSet = P_ID_AMD_STD, 490 .nr_regions = 1,
515 .NumEraseRegions= 1,
516 .regions = { 491 .regions = {
517 ERASEINFO(0x10000,8), 492 ERASEINFO(0x10000,8),
518 } 493 }
@@ -520,12 +495,11 @@ static const struct amd_flash_info jedec_table[] = {
520 .mfr_id = MANUFACTURER_AMD, 495 .mfr_id = MANUFACTURER_AMD,
521 .dev_id = AM29LV040B, 496 .dev_id = AM29LV040B,
522 .name = "AMD AM29LV040B", 497 .name = "AMD AM29LV040B",
523 .uaddr = { 498 .devtypes = CFI_DEVICETYPE_X8,
524 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 499 .uaddr = MTD_UADDR_0x0555_0x02AA,
525 }, 500 .dev_size = SIZE_512KiB,
526 .DevSize = SIZE_512KiB, 501 .cmd_set = P_ID_AMD_STD,
527 .CmdSet = P_ID_AMD_STD, 502 .nr_regions = 1,
528 .NumEraseRegions= 1,
529 .regions = { 503 .regions = {
530 ERASEINFO(0x10000,8), 504 ERASEINFO(0x10000,8),
531 } 505 }
@@ -533,12 +507,11 @@ static const struct amd_flash_info jedec_table[] = {
533 .mfr_id = MANUFACTURER_AMD, 507 .mfr_id = MANUFACTURER_AMD,
534 .dev_id = AM29F002T, 508 .dev_id = AM29F002T,
535 .name = "AMD AM29F002T", 509 .name = "AMD AM29F002T",
536 .uaddr = { 510 .devtypes = CFI_DEVICETYPE_X8,
537 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 511 .uaddr = MTD_UADDR_0x0555_0x02AA,
538 }, 512 .dev_size = SIZE_256KiB,
539 .DevSize = SIZE_256KiB, 513 .cmd_set = P_ID_AMD_STD,
540 .CmdSet = P_ID_AMD_STD, 514 .nr_regions = 4,
541 .NumEraseRegions= 4,
542 .regions = { 515 .regions = {
543 ERASEINFO(0x10000,3), 516 ERASEINFO(0x10000,3),
544 ERASEINFO(0x08000,1), 517 ERASEINFO(0x08000,1),
@@ -549,12 +522,11 @@ static const struct amd_flash_info jedec_table[] = {
549 .mfr_id = MANUFACTURER_ATMEL, 522 .mfr_id = MANUFACTURER_ATMEL,
550 .dev_id = AT49BV512, 523 .dev_id = AT49BV512,
551 .name = "Atmel AT49BV512", 524 .name = "Atmel AT49BV512",
552 .uaddr = { 525 .devtypes = CFI_DEVICETYPE_X8,
553 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 526 .uaddr = MTD_UADDR_0x5555_0x2AAA,
554 }, 527 .dev_size = SIZE_64KiB,
555 .DevSize = SIZE_64KiB, 528 .cmd_set = P_ID_AMD_STD,
556 .CmdSet = P_ID_AMD_STD, 529 .nr_regions = 1,
557 .NumEraseRegions= 1,
558 .regions = { 530 .regions = {
559 ERASEINFO(0x10000,1) 531 ERASEINFO(0x10000,1)
560 } 532 }
@@ -562,12 +534,11 @@ static const struct amd_flash_info jedec_table[] = {
562 .mfr_id = MANUFACTURER_ATMEL, 534 .mfr_id = MANUFACTURER_ATMEL,
563 .dev_id = AT29LV512, 535 .dev_id = AT29LV512,
564 .name = "Atmel AT29LV512", 536 .name = "Atmel AT29LV512",
565 .uaddr = { 537 .devtypes = CFI_DEVICETYPE_X8,
566 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 538 .uaddr = MTD_UADDR_0x5555_0x2AAA,
567 }, 539 .dev_size = SIZE_64KiB,
568 .DevSize = SIZE_64KiB, 540 .cmd_set = P_ID_AMD_STD,
569 .CmdSet = P_ID_AMD_STD, 541 .nr_regions = 1,
570 .NumEraseRegions= 1,
571 .regions = { 542 .regions = {
572 ERASEINFO(0x80,256), 543 ERASEINFO(0x80,256),
573 ERASEINFO(0x80,256) 544 ERASEINFO(0x80,256)
@@ -576,13 +547,11 @@ static const struct amd_flash_info jedec_table[] = {
576 .mfr_id = MANUFACTURER_ATMEL, 547 .mfr_id = MANUFACTURER_ATMEL,
577 .dev_id = AT49BV16X, 548 .dev_id = AT49BV16X,
578 .name = "Atmel AT49BV16X", 549 .name = "Atmel AT49BV16X",
579 .uaddr = { 550 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
580 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */ 551 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
581 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */ 552 .dev_size = SIZE_2MiB,
582 }, 553 .cmd_set = P_ID_AMD_STD,
583 .DevSize = SIZE_2MiB, 554 .nr_regions = 2,
584 .CmdSet = P_ID_AMD_STD,
585 .NumEraseRegions= 2,
586 .regions = { 555 .regions = {
587 ERASEINFO(0x02000,8), 556 ERASEINFO(0x02000,8),
588 ERASEINFO(0x10000,31) 557 ERASEINFO(0x10000,31)
@@ -591,13 +560,11 @@ static const struct amd_flash_info jedec_table[] = {
591 .mfr_id = MANUFACTURER_ATMEL, 560 .mfr_id = MANUFACTURER_ATMEL,
592 .dev_id = AT49BV16XT, 561 .dev_id = AT49BV16XT,
593 .name = "Atmel AT49BV16XT", 562 .name = "Atmel AT49BV16XT",
594 .uaddr = { 563 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
595 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */ 564 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
596 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */ 565 .dev_size = SIZE_2MiB,
597 }, 566 .cmd_set = P_ID_AMD_STD,
598 .DevSize = SIZE_2MiB, 567 .nr_regions = 2,
599 .CmdSet = P_ID_AMD_STD,
600 .NumEraseRegions= 2,
601 .regions = { 568 .regions = {
602 ERASEINFO(0x10000,31), 569 ERASEINFO(0x10000,31),
603 ERASEINFO(0x02000,8) 570 ERASEINFO(0x02000,8)
@@ -606,13 +573,11 @@ static const struct amd_flash_info jedec_table[] = {
606 .mfr_id = MANUFACTURER_ATMEL, 573 .mfr_id = MANUFACTURER_ATMEL,
607 .dev_id = AT49BV32X, 574 .dev_id = AT49BV32X,
608 .name = "Atmel AT49BV32X", 575 .name = "Atmel AT49BV32X",
609 .uaddr = { 576 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
610 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */ 577 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
611 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */ 578 .dev_size = SIZE_4MiB,
612 }, 579 .cmd_set = P_ID_AMD_STD,
613 .DevSize = SIZE_4MiB, 580 .nr_regions = 2,
614 .CmdSet = P_ID_AMD_STD,
615 .NumEraseRegions= 2,
616 .regions = { 581 .regions = {
617 ERASEINFO(0x02000,8), 582 ERASEINFO(0x02000,8),
618 ERASEINFO(0x10000,63) 583 ERASEINFO(0x10000,63)
@@ -621,13 +586,11 @@ static const struct amd_flash_info jedec_table[] = {
621 .mfr_id = MANUFACTURER_ATMEL, 586 .mfr_id = MANUFACTURER_ATMEL,
622 .dev_id = AT49BV32XT, 587 .dev_id = AT49BV32XT,
623 .name = "Atmel AT49BV32XT", 588 .name = "Atmel AT49BV32XT",
624 .uaddr = { 589 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
625 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */ 590 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
626 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */ 591 .dev_size = SIZE_4MiB,
627 }, 592 .cmd_set = P_ID_AMD_STD,
628 .DevSize = SIZE_4MiB, 593 .nr_regions = 2,
629 .CmdSet = P_ID_AMD_STD,
630 .NumEraseRegions= 2,
631 .regions = { 594 .regions = {
632 ERASEINFO(0x10000,63), 595 ERASEINFO(0x10000,63),
633 ERASEINFO(0x02000,8) 596 ERASEINFO(0x02000,8)
@@ -636,12 +599,11 @@ static const struct amd_flash_info jedec_table[] = {
636 .mfr_id = MANUFACTURER_FUJITSU, 599 .mfr_id = MANUFACTURER_FUJITSU,
637 .dev_id = MBM29F040C, 600 .dev_id = MBM29F040C,
638 .name = "Fujitsu MBM29F040C", 601 .name = "Fujitsu MBM29F040C",
639 .uaddr = { 602 .devtypes = CFI_DEVICETYPE_X8,
640 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 603 .uaddr = MTD_UADDR_0x0AAA_0x0555,
641 }, 604 .dev_size = SIZE_512KiB,
642 .DevSize = SIZE_512KiB, 605 .cmd_set = P_ID_AMD_STD,
643 .CmdSet = P_ID_AMD_STD, 606 .nr_regions = 1,
644 .NumEraseRegions= 1,
645 .regions = { 607 .regions = {
646 ERASEINFO(0x10000,8) 608 ERASEINFO(0x10000,8)
647 } 609 }
@@ -649,13 +611,11 @@ static const struct amd_flash_info jedec_table[] = {
649 .mfr_id = MANUFACTURER_FUJITSU, 611 .mfr_id = MANUFACTURER_FUJITSU,
650 .dev_id = MBM29F800BA, 612 .dev_id = MBM29F800BA,
651 .name = "Fujitsu MBM29F800BA", 613 .name = "Fujitsu MBM29F800BA",
652 .uaddr = { 614 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
653 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 615 .uaddr = MTD_UADDR_0x0AAA_0x0555,
654 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 616 .dev_size = SIZE_1MiB,
655 }, 617 .cmd_set = P_ID_AMD_STD,
656 .DevSize = SIZE_1MiB, 618 .nr_regions = 4,
657 .CmdSet = P_ID_AMD_STD,
658 .NumEraseRegions= 4,
659 .regions = { 619 .regions = {
660 ERASEINFO(0x04000,1), 620 ERASEINFO(0x04000,1),
661 ERASEINFO(0x02000,2), 621 ERASEINFO(0x02000,2),
@@ -666,12 +626,11 @@ static const struct amd_flash_info jedec_table[] = {
666 .mfr_id = MANUFACTURER_FUJITSU, 626 .mfr_id = MANUFACTURER_FUJITSU,
667 .dev_id = MBM29LV650UE, 627 .dev_id = MBM29LV650UE,
668 .name = "Fujitsu MBM29LV650UE", 628 .name = "Fujitsu MBM29LV650UE",
669 .uaddr = { 629 .devtypes = CFI_DEVICETYPE_X8,
670 [0] = MTD_UADDR_DONT_CARE /* x16 */ 630 .uaddr = MTD_UADDR_DONT_CARE,
671 }, 631 .dev_size = SIZE_8MiB,
672 .DevSize = SIZE_8MiB, 632 .cmd_set = P_ID_AMD_STD,
673 .CmdSet = P_ID_AMD_STD, 633 .nr_regions = 1,
674 .NumEraseRegions= 1,
675 .regions = { 634 .regions = {
676 ERASEINFO(0x10000,128) 635 ERASEINFO(0x10000,128)
677 } 636 }
@@ -679,13 +638,11 @@ static const struct amd_flash_info jedec_table[] = {
679 .mfr_id = MANUFACTURER_FUJITSU, 638 .mfr_id = MANUFACTURER_FUJITSU,
680 .dev_id = MBM29LV320TE, 639 .dev_id = MBM29LV320TE,
681 .name = "Fujitsu MBM29LV320TE", 640 .name = "Fujitsu MBM29LV320TE",
682 .uaddr = { 641 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
683 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 642 .uaddr = MTD_UADDR_0x0AAA_0x0555,
684 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 643 .dev_size = SIZE_4MiB,
685 }, 644 .cmd_set = P_ID_AMD_STD,
686 .DevSize = SIZE_4MiB, 645 .nr_regions = 2,
687 .CmdSet = P_ID_AMD_STD,
688 .NumEraseRegions= 2,
689 .regions = { 646 .regions = {
690 ERASEINFO(0x10000,63), 647 ERASEINFO(0x10000,63),
691 ERASEINFO(0x02000,8) 648 ERASEINFO(0x02000,8)
@@ -694,13 +651,11 @@ static const struct amd_flash_info jedec_table[] = {
694 .mfr_id = MANUFACTURER_FUJITSU, 651 .mfr_id = MANUFACTURER_FUJITSU,
695 .dev_id = MBM29LV320BE, 652 .dev_id = MBM29LV320BE,
696 .name = "Fujitsu MBM29LV320BE", 653 .name = "Fujitsu MBM29LV320BE",
697 .uaddr = { 654 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
698 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 655 .uaddr = MTD_UADDR_0x0AAA_0x0555,
699 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 656 .dev_size = SIZE_4MiB,
700 }, 657 .cmd_set = P_ID_AMD_STD,
701 .DevSize = SIZE_4MiB, 658 .nr_regions = 2,
702 .CmdSet = P_ID_AMD_STD,
703 .NumEraseRegions= 2,
704 .regions = { 659 .regions = {
705 ERASEINFO(0x02000,8), 660 ERASEINFO(0x02000,8),
706 ERASEINFO(0x10000,63) 661 ERASEINFO(0x10000,63)
@@ -709,13 +664,11 @@ static const struct amd_flash_info jedec_table[] = {
709 .mfr_id = MANUFACTURER_FUJITSU, 664 .mfr_id = MANUFACTURER_FUJITSU,
710 .dev_id = MBM29LV160TE, 665 .dev_id = MBM29LV160TE,
711 .name = "Fujitsu MBM29LV160TE", 666 .name = "Fujitsu MBM29LV160TE",
712 .uaddr = { 667 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
713 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 668 .uaddr = MTD_UADDR_0x0AAA_0x0555,
714 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 669 .dev_size = SIZE_2MiB,
715 }, 670 .cmd_set = P_ID_AMD_STD,
716 .DevSize = SIZE_2MiB, 671 .nr_regions = 4,
717 .CmdSet = P_ID_AMD_STD,
718 .NumEraseRegions= 4,
719 .regions = { 672 .regions = {
720 ERASEINFO(0x10000,31), 673 ERASEINFO(0x10000,31),
721 ERASEINFO(0x08000,1), 674 ERASEINFO(0x08000,1),
@@ -726,13 +679,11 @@ static const struct amd_flash_info jedec_table[] = {
726 .mfr_id = MANUFACTURER_FUJITSU, 679 .mfr_id = MANUFACTURER_FUJITSU,
727 .dev_id = MBM29LV160BE, 680 .dev_id = MBM29LV160BE,
728 .name = "Fujitsu MBM29LV160BE", 681 .name = "Fujitsu MBM29LV160BE",
729 .uaddr = { 682 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
730 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 683 .uaddr = MTD_UADDR_0x0AAA_0x0555,
731 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 684 .dev_size = SIZE_2MiB,
732 }, 685 .cmd_set = P_ID_AMD_STD,
733 .DevSize = SIZE_2MiB, 686 .nr_regions = 4,
734 .CmdSet = P_ID_AMD_STD,
735 .NumEraseRegions= 4,
736 .regions = { 687 .regions = {
737 ERASEINFO(0x04000,1), 688 ERASEINFO(0x04000,1),
738 ERASEINFO(0x02000,2), 689 ERASEINFO(0x02000,2),
@@ -743,13 +694,11 @@ static const struct amd_flash_info jedec_table[] = {
743 .mfr_id = MANUFACTURER_FUJITSU, 694 .mfr_id = MANUFACTURER_FUJITSU,
744 .dev_id = MBM29LV800BA, 695 .dev_id = MBM29LV800BA,
745 .name = "Fujitsu MBM29LV800BA", 696 .name = "Fujitsu MBM29LV800BA",
746 .uaddr = { 697 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
747 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 698 .uaddr = MTD_UADDR_0x0AAA_0x0555,
748 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 699 .dev_size = SIZE_1MiB,
749 }, 700 .cmd_set = P_ID_AMD_STD,
750 .DevSize = SIZE_1MiB, 701 .nr_regions = 4,
751 .CmdSet = P_ID_AMD_STD,
752 .NumEraseRegions= 4,
753 .regions = { 702 .regions = {
754 ERASEINFO(0x04000,1), 703 ERASEINFO(0x04000,1),
755 ERASEINFO(0x02000,2), 704 ERASEINFO(0x02000,2),
@@ -760,13 +709,11 @@ static const struct amd_flash_info jedec_table[] = {
760 .mfr_id = MANUFACTURER_FUJITSU, 709 .mfr_id = MANUFACTURER_FUJITSU,
761 .dev_id = MBM29LV800TA, 710 .dev_id = MBM29LV800TA,
762 .name = "Fujitsu MBM29LV800TA", 711 .name = "Fujitsu MBM29LV800TA",
763 .uaddr = { 712 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
764 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 713 .uaddr = MTD_UADDR_0x0AAA_0x0555,
765 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 714 .dev_size = SIZE_1MiB,
766 }, 715 .cmd_set = P_ID_AMD_STD,
767 .DevSize = SIZE_1MiB, 716 .nr_regions = 4,
768 .CmdSet = P_ID_AMD_STD,
769 .NumEraseRegions= 4,
770 .regions = { 717 .regions = {
771 ERASEINFO(0x10000,15), 718 ERASEINFO(0x10000,15),
772 ERASEINFO(0x08000,1), 719 ERASEINFO(0x08000,1),
@@ -777,13 +724,11 @@ static const struct amd_flash_info jedec_table[] = {
777 .mfr_id = MANUFACTURER_FUJITSU, 724 .mfr_id = MANUFACTURER_FUJITSU,
778 .dev_id = MBM29LV400BC, 725 .dev_id = MBM29LV400BC,
779 .name = "Fujitsu MBM29LV400BC", 726 .name = "Fujitsu MBM29LV400BC",
780 .uaddr = { 727 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
781 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 728 .uaddr = MTD_UADDR_0x0AAA_0x0555,
782 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 729 .dev_size = SIZE_512KiB,
783 }, 730 .cmd_set = P_ID_AMD_STD,
784 .DevSize = SIZE_512KiB, 731 .nr_regions = 4,
785 .CmdSet = P_ID_AMD_STD,
786 .NumEraseRegions= 4,
787 .regions = { 732 .regions = {
788 ERASEINFO(0x04000,1), 733 ERASEINFO(0x04000,1),
789 ERASEINFO(0x02000,2), 734 ERASEINFO(0x02000,2),
@@ -794,13 +739,11 @@ static const struct amd_flash_info jedec_table[] = {
794 .mfr_id = MANUFACTURER_FUJITSU, 739 .mfr_id = MANUFACTURER_FUJITSU,
795 .dev_id = MBM29LV400TC, 740 .dev_id = MBM29LV400TC,
796 .name = "Fujitsu MBM29LV400TC", 741 .name = "Fujitsu MBM29LV400TC",
797 .uaddr = { 742 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
798 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 743 .uaddr = MTD_UADDR_0x0AAA_0x0555,
799 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 744 .dev_size = SIZE_512KiB,
800 }, 745 .cmd_set = P_ID_AMD_STD,
801 .DevSize = SIZE_512KiB, 746 .nr_regions = 4,
802 .CmdSet = P_ID_AMD_STD,
803 .NumEraseRegions= 4,
804 .regions = { 747 .regions = {
805 ERASEINFO(0x10000,7), 748 ERASEINFO(0x10000,7),
806 ERASEINFO(0x08000,1), 749 ERASEINFO(0x08000,1),
@@ -811,12 +754,11 @@ static const struct amd_flash_info jedec_table[] = {
811 .mfr_id = MANUFACTURER_HYUNDAI, 754 .mfr_id = MANUFACTURER_HYUNDAI,
812 .dev_id = HY29F002T, 755 .dev_id = HY29F002T,
813 .name = "Hyundai HY29F002T", 756 .name = "Hyundai HY29F002T",
814 .uaddr = { 757 .devtypes = CFI_DEVICETYPE_X8,
815 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 758 .uaddr = MTD_UADDR_0x0555_0x02AA,
816 }, 759 .dev_size = SIZE_256KiB,
817 .DevSize = SIZE_256KiB, 760 .cmd_set = P_ID_AMD_STD,
818 .CmdSet = P_ID_AMD_STD, 761 .nr_regions = 4,
819 .NumEraseRegions= 4,
820 .regions = { 762 .regions = {
821 ERASEINFO(0x10000,3), 763 ERASEINFO(0x10000,3),
822 ERASEINFO(0x08000,1), 764 ERASEINFO(0x08000,1),
@@ -827,12 +769,11 @@ static const struct amd_flash_info jedec_table[] = {
827 .mfr_id = MANUFACTURER_INTEL, 769 .mfr_id = MANUFACTURER_INTEL,
828 .dev_id = I28F004B3B, 770 .dev_id = I28F004B3B,
829 .name = "Intel 28F004B3B", 771 .name = "Intel 28F004B3B",
830 .uaddr = { 772 .devtypes = CFI_DEVICETYPE_X8,
831 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 773 .uaddr = MTD_UADDR_UNNECESSARY,
832 }, 774 .dev_size = SIZE_512KiB,
833 .DevSize = SIZE_512KiB, 775 .cmd_set = P_ID_INTEL_STD,
834 .CmdSet = P_ID_INTEL_STD, 776 .nr_regions = 2,
835 .NumEraseRegions= 2,
836 .regions = { 777 .regions = {
837 ERASEINFO(0x02000, 8), 778 ERASEINFO(0x02000, 8),
838 ERASEINFO(0x10000, 7), 779 ERASEINFO(0x10000, 7),
@@ -841,12 +782,11 @@ static const struct amd_flash_info jedec_table[] = {
841 .mfr_id = MANUFACTURER_INTEL, 782 .mfr_id = MANUFACTURER_INTEL,
842 .dev_id = I28F004B3T, 783 .dev_id = I28F004B3T,
843 .name = "Intel 28F004B3T", 784 .name = "Intel 28F004B3T",
844 .uaddr = { 785 .devtypes = CFI_DEVICETYPE_X8,
845 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 786 .uaddr = MTD_UADDR_UNNECESSARY,
846 }, 787 .dev_size = SIZE_512KiB,
847 .DevSize = SIZE_512KiB, 788 .cmd_set = P_ID_INTEL_STD,
848 .CmdSet = P_ID_INTEL_STD, 789 .nr_regions = 2,
849 .NumEraseRegions= 2,
850 .regions = { 790 .regions = {
851 ERASEINFO(0x10000, 7), 791 ERASEINFO(0x10000, 7),
852 ERASEINFO(0x02000, 8), 792 ERASEINFO(0x02000, 8),
@@ -855,13 +795,11 @@ static const struct amd_flash_info jedec_table[] = {
855 .mfr_id = MANUFACTURER_INTEL, 795 .mfr_id = MANUFACTURER_INTEL,
856 .dev_id = I28F400B3B, 796 .dev_id = I28F400B3B,
857 .name = "Intel 28F400B3B", 797 .name = "Intel 28F400B3B",
858 .uaddr = { 798 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
859 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 799 .uaddr = MTD_UADDR_UNNECESSARY,
860 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 800 .dev_size = SIZE_512KiB,
861 }, 801 .cmd_set = P_ID_INTEL_STD,
862 .DevSize = SIZE_512KiB, 802 .nr_regions = 2,
863 .CmdSet = P_ID_INTEL_STD,
864 .NumEraseRegions= 2,
865 .regions = { 803 .regions = {
866 ERASEINFO(0x02000, 8), 804 ERASEINFO(0x02000, 8),
867 ERASEINFO(0x10000, 7), 805 ERASEINFO(0x10000, 7),
@@ -870,13 +808,11 @@ static const struct amd_flash_info jedec_table[] = {
870 .mfr_id = MANUFACTURER_INTEL, 808 .mfr_id = MANUFACTURER_INTEL,
871 .dev_id = I28F400B3T, 809 .dev_id = I28F400B3T,
872 .name = "Intel 28F400B3T", 810 .name = "Intel 28F400B3T",
873 .uaddr = { 811 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
874 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 812 .uaddr = MTD_UADDR_UNNECESSARY,
875 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 813 .dev_size = SIZE_512KiB,
876 }, 814 .cmd_set = P_ID_INTEL_STD,
877 .DevSize = SIZE_512KiB, 815 .nr_regions = 2,
878 .CmdSet = P_ID_INTEL_STD,
879 .NumEraseRegions= 2,
880 .regions = { 816 .regions = {
881 ERASEINFO(0x10000, 7), 817 ERASEINFO(0x10000, 7),
882 ERASEINFO(0x02000, 8), 818 ERASEINFO(0x02000, 8),
@@ -885,12 +821,11 @@ static const struct amd_flash_info jedec_table[] = {
885 .mfr_id = MANUFACTURER_INTEL, 821 .mfr_id = MANUFACTURER_INTEL,
886 .dev_id = I28F008B3B, 822 .dev_id = I28F008B3B,
887 .name = "Intel 28F008B3B", 823 .name = "Intel 28F008B3B",
888 .uaddr = { 824 .devtypes = CFI_DEVICETYPE_X8,
889 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 825 .uaddr = MTD_UADDR_UNNECESSARY,
890 }, 826 .dev_size = SIZE_1MiB,
891 .DevSize = SIZE_1MiB, 827 .cmd_set = P_ID_INTEL_STD,
892 .CmdSet = P_ID_INTEL_STD, 828 .nr_regions = 2,
893 .NumEraseRegions= 2,
894 .regions = { 829 .regions = {
895 ERASEINFO(0x02000, 8), 830 ERASEINFO(0x02000, 8),
896 ERASEINFO(0x10000, 15), 831 ERASEINFO(0x10000, 15),
@@ -899,12 +834,11 @@ static const struct amd_flash_info jedec_table[] = {
899 .mfr_id = MANUFACTURER_INTEL, 834 .mfr_id = MANUFACTURER_INTEL,
900 .dev_id = I28F008B3T, 835 .dev_id = I28F008B3T,
901 .name = "Intel 28F008B3T", 836 .name = "Intel 28F008B3T",
902 .uaddr = { 837 .devtypes = CFI_DEVICETYPE_X8,
903 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 838 .uaddr = MTD_UADDR_UNNECESSARY,
904 }, 839 .dev_size = SIZE_1MiB,
905 .DevSize = SIZE_1MiB, 840 .cmd_set = P_ID_INTEL_STD,
906 .CmdSet = P_ID_INTEL_STD, 841 .nr_regions = 2,
907 .NumEraseRegions= 2,
908 .regions = { 842 .regions = {
909 ERASEINFO(0x10000, 15), 843 ERASEINFO(0x10000, 15),
910 ERASEINFO(0x02000, 8), 844 ERASEINFO(0x02000, 8),
@@ -913,12 +847,11 @@ static const struct amd_flash_info jedec_table[] = {
913 .mfr_id = MANUFACTURER_INTEL, 847 .mfr_id = MANUFACTURER_INTEL,
914 .dev_id = I28F008S5, 848 .dev_id = I28F008S5,
915 .name = "Intel 28F008S5", 849 .name = "Intel 28F008S5",
916 .uaddr = { 850 .devtypes = CFI_DEVICETYPE_X8,
917 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 851 .uaddr = MTD_UADDR_UNNECESSARY,
918 }, 852 .dev_size = SIZE_1MiB,
919 .DevSize = SIZE_1MiB, 853 .cmd_set = P_ID_INTEL_EXT,
920 .CmdSet = P_ID_INTEL_EXT, 854 .nr_regions = 1,
921 .NumEraseRegions= 1,
922 .regions = { 855 .regions = {
923 ERASEINFO(0x10000,16), 856 ERASEINFO(0x10000,16),
924 } 857 }
@@ -926,12 +859,11 @@ static const struct amd_flash_info jedec_table[] = {
926 .mfr_id = MANUFACTURER_INTEL, 859 .mfr_id = MANUFACTURER_INTEL,
927 .dev_id = I28F016S5, 860 .dev_id = I28F016S5,
928 .name = "Intel 28F016S5", 861 .name = "Intel 28F016S5",
929 .uaddr = { 862 .devtypes = CFI_DEVICETYPE_X8,
930 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 863 .uaddr = MTD_UADDR_UNNECESSARY,
931 }, 864 .dev_size = SIZE_2MiB,
932 .DevSize = SIZE_2MiB, 865 .cmd_set = P_ID_INTEL_EXT,
933 .CmdSet = P_ID_INTEL_EXT, 866 .nr_regions = 1,
934 .NumEraseRegions= 1,
935 .regions = { 867 .regions = {
936 ERASEINFO(0x10000,32), 868 ERASEINFO(0x10000,32),
937 } 869 }
@@ -939,12 +871,11 @@ static const struct amd_flash_info jedec_table[] = {
939 .mfr_id = MANUFACTURER_INTEL, 871 .mfr_id = MANUFACTURER_INTEL,
940 .dev_id = I28F008SA, 872 .dev_id = I28F008SA,
941 .name = "Intel 28F008SA", 873 .name = "Intel 28F008SA",
942 .uaddr = { 874 .devtypes = CFI_DEVICETYPE_X8,
943 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 875 .uaddr = MTD_UADDR_UNNECESSARY,
944 }, 876 .dev_size = SIZE_1MiB,
945 .DevSize = SIZE_1MiB, 877 .cmd_set = P_ID_INTEL_STD,
946 .CmdSet = P_ID_INTEL_STD, 878 .nr_regions = 1,
947 .NumEraseRegions= 1,
948 .regions = { 879 .regions = {
949 ERASEINFO(0x10000, 16), 880 ERASEINFO(0x10000, 16),
950 } 881 }
@@ -952,12 +883,11 @@ static const struct amd_flash_info jedec_table[] = {
952 .mfr_id = MANUFACTURER_INTEL, 883 .mfr_id = MANUFACTURER_INTEL,
953 .dev_id = I28F800B3B, 884 .dev_id = I28F800B3B,
954 .name = "Intel 28F800B3B", 885 .name = "Intel 28F800B3B",
955 .uaddr = { 886 .devtypes = CFI_DEVICETYPE_X16,
956 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 887 .uaddr = MTD_UADDR_UNNECESSARY,
957 }, 888 .dev_size = SIZE_1MiB,
958 .DevSize = SIZE_1MiB, 889 .cmd_set = P_ID_INTEL_STD,
959 .CmdSet = P_ID_INTEL_STD, 890 .nr_regions = 2,
960 .NumEraseRegions= 2,
961 .regions = { 891 .regions = {
962 ERASEINFO(0x02000, 8), 892 ERASEINFO(0x02000, 8),
963 ERASEINFO(0x10000, 15), 893 ERASEINFO(0x10000, 15),
@@ -966,12 +896,11 @@ static const struct amd_flash_info jedec_table[] = {
966 .mfr_id = MANUFACTURER_INTEL, 896 .mfr_id = MANUFACTURER_INTEL,
967 .dev_id = I28F800B3T, 897 .dev_id = I28F800B3T,
968 .name = "Intel 28F800B3T", 898 .name = "Intel 28F800B3T",
969 .uaddr = { 899 .devtypes = CFI_DEVICETYPE_X16,
970 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 900 .uaddr = MTD_UADDR_UNNECESSARY,
971 }, 901 .dev_size = SIZE_1MiB,
972 .DevSize = SIZE_1MiB, 902 .cmd_set = P_ID_INTEL_STD,
973 .CmdSet = P_ID_INTEL_STD, 903 .nr_regions = 2,
974 .NumEraseRegions= 2,
975 .regions = { 904 .regions = {
976 ERASEINFO(0x10000, 15), 905 ERASEINFO(0x10000, 15),
977 ERASEINFO(0x02000, 8), 906 ERASEINFO(0x02000, 8),
@@ -980,12 +909,11 @@ static const struct amd_flash_info jedec_table[] = {
980 .mfr_id = MANUFACTURER_INTEL, 909 .mfr_id = MANUFACTURER_INTEL,
981 .dev_id = I28F016B3B, 910 .dev_id = I28F016B3B,
982 .name = "Intel 28F016B3B", 911 .name = "Intel 28F016B3B",
983 .uaddr = { 912 .devtypes = CFI_DEVICETYPE_X8,
984 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 913 .uaddr = MTD_UADDR_UNNECESSARY,
985 }, 914 .dev_size = SIZE_2MiB,
986 .DevSize = SIZE_2MiB, 915 .cmd_set = P_ID_INTEL_STD,
987 .CmdSet = P_ID_INTEL_STD, 916 .nr_regions = 2,
988 .NumEraseRegions= 2,
989 .regions = { 917 .regions = {
990 ERASEINFO(0x02000, 8), 918 ERASEINFO(0x02000, 8),
991 ERASEINFO(0x10000, 31), 919 ERASEINFO(0x10000, 31),
@@ -994,12 +922,11 @@ static const struct amd_flash_info jedec_table[] = {
994 .mfr_id = MANUFACTURER_INTEL, 922 .mfr_id = MANUFACTURER_INTEL,
995 .dev_id = I28F016S3, 923 .dev_id = I28F016S3,
996 .name = "Intel I28F016S3", 924 .name = "Intel I28F016S3",
997 .uaddr = { 925 .devtypes = CFI_DEVICETYPE_X8,
998 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 926 .uaddr = MTD_UADDR_UNNECESSARY,
999 }, 927 .dev_size = SIZE_2MiB,
1000 .DevSize = SIZE_2MiB, 928 .cmd_set = P_ID_INTEL_STD,
1001 .CmdSet = P_ID_INTEL_STD, 929 .nr_regions = 1,
1002 .NumEraseRegions= 1,
1003 .regions = { 930 .regions = {
1004 ERASEINFO(0x10000, 32), 931 ERASEINFO(0x10000, 32),
1005 } 932 }
@@ -1007,12 +934,11 @@ static const struct amd_flash_info jedec_table[] = {
1007 .mfr_id = MANUFACTURER_INTEL, 934 .mfr_id = MANUFACTURER_INTEL,
1008 .dev_id = I28F016B3T, 935 .dev_id = I28F016B3T,
1009 .name = "Intel 28F016B3T", 936 .name = "Intel 28F016B3T",
1010 .uaddr = { 937 .devtypes = CFI_DEVICETYPE_X8,
1011 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 938 .uaddr = MTD_UADDR_UNNECESSARY,
1012 }, 939 .dev_size = SIZE_2MiB,
1013 .DevSize = SIZE_2MiB, 940 .cmd_set = P_ID_INTEL_STD,
1014 .CmdSet = P_ID_INTEL_STD, 941 .nr_regions = 2,
1015 .NumEraseRegions= 2,
1016 .regions = { 942 .regions = {
1017 ERASEINFO(0x10000, 31), 943 ERASEINFO(0x10000, 31),
1018 ERASEINFO(0x02000, 8), 944 ERASEINFO(0x02000, 8),
@@ -1021,12 +947,11 @@ static const struct amd_flash_info jedec_table[] = {
1021 .mfr_id = MANUFACTURER_INTEL, 947 .mfr_id = MANUFACTURER_INTEL,
1022 .dev_id = I28F160B3B, 948 .dev_id = I28F160B3B,
1023 .name = "Intel 28F160B3B", 949 .name = "Intel 28F160B3B",
1024 .uaddr = { 950 .devtypes = CFI_DEVICETYPE_X16,
1025 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 951 .uaddr = MTD_UADDR_UNNECESSARY,
1026 }, 952 .dev_size = SIZE_2MiB,
1027 .DevSize = SIZE_2MiB, 953 .cmd_set = P_ID_INTEL_STD,
1028 .CmdSet = P_ID_INTEL_STD, 954 .nr_regions = 2,
1029 .NumEraseRegions= 2,
1030 .regions = { 955 .regions = {
1031 ERASEINFO(0x02000, 8), 956 ERASEINFO(0x02000, 8),
1032 ERASEINFO(0x10000, 31), 957 ERASEINFO(0x10000, 31),
@@ -1035,12 +960,11 @@ static const struct amd_flash_info jedec_table[] = {
1035 .mfr_id = MANUFACTURER_INTEL, 960 .mfr_id = MANUFACTURER_INTEL,
1036 .dev_id = I28F160B3T, 961 .dev_id = I28F160B3T,
1037 .name = "Intel 28F160B3T", 962 .name = "Intel 28F160B3T",
1038 .uaddr = { 963 .devtypes = CFI_DEVICETYPE_X16,
1039 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 964 .uaddr = MTD_UADDR_UNNECESSARY,
1040 }, 965 .dev_size = SIZE_2MiB,
1041 .DevSize = SIZE_2MiB, 966 .cmd_set = P_ID_INTEL_STD,
1042 .CmdSet = P_ID_INTEL_STD, 967 .nr_regions = 2,
1043 .NumEraseRegions= 2,
1044 .regions = { 968 .regions = {
1045 ERASEINFO(0x10000, 31), 969 ERASEINFO(0x10000, 31),
1046 ERASEINFO(0x02000, 8), 970 ERASEINFO(0x02000, 8),
@@ -1049,12 +973,11 @@ static const struct amd_flash_info jedec_table[] = {
1049 .mfr_id = MANUFACTURER_INTEL, 973 .mfr_id = MANUFACTURER_INTEL,
1050 .dev_id = I28F320B3B, 974 .dev_id = I28F320B3B,
1051 .name = "Intel 28F320B3B", 975 .name = "Intel 28F320B3B",
1052 .uaddr = { 976 .devtypes = CFI_DEVICETYPE_X16,
1053 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 977 .uaddr = MTD_UADDR_UNNECESSARY,
1054 }, 978 .dev_size = SIZE_4MiB,
1055 .DevSize = SIZE_4MiB, 979 .cmd_set = P_ID_INTEL_STD,
1056 .CmdSet = P_ID_INTEL_STD, 980 .nr_regions = 2,
1057 .NumEraseRegions= 2,
1058 .regions = { 981 .regions = {
1059 ERASEINFO(0x02000, 8), 982 ERASEINFO(0x02000, 8),
1060 ERASEINFO(0x10000, 63), 983 ERASEINFO(0x10000, 63),
@@ -1063,12 +986,11 @@ static const struct amd_flash_info jedec_table[] = {
1063 .mfr_id = MANUFACTURER_INTEL, 986 .mfr_id = MANUFACTURER_INTEL,
1064 .dev_id = I28F320B3T, 987 .dev_id = I28F320B3T,
1065 .name = "Intel 28F320B3T", 988 .name = "Intel 28F320B3T",
1066 .uaddr = { 989 .devtypes = CFI_DEVICETYPE_X16,
1067 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 990 .uaddr = MTD_UADDR_UNNECESSARY,
1068 }, 991 .dev_size = SIZE_4MiB,
1069 .DevSize = SIZE_4MiB, 992 .cmd_set = P_ID_INTEL_STD,
1070 .CmdSet = P_ID_INTEL_STD, 993 .nr_regions = 2,
1071 .NumEraseRegions= 2,
1072 .regions = { 994 .regions = {
1073 ERASEINFO(0x10000, 63), 995 ERASEINFO(0x10000, 63),
1074 ERASEINFO(0x02000, 8), 996 ERASEINFO(0x02000, 8),
@@ -1077,12 +999,11 @@ static const struct amd_flash_info jedec_table[] = {
1077 .mfr_id = MANUFACTURER_INTEL, 999 .mfr_id = MANUFACTURER_INTEL,
1078 .dev_id = I28F640B3B, 1000 .dev_id = I28F640B3B,
1079 .name = "Intel 28F640B3B", 1001 .name = "Intel 28F640B3B",
1080 .uaddr = { 1002 .devtypes = CFI_DEVICETYPE_X16,
1081 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 1003 .uaddr = MTD_UADDR_UNNECESSARY,
1082 }, 1004 .dev_size = SIZE_8MiB,
1083 .DevSize = SIZE_8MiB, 1005 .cmd_set = P_ID_INTEL_STD,
1084 .CmdSet = P_ID_INTEL_STD, 1006 .nr_regions = 2,
1085 .NumEraseRegions= 2,
1086 .regions = { 1007 .regions = {
1087 ERASEINFO(0x02000, 8), 1008 ERASEINFO(0x02000, 8),
1088 ERASEINFO(0x10000, 127), 1009 ERASEINFO(0x10000, 127),
@@ -1091,12 +1012,11 @@ static const struct amd_flash_info jedec_table[] = {
1091 .mfr_id = MANUFACTURER_INTEL, 1012 .mfr_id = MANUFACTURER_INTEL,
1092 .dev_id = I28F640B3T, 1013 .dev_id = I28F640B3T,
1093 .name = "Intel 28F640B3T", 1014 .name = "Intel 28F640B3T",
1094 .uaddr = { 1015 .devtypes = CFI_DEVICETYPE_X16,
1095 [1] = MTD_UADDR_UNNECESSARY, /* x16 */ 1016 .uaddr = MTD_UADDR_UNNECESSARY,
1096 }, 1017 .dev_size = SIZE_8MiB,
1097 .DevSize = SIZE_8MiB, 1018 .cmd_set = P_ID_INTEL_STD,
1098 .CmdSet = P_ID_INTEL_STD, 1019 .nr_regions = 2,
1099 .NumEraseRegions= 2,
1100 .regions = { 1020 .regions = {
1101 ERASEINFO(0x10000, 127), 1021 ERASEINFO(0x10000, 127),
1102 ERASEINFO(0x02000, 8), 1022 ERASEINFO(0x02000, 8),
@@ -1105,12 +1025,11 @@ static const struct amd_flash_info jedec_table[] = {
1105 .mfr_id = MANUFACTURER_INTEL, 1025 .mfr_id = MANUFACTURER_INTEL,
1106 .dev_id = I82802AB, 1026 .dev_id = I82802AB,
1107 .name = "Intel 82802AB", 1027 .name = "Intel 82802AB",
1108 .uaddr = { 1028 .devtypes = CFI_DEVICETYPE_X8,
1109 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1029 .uaddr = MTD_UADDR_UNNECESSARY,
1110 }, 1030 .dev_size = SIZE_512KiB,
1111 .DevSize = SIZE_512KiB, 1031 .cmd_set = P_ID_INTEL_EXT,
1112 .CmdSet = P_ID_INTEL_EXT, 1032 .nr_regions = 1,
1113 .NumEraseRegions= 1,
1114 .regions = { 1033 .regions = {
1115 ERASEINFO(0x10000,8), 1034 ERASEINFO(0x10000,8),
1116 } 1035 }
@@ -1118,12 +1037,11 @@ static const struct amd_flash_info jedec_table[] = {
1118 .mfr_id = MANUFACTURER_INTEL, 1037 .mfr_id = MANUFACTURER_INTEL,
1119 .dev_id = I82802AC, 1038 .dev_id = I82802AC,
1120 .name = "Intel 82802AC", 1039 .name = "Intel 82802AC",
1121 .uaddr = { 1040 .devtypes = CFI_DEVICETYPE_X8,
1122 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1041 .uaddr = MTD_UADDR_UNNECESSARY,
1123 }, 1042 .dev_size = SIZE_1MiB,
1124 .DevSize = SIZE_1MiB, 1043 .cmd_set = P_ID_INTEL_EXT,
1125 .CmdSet = P_ID_INTEL_EXT, 1044 .nr_regions = 1,
1126 .NumEraseRegions= 1,
1127 .regions = { 1045 .regions = {
1128 ERASEINFO(0x10000,16), 1046 ERASEINFO(0x10000,16),
1129 } 1047 }
@@ -1131,12 +1049,11 @@ static const struct amd_flash_info jedec_table[] = {
1131 .mfr_id = MANUFACTURER_MACRONIX, 1049 .mfr_id = MANUFACTURER_MACRONIX,
1132 .dev_id = MX29LV040C, 1050 .dev_id = MX29LV040C,
1133 .name = "Macronix MX29LV040C", 1051 .name = "Macronix MX29LV040C",
1134 .uaddr = { 1052 .devtypes = CFI_DEVICETYPE_X8,
1135 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */ 1053 .uaddr = MTD_UADDR_0x0555_0x02AA,
1136 }, 1054 .dev_size = SIZE_512KiB,
1137 .DevSize = SIZE_512KiB, 1055 .cmd_set = P_ID_AMD_STD,
1138 .CmdSet = P_ID_AMD_STD, 1056 .nr_regions = 1,
1139 .NumEraseRegions= 1,
1140 .regions = { 1057 .regions = {
1141 ERASEINFO(0x10000,8), 1058 ERASEINFO(0x10000,8),
1142 } 1059 }
@@ -1144,13 +1061,11 @@ static const struct amd_flash_info jedec_table[] = {
1144 .mfr_id = MANUFACTURER_MACRONIX, 1061 .mfr_id = MANUFACTURER_MACRONIX,
1145 .dev_id = MX29LV160T, 1062 .dev_id = MX29LV160T,
1146 .name = "MXIC MX29LV160T", 1063 .name = "MXIC MX29LV160T",
1147 .uaddr = { 1064 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1148 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1065 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1149 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1066 .dev_size = SIZE_2MiB,
1150 }, 1067 .cmd_set = P_ID_AMD_STD,
1151 .DevSize = SIZE_2MiB, 1068 .nr_regions = 4,
1152 .CmdSet = P_ID_AMD_STD,
1153 .NumEraseRegions= 4,
1154 .regions = { 1069 .regions = {
1155 ERASEINFO(0x10000,31), 1070 ERASEINFO(0x10000,31),
1156 ERASEINFO(0x08000,1), 1071 ERASEINFO(0x08000,1),
@@ -1161,13 +1076,11 @@ static const struct amd_flash_info jedec_table[] = {
1161 .mfr_id = MANUFACTURER_NEC, 1076 .mfr_id = MANUFACTURER_NEC,
1162 .dev_id = UPD29F064115, 1077 .dev_id = UPD29F064115,
1163 .name = "NEC uPD29F064115", 1078 .name = "NEC uPD29F064115",
1164 .uaddr = { 1079 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1165 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */ 1080 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
1166 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1081 .dev_size = SIZE_8MiB,
1167 }, 1082 .cmd_set = P_ID_AMD_STD,
1168 .DevSize = SIZE_8MiB, 1083 .nr_regions = 3,
1169 .CmdSet = P_ID_AMD_STD,
1170 .NumEraseRegions= 3,
1171 .regions = { 1084 .regions = {
1172 ERASEINFO(0x2000,8), 1085 ERASEINFO(0x2000,8),
1173 ERASEINFO(0x10000,126), 1086 ERASEINFO(0x10000,126),
@@ -1177,13 +1090,11 @@ static const struct amd_flash_info jedec_table[] = {
1177 .mfr_id = MANUFACTURER_MACRONIX, 1090 .mfr_id = MANUFACTURER_MACRONIX,
1178 .dev_id = MX29LV160B, 1091 .dev_id = MX29LV160B,
1179 .name = "MXIC MX29LV160B", 1092 .name = "MXIC MX29LV160B",
1180 .uaddr = { 1093 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1181 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1094 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1182 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1095 .dev_size = SIZE_2MiB,
1183 }, 1096 .cmd_set = P_ID_AMD_STD,
1184 .DevSize = SIZE_2MiB, 1097 .nr_regions = 4,
1185 .CmdSet = P_ID_AMD_STD,
1186 .NumEraseRegions= 4,
1187 .regions = { 1098 .regions = {
1188 ERASEINFO(0x04000,1), 1099 ERASEINFO(0x04000,1),
1189 ERASEINFO(0x02000,2), 1100 ERASEINFO(0x02000,2),
@@ -1194,12 +1105,11 @@ static const struct amd_flash_info jedec_table[] = {
1194 .mfr_id = MANUFACTURER_MACRONIX, 1105 .mfr_id = MANUFACTURER_MACRONIX,
1195 .dev_id = MX29F040, 1106 .dev_id = MX29F040,
1196 .name = "Macronix MX29F040", 1107 .name = "Macronix MX29F040",
1197 .uaddr = { 1108 .devtypes = CFI_DEVICETYPE_X8,
1198 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1109 .uaddr = MTD_UADDR_0x0555_0x02AA,
1199 }, 1110 .dev_size = SIZE_512KiB,
1200 .DevSize = SIZE_512KiB, 1111 .cmd_set = P_ID_AMD_STD,
1201 .CmdSet = P_ID_AMD_STD, 1112 .nr_regions = 1,
1202 .NumEraseRegions= 1,
1203 .regions = { 1113 .regions = {
1204 ERASEINFO(0x10000,8), 1114 ERASEINFO(0x10000,8),
1205 } 1115 }
@@ -1207,12 +1117,11 @@ static const struct amd_flash_info jedec_table[] = {
1207 .mfr_id = MANUFACTURER_MACRONIX, 1117 .mfr_id = MANUFACTURER_MACRONIX,
1208 .dev_id = MX29F016, 1118 .dev_id = MX29F016,
1209 .name = "Macronix MX29F016", 1119 .name = "Macronix MX29F016",
1210 .uaddr = { 1120 .devtypes = CFI_DEVICETYPE_X8,
1211 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1121 .uaddr = MTD_UADDR_0x0555_0x02AA,
1212 }, 1122 .dev_size = SIZE_2MiB,
1213 .DevSize = SIZE_2MiB, 1123 .cmd_set = P_ID_AMD_STD,
1214 .CmdSet = P_ID_AMD_STD, 1124 .nr_regions = 1,
1215 .NumEraseRegions= 1,
1216 .regions = { 1125 .regions = {
1217 ERASEINFO(0x10000,32), 1126 ERASEINFO(0x10000,32),
1218 } 1127 }
@@ -1220,12 +1129,11 @@ static const struct amd_flash_info jedec_table[] = {
1220 .mfr_id = MANUFACTURER_MACRONIX, 1129 .mfr_id = MANUFACTURER_MACRONIX,
1221 .dev_id = MX29F004T, 1130 .dev_id = MX29F004T,
1222 .name = "Macronix MX29F004T", 1131 .name = "Macronix MX29F004T",
1223 .uaddr = { 1132 .devtypes = CFI_DEVICETYPE_X8,
1224 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1133 .uaddr = MTD_UADDR_0x0555_0x02AA,
1225 }, 1134 .dev_size = SIZE_512KiB,
1226 .DevSize = SIZE_512KiB, 1135 .cmd_set = P_ID_AMD_STD,
1227 .CmdSet = P_ID_AMD_STD, 1136 .nr_regions = 4,
1228 .NumEraseRegions= 4,
1229 .regions = { 1137 .regions = {
1230 ERASEINFO(0x10000,7), 1138 ERASEINFO(0x10000,7),
1231 ERASEINFO(0x08000,1), 1139 ERASEINFO(0x08000,1),
@@ -1236,12 +1144,11 @@ static const struct amd_flash_info jedec_table[] = {
1236 .mfr_id = MANUFACTURER_MACRONIX, 1144 .mfr_id = MANUFACTURER_MACRONIX,
1237 .dev_id = MX29F004B, 1145 .dev_id = MX29F004B,
1238 .name = "Macronix MX29F004B", 1146 .name = "Macronix MX29F004B",
1239 .uaddr = { 1147 .devtypes = CFI_DEVICETYPE_X8,
1240 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1148 .uaddr = MTD_UADDR_0x0555_0x02AA,
1241 }, 1149 .dev_size = SIZE_512KiB,
1242 .DevSize = SIZE_512KiB, 1150 .cmd_set = P_ID_AMD_STD,
1243 .CmdSet = P_ID_AMD_STD, 1151 .nr_regions = 4,
1244 .NumEraseRegions= 4,
1245 .regions = { 1152 .regions = {
1246 ERASEINFO(0x04000,1), 1153 ERASEINFO(0x04000,1),
1247 ERASEINFO(0x02000,2), 1154 ERASEINFO(0x02000,2),
@@ -1252,12 +1159,11 @@ static const struct amd_flash_info jedec_table[] = {
1252 .mfr_id = MANUFACTURER_MACRONIX, 1159 .mfr_id = MANUFACTURER_MACRONIX,
1253 .dev_id = MX29F002T, 1160 .dev_id = MX29F002T,
1254 .name = "Macronix MX29F002T", 1161 .name = "Macronix MX29F002T",
1255 .uaddr = { 1162 .devtypes = CFI_DEVICETYPE_X8,
1256 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1163 .uaddr = MTD_UADDR_0x0555_0x02AA,
1257 }, 1164 .dev_size = SIZE_256KiB,
1258 .DevSize = SIZE_256KiB, 1165 .cmd_set = P_ID_AMD_STD,
1259 .CmdSet = P_ID_AMD_STD, 1166 .nr_regions = 4,
1260 .NumEraseRegions= 4,
1261 .regions = { 1167 .regions = {
1262 ERASEINFO(0x10000,3), 1168 ERASEINFO(0x10000,3),
1263 ERASEINFO(0x08000,1), 1169 ERASEINFO(0x08000,1),
@@ -1268,12 +1174,11 @@ static const struct amd_flash_info jedec_table[] = {
1268 .mfr_id = MANUFACTURER_PMC, 1174 .mfr_id = MANUFACTURER_PMC,
1269 .dev_id = PM49FL002, 1175 .dev_id = PM49FL002,
1270 .name = "PMC Pm49FL002", 1176 .name = "PMC Pm49FL002",
1271 .uaddr = { 1177 .devtypes = CFI_DEVICETYPE_X8,
1272 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1178 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1273 }, 1179 .dev_size = SIZE_256KiB,
1274 .DevSize = SIZE_256KiB, 1180 .cmd_set = P_ID_AMD_STD,
1275 .CmdSet = P_ID_AMD_STD, 1181 .nr_regions = 1,
1276 .NumEraseRegions= 1,
1277 .regions = { 1182 .regions = {
1278 ERASEINFO( 0x01000, 64 ) 1183 ERASEINFO( 0x01000, 64 )
1279 } 1184 }
@@ -1281,12 +1186,11 @@ static const struct amd_flash_info jedec_table[] = {
1281 .mfr_id = MANUFACTURER_PMC, 1186 .mfr_id = MANUFACTURER_PMC,
1282 .dev_id = PM49FL004, 1187 .dev_id = PM49FL004,
1283 .name = "PMC Pm49FL004", 1188 .name = "PMC Pm49FL004",
1284 .uaddr = { 1189 .devtypes = CFI_DEVICETYPE_X8,
1285 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1190 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1286 }, 1191 .dev_size = SIZE_512KiB,
1287 .DevSize = SIZE_512KiB, 1192 .cmd_set = P_ID_AMD_STD,
1288 .CmdSet = P_ID_AMD_STD, 1193 .nr_regions = 1,
1289 .NumEraseRegions= 1,
1290 .regions = { 1194 .regions = {
1291 ERASEINFO( 0x01000, 128 ) 1195 ERASEINFO( 0x01000, 128 )
1292 } 1196 }
@@ -1294,12 +1198,11 @@ static const struct amd_flash_info jedec_table[] = {
1294 .mfr_id = MANUFACTURER_PMC, 1198 .mfr_id = MANUFACTURER_PMC,
1295 .dev_id = PM49FL008, 1199 .dev_id = PM49FL008,
1296 .name = "PMC Pm49FL008", 1200 .name = "PMC Pm49FL008",
1297 .uaddr = { 1201 .devtypes = CFI_DEVICETYPE_X8,
1298 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1202 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1299 }, 1203 .dev_size = SIZE_1MiB,
1300 .DevSize = SIZE_1MiB, 1204 .cmd_set = P_ID_AMD_STD,
1301 .CmdSet = P_ID_AMD_STD, 1205 .nr_regions = 1,
1302 .NumEraseRegions= 1,
1303 .regions = { 1206 .regions = {
1304 ERASEINFO( 0x01000, 256 ) 1207 ERASEINFO( 0x01000, 256 )
1305 } 1208 }
@@ -1307,25 +1210,23 @@ static const struct amd_flash_info jedec_table[] = {
1307 .mfr_id = MANUFACTURER_SHARP, 1210 .mfr_id = MANUFACTURER_SHARP,
1308 .dev_id = LH28F640BF, 1211 .dev_id = LH28F640BF,
1309 .name = "LH28F640BF", 1212 .name = "LH28F640BF",
1310 .uaddr = { 1213 .devtypes = CFI_DEVICETYPE_X8,
1311 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1214 .uaddr = MTD_UADDR_UNNECESSARY,
1312 }, 1215 .dev_size = SIZE_4MiB,
1313 .DevSize = SIZE_4MiB, 1216 .cmd_set = P_ID_INTEL_STD,
1314 .CmdSet = P_ID_INTEL_STD, 1217 .nr_regions = 1,
1315 .NumEraseRegions= 1, 1218 .regions = {
1316 .regions = {
1317 ERASEINFO(0x40000,16), 1219 ERASEINFO(0x40000,16),
1318 } 1220 }
1319 }, { 1221 }, {
1320 .mfr_id = MANUFACTURER_SST, 1222 .mfr_id = MANUFACTURER_SST,
1321 .dev_id = SST39LF512, 1223 .dev_id = SST39LF512,
1322 .name = "SST 39LF512", 1224 .name = "SST 39LF512",
1323 .uaddr = { 1225 .devtypes = CFI_DEVICETYPE_X8,
1324 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1226 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1325 }, 1227 .dev_size = SIZE_64KiB,
1326 .DevSize = SIZE_64KiB, 1228 .cmd_set = P_ID_AMD_STD,
1327 .CmdSet = P_ID_AMD_STD, 1229 .nr_regions = 1,
1328 .NumEraseRegions= 1,
1329 .regions = { 1230 .regions = {
1330 ERASEINFO(0x01000,16), 1231 ERASEINFO(0x01000,16),
1331 } 1232 }
@@ -1333,12 +1234,11 @@ static const struct amd_flash_info jedec_table[] = {
1333 .mfr_id = MANUFACTURER_SST, 1234 .mfr_id = MANUFACTURER_SST,
1334 .dev_id = SST39LF010, 1235 .dev_id = SST39LF010,
1335 .name = "SST 39LF010", 1236 .name = "SST 39LF010",
1336 .uaddr = { 1237 .devtypes = CFI_DEVICETYPE_X8,
1337 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1238 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1338 }, 1239 .dev_size = SIZE_128KiB,
1339 .DevSize = SIZE_128KiB, 1240 .cmd_set = P_ID_AMD_STD,
1340 .CmdSet = P_ID_AMD_STD, 1241 .nr_regions = 1,
1341 .NumEraseRegions= 1,
1342 .regions = { 1242 .regions = {
1343 ERASEINFO(0x01000,32), 1243 ERASEINFO(0x01000,32),
1344 } 1244 }
@@ -1346,36 +1246,33 @@ static const struct amd_flash_info jedec_table[] = {
1346 .mfr_id = MANUFACTURER_SST, 1246 .mfr_id = MANUFACTURER_SST,
1347 .dev_id = SST29EE020, 1247 .dev_id = SST29EE020,
1348 .name = "SST 29EE020", 1248 .name = "SST 29EE020",
1349 .uaddr = { 1249 .devtypes = CFI_DEVICETYPE_X8,
1350 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1250 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1351 }, 1251 .dev_size = SIZE_256KiB,
1352 .DevSize = SIZE_256KiB, 1252 .cmd_set = P_ID_SST_PAGE,
1353 .CmdSet = P_ID_SST_PAGE, 1253 .nr_regions = 1,
1354 .NumEraseRegions= 1, 1254 .regions = {ERASEINFO(0x01000,64),
1355 .regions = {ERASEINFO(0x01000,64), 1255 }
1356 } 1256 }, {
1357 }, {
1358 .mfr_id = MANUFACTURER_SST, 1257 .mfr_id = MANUFACTURER_SST,
1359 .dev_id = SST29LE020, 1258 .dev_id = SST29LE020,
1360 .name = "SST 29LE020", 1259 .name = "SST 29LE020",
1361 .uaddr = { 1260 .devtypes = CFI_DEVICETYPE_X8,
1362 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1261 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1363 }, 1262 .dev_size = SIZE_256KiB,
1364 .DevSize = SIZE_256KiB, 1263 .cmd_set = P_ID_SST_PAGE,
1365 .CmdSet = P_ID_SST_PAGE, 1264 .nr_regions = 1,
1366 .NumEraseRegions= 1, 1265 .regions = {ERASEINFO(0x01000,64),
1367 .regions = {ERASEINFO(0x01000,64), 1266 }
1368 }
1369 }, { 1267 }, {
1370 .mfr_id = MANUFACTURER_SST, 1268 .mfr_id = MANUFACTURER_SST,
1371 .dev_id = SST39LF020, 1269 .dev_id = SST39LF020,
1372 .name = "SST 39LF020", 1270 .name = "SST 39LF020",
1373 .uaddr = { 1271 .devtypes = CFI_DEVICETYPE_X8,
1374 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1272 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1375 }, 1273 .dev_size = SIZE_256KiB,
1376 .DevSize = SIZE_256KiB, 1274 .cmd_set = P_ID_AMD_STD,
1377 .CmdSet = P_ID_AMD_STD, 1275 .nr_regions = 1,
1378 .NumEraseRegions= 1,
1379 .regions = { 1276 .regions = {
1380 ERASEINFO(0x01000,64), 1277 ERASEINFO(0x01000,64),
1381 } 1278 }
@@ -1383,12 +1280,11 @@ static const struct amd_flash_info jedec_table[] = {
1383 .mfr_id = MANUFACTURER_SST, 1280 .mfr_id = MANUFACTURER_SST,
1384 .dev_id = SST39LF040, 1281 .dev_id = SST39LF040,
1385 .name = "SST 39LF040", 1282 .name = "SST 39LF040",
1386 .uaddr = { 1283 .devtypes = CFI_DEVICETYPE_X8,
1387 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1284 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1388 }, 1285 .dev_size = SIZE_512KiB,
1389 .DevSize = SIZE_512KiB, 1286 .cmd_set = P_ID_AMD_STD,
1390 .CmdSet = P_ID_AMD_STD, 1287 .nr_regions = 1,
1391 .NumEraseRegions= 1,
1392 .regions = { 1288 .regions = {
1393 ERASEINFO(0x01000,128), 1289 ERASEINFO(0x01000,128),
1394 } 1290 }
@@ -1396,12 +1292,11 @@ static const struct amd_flash_info jedec_table[] = {
1396 .mfr_id = MANUFACTURER_SST, 1292 .mfr_id = MANUFACTURER_SST,
1397 .dev_id = SST39SF010A, 1293 .dev_id = SST39SF010A,
1398 .name = "SST 39SF010A", 1294 .name = "SST 39SF010A",
1399 .uaddr = { 1295 .devtypes = CFI_DEVICETYPE_X8,
1400 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1296 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1401 }, 1297 .dev_size = SIZE_128KiB,
1402 .DevSize = SIZE_128KiB, 1298 .cmd_set = P_ID_AMD_STD,
1403 .CmdSet = P_ID_AMD_STD, 1299 .nr_regions = 1,
1404 .NumEraseRegions= 1,
1405 .regions = { 1300 .regions = {
1406 ERASEINFO(0x01000,32), 1301 ERASEINFO(0x01000,32),
1407 } 1302 }
@@ -1409,26 +1304,24 @@ static const struct amd_flash_info jedec_table[] = {
1409 .mfr_id = MANUFACTURER_SST, 1304 .mfr_id = MANUFACTURER_SST,
1410 .dev_id = SST39SF020A, 1305 .dev_id = SST39SF020A,
1411 .name = "SST 39SF020A", 1306 .name = "SST 39SF020A",
1412 .uaddr = { 1307 .devtypes = CFI_DEVICETYPE_X8,
1413 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1308 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1414 }, 1309 .dev_size = SIZE_256KiB,
1415 .DevSize = SIZE_256KiB, 1310 .cmd_set = P_ID_AMD_STD,
1416 .CmdSet = P_ID_AMD_STD, 1311 .nr_regions = 1,
1417 .NumEraseRegions= 1,
1418 .regions = { 1312 .regions = {
1419 ERASEINFO(0x01000,64), 1313 ERASEINFO(0x01000,64),
1420 } 1314 }
1421 }, { 1315 }, {
1422 .mfr_id = MANUFACTURER_SST, 1316 .mfr_id = MANUFACTURER_SST,
1423 .dev_id = SST49LF040B, 1317 .dev_id = SST49LF040B,
1424 .name = "SST 49LF040B", 1318 .name = "SST 49LF040B",
1425 .uaddr = { 1319 .devtypes = CFI_DEVICETYPE_X8,
1426 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1320 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1427 }, 1321 .dev_size = SIZE_512KiB,
1428 .DevSize = SIZE_512KiB, 1322 .cmd_set = P_ID_AMD_STD,
1429 .CmdSet = P_ID_AMD_STD, 1323 .nr_regions = 1,
1430 .NumEraseRegions= 1, 1324 .regions = {
1431 .regions = {
1432 ERASEINFO(0x01000,128), 1325 ERASEINFO(0x01000,128),
1433 } 1326 }
1434 }, { 1327 }, {
@@ -1436,12 +1329,11 @@ static const struct amd_flash_info jedec_table[] = {
1436 .mfr_id = MANUFACTURER_SST, 1329 .mfr_id = MANUFACTURER_SST,
1437 .dev_id = SST49LF004B, 1330 .dev_id = SST49LF004B,
1438 .name = "SST 49LF004B", 1331 .name = "SST 49LF004B",
1439 .uaddr = { 1332 .devtypes = CFI_DEVICETYPE_X8,
1440 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1333 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1441 }, 1334 .dev_size = SIZE_512KiB,
1442 .DevSize = SIZE_512KiB, 1335 .cmd_set = P_ID_AMD_STD,
1443 .CmdSet = P_ID_AMD_STD, 1336 .nr_regions = 1,
1444 .NumEraseRegions= 1,
1445 .regions = { 1337 .regions = {
1446 ERASEINFO(0x01000,128), 1338 ERASEINFO(0x01000,128),
1447 } 1339 }
@@ -1449,12 +1341,11 @@ static const struct amd_flash_info jedec_table[] = {
1449 .mfr_id = MANUFACTURER_SST, 1341 .mfr_id = MANUFACTURER_SST,
1450 .dev_id = SST49LF008A, 1342 .dev_id = SST49LF008A,
1451 .name = "SST 49LF008A", 1343 .name = "SST 49LF008A",
1452 .uaddr = { 1344 .devtypes = CFI_DEVICETYPE_X8,
1453 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1345 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1454 }, 1346 .dev_size = SIZE_1MiB,
1455 .DevSize = SIZE_1MiB, 1347 .cmd_set = P_ID_AMD_STD,
1456 .CmdSet = P_ID_AMD_STD, 1348 .nr_regions = 1,
1457 .NumEraseRegions= 1,
1458 .regions = { 1349 .regions = {
1459 ERASEINFO(0x01000,256), 1350 ERASEINFO(0x01000,256),
1460 } 1351 }
@@ -1462,12 +1353,11 @@ static const struct amd_flash_info jedec_table[] = {
1462 .mfr_id = MANUFACTURER_SST, 1353 .mfr_id = MANUFACTURER_SST,
1463 .dev_id = SST49LF030A, 1354 .dev_id = SST49LF030A,
1464 .name = "SST 49LF030A", 1355 .name = "SST 49LF030A",
1465 .uaddr = { 1356 .devtypes = CFI_DEVICETYPE_X8,
1466 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1357 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1467 }, 1358 .dev_size = SIZE_512KiB,
1468 .DevSize = SIZE_512KiB, 1359 .cmd_set = P_ID_AMD_STD,
1469 .CmdSet = P_ID_AMD_STD, 1360 .nr_regions = 1,
1470 .NumEraseRegions= 1,
1471 .regions = { 1361 .regions = {
1472 ERASEINFO(0x01000,96), 1362 ERASEINFO(0x01000,96),
1473 } 1363 }
@@ -1475,12 +1365,11 @@ static const struct amd_flash_info jedec_table[] = {
1475 .mfr_id = MANUFACTURER_SST, 1365 .mfr_id = MANUFACTURER_SST,
1476 .dev_id = SST49LF040A, 1366 .dev_id = SST49LF040A,
1477 .name = "SST 49LF040A", 1367 .name = "SST 49LF040A",
1478 .uaddr = { 1368 .devtypes = CFI_DEVICETYPE_X8,
1479 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1369 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1480 }, 1370 .dev_size = SIZE_512KiB,
1481 .DevSize = SIZE_512KiB, 1371 .cmd_set = P_ID_AMD_STD,
1482 .CmdSet = P_ID_AMD_STD, 1372 .nr_regions = 1,
1483 .NumEraseRegions= 1,
1484 .regions = { 1373 .regions = {
1485 ERASEINFO(0x01000,128), 1374 ERASEINFO(0x01000,128),
1486 } 1375 }
@@ -1488,57 +1377,49 @@ static const struct amd_flash_info jedec_table[] = {
1488 .mfr_id = MANUFACTURER_SST, 1377 .mfr_id = MANUFACTURER_SST,
1489 .dev_id = SST49LF080A, 1378 .dev_id = SST49LF080A,
1490 .name = "SST 49LF080A", 1379 .name = "SST 49LF080A",
1491 .uaddr = { 1380 .devtypes = CFI_DEVICETYPE_X8,
1492 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1381 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1493 }, 1382 .dev_size = SIZE_1MiB,
1494 .DevSize = SIZE_1MiB, 1383 .cmd_set = P_ID_AMD_STD,
1495 .CmdSet = P_ID_AMD_STD, 1384 .nr_regions = 1,
1496 .NumEraseRegions= 1,
1497 .regions = { 1385 .regions = {
1498 ERASEINFO(0x01000,256), 1386 ERASEINFO(0x01000,256),
1499 } 1387 }
1500 }, { 1388 }, {
1501 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1389 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1502 .dev_id = SST39LF160, 1390 .dev_id = SST39LF160,
1503 .name = "SST 39LF160", 1391 .name = "SST 39LF160",
1504 .uaddr = { 1392 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1505 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */ 1393 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
1506 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */ 1394 .dev_size = SIZE_2MiB,
1507 }, 1395 .cmd_set = P_ID_AMD_STD,
1508 .DevSize = SIZE_2MiB, 1396 .nr_regions = 2,
1509 .CmdSet = P_ID_AMD_STD, 1397 .regions = {
1510 .NumEraseRegions= 2, 1398 ERASEINFO(0x1000,256),
1511 .regions = { 1399 ERASEINFO(0x1000,256)
1512 ERASEINFO(0x1000,256), 1400 }
1513 ERASEINFO(0x1000,256) 1401 }, {
1514 } 1402 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1515 }, { 1403 .dev_id = SST39VF1601,
1516 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1404 .name = "SST 39VF1601",
1517 .dev_id = SST39VF1601, 1405 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1518 .name = "SST 39VF1601", 1406 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
1519 .uaddr = { 1407 .dev_size = SIZE_2MiB,
1520 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */ 1408 .cmd_set = P_ID_AMD_STD,
1521 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */ 1409 .nr_regions = 2,
1522 }, 1410 .regions = {
1523 .DevSize = SIZE_2MiB, 1411 ERASEINFO(0x1000,256),
1524 .CmdSet = P_ID_AMD_STD, 1412 ERASEINFO(0x1000,256)
1525 .NumEraseRegions= 2, 1413 }
1526 .regions = {
1527 ERASEINFO(0x1000,256),
1528 ERASEINFO(0x1000,256)
1529 }
1530
1531 }, { 1414 }, {
1532 .mfr_id = MANUFACTURER_ST, 1415 .mfr_id = MANUFACTURER_ST,
1533 .dev_id = M29F800AB, 1416 .dev_id = M29F800AB,
1534 .name = "ST M29F800AB", 1417 .name = "ST M29F800AB",
1535 .uaddr = { 1418 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1536 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1419 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1537 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1420 .dev_size = SIZE_1MiB,
1538 }, 1421 .cmd_set = P_ID_AMD_STD,
1539 .DevSize = SIZE_1MiB, 1422 .nr_regions = 4,
1540 .CmdSet = P_ID_AMD_STD,
1541 .NumEraseRegions= 4,
1542 .regions = { 1423 .regions = {
1543 ERASEINFO(0x04000,1), 1424 ERASEINFO(0x04000,1),
1544 ERASEINFO(0x02000,2), 1425 ERASEINFO(0x02000,2),
@@ -1549,13 +1430,11 @@ static const struct amd_flash_info jedec_table[] = {
1549 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1430 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1550 .dev_id = M29W800DT, 1431 .dev_id = M29W800DT,
1551 .name = "ST M29W800DT", 1432 .name = "ST M29W800DT",
1552 .uaddr = { 1433 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1553 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */ 1434 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
1554 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */ 1435 .dev_size = SIZE_1MiB,
1555 }, 1436 .cmd_set = P_ID_AMD_STD,
1556 .DevSize = SIZE_1MiB, 1437 .nr_regions = 4,
1557 .CmdSet = P_ID_AMD_STD,
1558 .NumEraseRegions= 4,
1559 .regions = { 1438 .regions = {
1560 ERASEINFO(0x10000,15), 1439 ERASEINFO(0x10000,15),
1561 ERASEINFO(0x08000,1), 1440 ERASEINFO(0x08000,1),
@@ -1566,13 +1445,11 @@ static const struct amd_flash_info jedec_table[] = {
1566 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1445 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1567 .dev_id = M29W800DB, 1446 .dev_id = M29W800DB,
1568 .name = "ST M29W800DB", 1447 .name = "ST M29W800DB",
1569 .uaddr = { 1448 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1570 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */ 1449 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
1571 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */ 1450 .dev_size = SIZE_1MiB,
1572 }, 1451 .cmd_set = P_ID_AMD_STD,
1573 .DevSize = SIZE_1MiB, 1452 .nr_regions = 4,
1574 .CmdSet = P_ID_AMD_STD,
1575 .NumEraseRegions= 4,
1576 .regions = { 1453 .regions = {
1577 ERASEINFO(0x04000,1), 1454 ERASEINFO(0x04000,1),
1578 ERASEINFO(0x02000,2), 1455 ERASEINFO(0x02000,2),
@@ -1583,13 +1460,11 @@ static const struct amd_flash_info jedec_table[] = {
1583 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1460 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1584 .dev_id = M29W160DT, 1461 .dev_id = M29W160DT,
1585 .name = "ST M29W160DT", 1462 .name = "ST M29W160DT",
1586 .uaddr = { 1463 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1587 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */ 1464 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
1588 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1465 .dev_size = SIZE_2MiB,
1589 }, 1466 .cmd_set = P_ID_AMD_STD,
1590 .DevSize = SIZE_2MiB, 1467 .nr_regions = 4,
1591 .CmdSet = P_ID_AMD_STD,
1592 .NumEraseRegions= 4,
1593 .regions = { 1468 .regions = {
1594 ERASEINFO(0x10000,31), 1469 ERASEINFO(0x10000,31),
1595 ERASEINFO(0x08000,1), 1470 ERASEINFO(0x08000,1),
@@ -1600,13 +1475,11 @@ static const struct amd_flash_info jedec_table[] = {
1600 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1475 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1601 .dev_id = M29W160DB, 1476 .dev_id = M29W160DB,
1602 .name = "ST M29W160DB", 1477 .name = "ST M29W160DB",
1603 .uaddr = { 1478 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1604 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */ 1479 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
1605 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1480 .dev_size = SIZE_2MiB,
1606 }, 1481 .cmd_set = P_ID_AMD_STD,
1607 .DevSize = SIZE_2MiB, 1482 .nr_regions = 4,
1608 .CmdSet = P_ID_AMD_STD,
1609 .NumEraseRegions= 4,
1610 .regions = { 1483 .regions = {
1611 ERASEINFO(0x04000,1), 1484 ERASEINFO(0x04000,1),
1612 ERASEINFO(0x02000,2), 1485 ERASEINFO(0x02000,2),
@@ -1617,12 +1490,11 @@ static const struct amd_flash_info jedec_table[] = {
1617 .mfr_id = MANUFACTURER_ST, 1490 .mfr_id = MANUFACTURER_ST,
1618 .dev_id = M29W040B, 1491 .dev_id = M29W040B,
1619 .name = "ST M29W040B", 1492 .name = "ST M29W040B",
1620 .uaddr = { 1493 .devtypes = CFI_DEVICETYPE_X8,
1621 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 1494 .uaddr = MTD_UADDR_0x0555_0x02AA,
1622 }, 1495 .dev_size = SIZE_512KiB,
1623 .DevSize = SIZE_512KiB, 1496 .cmd_set = P_ID_AMD_STD,
1624 .CmdSet = P_ID_AMD_STD, 1497 .nr_regions = 1,
1625 .NumEraseRegions= 1,
1626 .regions = { 1498 .regions = {
1627 ERASEINFO(0x10000,8), 1499 ERASEINFO(0x10000,8),
1628 } 1500 }
@@ -1630,12 +1502,11 @@ static const struct amd_flash_info jedec_table[] = {
1630 .mfr_id = MANUFACTURER_ST, 1502 .mfr_id = MANUFACTURER_ST,
1631 .dev_id = M50FW040, 1503 .dev_id = M50FW040,
1632 .name = "ST M50FW040", 1504 .name = "ST M50FW040",
1633 .uaddr = { 1505 .devtypes = CFI_DEVICETYPE_X8,
1634 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1506 .uaddr = MTD_UADDR_UNNECESSARY,
1635 }, 1507 .dev_size = SIZE_512KiB,
1636 .DevSize = SIZE_512KiB, 1508 .cmd_set = P_ID_INTEL_EXT,
1637 .CmdSet = P_ID_INTEL_EXT, 1509 .nr_regions = 1,
1638 .NumEraseRegions= 1,
1639 .regions = { 1510 .regions = {
1640 ERASEINFO(0x10000,8), 1511 ERASEINFO(0x10000,8),
1641 } 1512 }
@@ -1643,12 +1514,11 @@ static const struct amd_flash_info jedec_table[] = {
1643 .mfr_id = MANUFACTURER_ST, 1514 .mfr_id = MANUFACTURER_ST,
1644 .dev_id = M50FW080, 1515 .dev_id = M50FW080,
1645 .name = "ST M50FW080", 1516 .name = "ST M50FW080",
1646 .uaddr = { 1517 .devtypes = CFI_DEVICETYPE_X8,
1647 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1518 .uaddr = MTD_UADDR_UNNECESSARY,
1648 }, 1519 .dev_size = SIZE_1MiB,
1649 .DevSize = SIZE_1MiB, 1520 .cmd_set = P_ID_INTEL_EXT,
1650 .CmdSet = P_ID_INTEL_EXT, 1521 .nr_regions = 1,
1651 .NumEraseRegions= 1,
1652 .regions = { 1522 .regions = {
1653 ERASEINFO(0x10000,16), 1523 ERASEINFO(0x10000,16),
1654 } 1524 }
@@ -1656,12 +1526,11 @@ static const struct amd_flash_info jedec_table[] = {
1656 .mfr_id = MANUFACTURER_ST, 1526 .mfr_id = MANUFACTURER_ST,
1657 .dev_id = M50FW016, 1527 .dev_id = M50FW016,
1658 .name = "ST M50FW016", 1528 .name = "ST M50FW016",
1659 .uaddr = { 1529 .devtypes = CFI_DEVICETYPE_X8,
1660 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1530 .uaddr = MTD_UADDR_UNNECESSARY,
1661 }, 1531 .dev_size = SIZE_2MiB,
1662 .DevSize = SIZE_2MiB, 1532 .cmd_set = P_ID_INTEL_EXT,
1663 .CmdSet = P_ID_INTEL_EXT, 1533 .nr_regions = 1,
1664 .NumEraseRegions= 1,
1665 .regions = { 1534 .regions = {
1666 ERASEINFO(0x10000,32), 1535 ERASEINFO(0x10000,32),
1667 } 1536 }
@@ -1669,12 +1538,11 @@ static const struct amd_flash_info jedec_table[] = {
1669 .mfr_id = MANUFACTURER_ST, 1538 .mfr_id = MANUFACTURER_ST,
1670 .dev_id = M50LPW080, 1539 .dev_id = M50LPW080,
1671 .name = "ST M50LPW080", 1540 .name = "ST M50LPW080",
1672 .uaddr = { 1541 .devtypes = CFI_DEVICETYPE_X8,
1673 [0] = MTD_UADDR_UNNECESSARY, /* x8 */ 1542 .uaddr = MTD_UADDR_UNNECESSARY,
1674 }, 1543 .dev_size = SIZE_1MiB,
1675 .DevSize = SIZE_1MiB, 1544 .cmd_set = P_ID_INTEL_EXT,
1676 .CmdSet = P_ID_INTEL_EXT, 1545 .nr_regions = 1,
1677 .NumEraseRegions= 1,
1678 .regions = { 1546 .regions = {
1679 ERASEINFO(0x10000,16), 1547 ERASEINFO(0x10000,16),
1680 } 1548 }
@@ -1682,13 +1550,11 @@ static const struct amd_flash_info jedec_table[] = {
1682 .mfr_id = MANUFACTURER_TOSHIBA, 1550 .mfr_id = MANUFACTURER_TOSHIBA,
1683 .dev_id = TC58FVT160, 1551 .dev_id = TC58FVT160,
1684 .name = "Toshiba TC58FVT160", 1552 .name = "Toshiba TC58FVT160",
1685 .uaddr = { 1553 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1686 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1554 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1687 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 1555 .dev_size = SIZE_2MiB,
1688 }, 1556 .cmd_set = P_ID_AMD_STD,
1689 .DevSize = SIZE_2MiB, 1557 .nr_regions = 4,
1690 .CmdSet = P_ID_AMD_STD,
1691 .NumEraseRegions= 4,
1692 .regions = { 1558 .regions = {
1693 ERASEINFO(0x10000,31), 1559 ERASEINFO(0x10000,31),
1694 ERASEINFO(0x08000,1), 1560 ERASEINFO(0x08000,1),
@@ -1699,13 +1565,11 @@ static const struct amd_flash_info jedec_table[] = {
1699 .mfr_id = MANUFACTURER_TOSHIBA, 1565 .mfr_id = MANUFACTURER_TOSHIBA,
1700 .dev_id = TC58FVB160, 1566 .dev_id = TC58FVB160,
1701 .name = "Toshiba TC58FVB160", 1567 .name = "Toshiba TC58FVB160",
1702 .uaddr = { 1568 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1703 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1569 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1704 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 1570 .dev_size = SIZE_2MiB,
1705 }, 1571 .cmd_set = P_ID_AMD_STD,
1706 .DevSize = SIZE_2MiB, 1572 .nr_regions = 4,
1707 .CmdSet = P_ID_AMD_STD,
1708 .NumEraseRegions= 4,
1709 .regions = { 1573 .regions = {
1710 ERASEINFO(0x04000,1), 1574 ERASEINFO(0x04000,1),
1711 ERASEINFO(0x02000,2), 1575 ERASEINFO(0x02000,2),
@@ -1716,13 +1580,11 @@ static const struct amd_flash_info jedec_table[] = {
1716 .mfr_id = MANUFACTURER_TOSHIBA, 1580 .mfr_id = MANUFACTURER_TOSHIBA,
1717 .dev_id = TC58FVB321, 1581 .dev_id = TC58FVB321,
1718 .name = "Toshiba TC58FVB321", 1582 .name = "Toshiba TC58FVB321",
1719 .uaddr = { 1583 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1720 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1584 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1721 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 1585 .dev_size = SIZE_4MiB,
1722 }, 1586 .cmd_set = P_ID_AMD_STD,
1723 .DevSize = SIZE_4MiB, 1587 .nr_regions = 2,
1724 .CmdSet = P_ID_AMD_STD,
1725 .NumEraseRegions= 2,
1726 .regions = { 1588 .regions = {
1727 ERASEINFO(0x02000,8), 1589 ERASEINFO(0x02000,8),
1728 ERASEINFO(0x10000,63) 1590 ERASEINFO(0x10000,63)
@@ -1731,13 +1593,11 @@ static const struct amd_flash_info jedec_table[] = {
1731 .mfr_id = MANUFACTURER_TOSHIBA, 1593 .mfr_id = MANUFACTURER_TOSHIBA,
1732 .dev_id = TC58FVT321, 1594 .dev_id = TC58FVT321,
1733 .name = "Toshiba TC58FVT321", 1595 .name = "Toshiba TC58FVT321",
1734 .uaddr = { 1596 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1735 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1597 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1736 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 1598 .dev_size = SIZE_4MiB,
1737 }, 1599 .cmd_set = P_ID_AMD_STD,
1738 .DevSize = SIZE_4MiB, 1600 .nr_regions = 2,
1739 .CmdSet = P_ID_AMD_STD,
1740 .NumEraseRegions= 2,
1741 .regions = { 1601 .regions = {
1742 ERASEINFO(0x10000,63), 1602 ERASEINFO(0x10000,63),
1743 ERASEINFO(0x02000,8) 1603 ERASEINFO(0x02000,8)
@@ -1746,13 +1606,11 @@ static const struct amd_flash_info jedec_table[] = {
1746 .mfr_id = MANUFACTURER_TOSHIBA, 1606 .mfr_id = MANUFACTURER_TOSHIBA,
1747 .dev_id = TC58FVB641, 1607 .dev_id = TC58FVB641,
1748 .name = "Toshiba TC58FVB641", 1608 .name = "Toshiba TC58FVB641",
1749 .uaddr = { 1609 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1750 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1610 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1751 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1611 .dev_size = SIZE_8MiB,
1752 }, 1612 .cmd_set = P_ID_AMD_STD,
1753 .DevSize = SIZE_8MiB, 1613 .nr_regions = 2,
1754 .CmdSet = P_ID_AMD_STD,
1755 .NumEraseRegions= 2,
1756 .regions = { 1614 .regions = {
1757 ERASEINFO(0x02000,8), 1615 ERASEINFO(0x02000,8),
1758 ERASEINFO(0x10000,127) 1616 ERASEINFO(0x10000,127)
@@ -1761,13 +1619,11 @@ static const struct amd_flash_info jedec_table[] = {
1761 .mfr_id = MANUFACTURER_TOSHIBA, 1619 .mfr_id = MANUFACTURER_TOSHIBA,
1762 .dev_id = TC58FVT641, 1620 .dev_id = TC58FVT641,
1763 .name = "Toshiba TC58FVT641", 1621 .name = "Toshiba TC58FVT641",
1764 .uaddr = { 1622 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
1765 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */ 1623 .uaddr = MTD_UADDR_0x0AAA_0x0555,
1766 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */ 1624 .dev_size = SIZE_8MiB,
1767 }, 1625 .cmd_set = P_ID_AMD_STD,
1768 .DevSize = SIZE_8MiB, 1626 .nr_regions = 2,
1769 .CmdSet = P_ID_AMD_STD,
1770 .NumEraseRegions= 2,
1771 .regions = { 1627 .regions = {
1772 ERASEINFO(0x10000,127), 1628 ERASEINFO(0x10000,127),
1773 ERASEINFO(0x02000,8) 1629 ERASEINFO(0x02000,8)
@@ -1776,12 +1632,11 @@ static const struct amd_flash_info jedec_table[] = {
1776 .mfr_id = MANUFACTURER_WINBOND, 1632 .mfr_id = MANUFACTURER_WINBOND,
1777 .dev_id = W49V002A, 1633 .dev_id = W49V002A,
1778 .name = "Winbond W49V002A", 1634 .name = "Winbond W49V002A",
1779 .uaddr = { 1635 .devtypes = CFI_DEVICETYPE_X8,
1780 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 1636 .uaddr = MTD_UADDR_0x5555_0x2AAA,
1781 }, 1637 .dev_size = SIZE_256KiB,
1782 .DevSize = SIZE_256KiB, 1638 .cmd_set = P_ID_AMD_STD,
1783 .CmdSet = P_ID_AMD_STD, 1639 .nr_regions = 4,
1784 .NumEraseRegions= 4,
1785 .regions = { 1640 .regions = {
1786 ERASEINFO(0x10000, 3), 1641 ERASEINFO(0x10000, 3),
1787 ERASEINFO(0x08000, 1), 1642 ERASEINFO(0x08000, 1),
@@ -1791,15 +1646,7 @@ static const struct amd_flash_info jedec_table[] = {
1791 } 1646 }
1792}; 1647};
1793 1648
1794 1649static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
1795static int cfi_jedec_setup(struct cfi_private *p_cfi, int index);
1796
1797static int jedec_probe_chip(struct map_info *map, __u32 base,
1798 unsigned long *chip_map, struct cfi_private *cfi);
1799
1800static struct mtd_info *jedec_probe(struct map_info *map);
1801
1802static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
1803 struct cfi_private *cfi) 1650 struct cfi_private *cfi)
1804{ 1651{
1805 map_word result; 1652 map_word result;
@@ -1810,7 +1657,7 @@ static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
1810 return result.x[0] & mask; 1657 return result.x[0] & mask;
1811} 1658}
1812 1659
1813static inline u32 jedec_read_id(struct map_info *map, __u32 base, 1660static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
1814 struct cfi_private *cfi) 1661 struct cfi_private *cfi)
1815{ 1662{
1816 map_word result; 1663 map_word result;
@@ -1821,8 +1668,7 @@ static inline u32 jedec_read_id(struct map_info *map, __u32 base,
1821 return result.x[0] & mask; 1668 return result.x[0] & mask;
1822} 1669}
1823 1670
1824static inline void jedec_reset(u32 base, struct map_info *map, 1671static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
1825 struct cfi_private *cfi)
1826{ 1672{
1827 /* Reset */ 1673 /* Reset */
1828 1674
@@ -1832,7 +1678,7 @@ static inline void jedec_reset(u32 base, struct map_info *map,
1832 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1678 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1833 * as they will ignore the writes and dont care what address 1679 * as they will ignore the writes and dont care what address
1834 * the F0 is written to */ 1680 * the F0 is written to */
1835 if(cfi->addr_unlock1) { 1681 if (cfi->addr_unlock1) {
1836 DEBUG( MTD_DEBUG_LEVEL3, 1682 DEBUG( MTD_DEBUG_LEVEL3,
1837 "reset unlock called %x %x \n", 1683 "reset unlock called %x %x \n",
1838 cfi->addr_unlock1,cfi->addr_unlock2); 1684 cfi->addr_unlock1,cfi->addr_unlock2);
@@ -1841,7 +1687,7 @@ static inline void jedec_reset(u32 base, struct map_info *map,
1841 } 1687 }
1842 1688
1843 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1689 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1844 /* Some misdesigned intel chips do not respond for 0xF0 for a reset, 1690 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
1845 * so ensure we're in read mode. Send both the Intel and the AMD command 1691 * so ensure we're in read mode. Send both the Intel and the AMD command
1846 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1692 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
1847 * this should be safe. 1693 * this should be safe.
@@ -1851,42 +1697,20 @@ static inline void jedec_reset(u32 base, struct map_info *map,
1851} 1697}
1852 1698
1853 1699
1854static inline __u8 finfo_uaddr(const struct amd_flash_info *finfo, int device_type)
1855{
1856 int uaddr_idx;
1857 __u8 uaddr = MTD_UADDR_NOT_SUPPORTED;
1858
1859 switch ( device_type ) {
1860 case CFI_DEVICETYPE_X8: uaddr_idx = 0; break;
1861 case CFI_DEVICETYPE_X16: uaddr_idx = 1; break;
1862 case CFI_DEVICETYPE_X32: uaddr_idx = 2; break;
1863 default:
1864 printk(KERN_NOTICE "MTD: %s(): unknown device_type %d\n",
1865 __func__, device_type);
1866 goto uaddr_done;
1867 }
1868
1869 uaddr = finfo->uaddr[uaddr_idx];
1870
1871 if (uaddr != MTD_UADDR_NOT_SUPPORTED ) {
1872 /* ASSERT("The unlock addresses for non-8-bit mode
1873 are bollocks. We don't really need an array."); */
1874 uaddr = finfo->uaddr[0];
1875 }
1876
1877 uaddr_done:
1878 return uaddr;
1879}
1880
1881
1882static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1700static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1883{ 1701{
1884 int i,num_erase_regions; 1702 int i,num_erase_regions;
1885 __u8 uaddr; 1703 uint8_t uaddr;
1886 1704
1887 printk("Found: %s\n",jedec_table[index].name); 1705 if (! (jedec_table[index].devtypes & p_cfi->device_type)) {
1706 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n",
1707 jedec_table[index].name, 4 * (1<<p_cfi->device_type));
1708 return 0;
1709 }
1710
1711 printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
1888 1712
1889 num_erase_regions = jedec_table[index].NumEraseRegions; 1713 num_erase_regions = jedec_table[index].nr_regions;
1890 1714
1891 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1715 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1892 if (!p_cfi->cfiq) { 1716 if (!p_cfi->cfiq) {
@@ -1896,9 +1720,9 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1896 1720
1897 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1721 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
1898 1722
1899 p_cfi->cfiq->P_ID = jedec_table[index].CmdSet; 1723 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set;
1900 p_cfi->cfiq->NumEraseRegions = jedec_table[index].NumEraseRegions; 1724 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
1901 p_cfi->cfiq->DevSize = jedec_table[index].DevSize; 1725 p_cfi->cfiq->DevSize = jedec_table[index].dev_size;
1902 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1726 p_cfi->cfi_mode = CFI_MODE_JEDEC;
1903 1727
1904 for (i=0; i<num_erase_regions; i++){ 1728 for (i=0; i<num_erase_regions; i++){
@@ -1910,14 +1734,14 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1910 p_cfi->mfr = jedec_table[index].mfr_id; 1734 p_cfi->mfr = jedec_table[index].mfr_id;
1911 p_cfi->id = jedec_table[index].dev_id; 1735 p_cfi->id = jedec_table[index].dev_id;
1912 1736
1913 uaddr = finfo_uaddr(&jedec_table[index], p_cfi->device_type); 1737 uaddr = jedec_table[index].uaddr;
1914 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1915 kfree( p_cfi->cfiq );
1916 return 0;
1917 }
1918 1738
1919 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1; 1739 /* The table has unlock addresses in _bytes_, and we try not to let
1920 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2; 1740 our brains explode when we see the datasheets talking about address
1741 lines numbered from A-1 to A18. The CFI table has unlock addresses
1742 in device-words according to the mode the device is connected in */
1743 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type;
1744 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type;
1921 1745
1922 return 1; /* ok */ 1746 return 1; /* ok */
1923} 1747}
@@ -1930,14 +1754,14 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1930 * be perfect - consequently there should be some module parameters that 1754 * be perfect - consequently there should be some module parameters that
1931 * could be manually specified to force the chip info. 1755 * could be manually specified to force the chip info.
1932 */ 1756 */
1933static inline int jedec_match( __u32 base, 1757static inline int jedec_match( uint32_t base,
1934 struct map_info *map, 1758 struct map_info *map,
1935 struct cfi_private *cfi, 1759 struct cfi_private *cfi,
1936 const struct amd_flash_info *finfo ) 1760 const struct amd_flash_info *finfo )
1937{ 1761{
1938 int rc = 0; /* failure until all tests pass */ 1762 int rc = 0; /* failure until all tests pass */
1939 u32 mfr, id; 1763 u32 mfr, id;
1940 __u8 uaddr; 1764 uint8_t uaddr;
1941 1765
1942 /* 1766 /*
1943 * The IDs must match. For X16 and X32 devices operating in 1767 * The IDs must match. For X16 and X32 devices operating in
@@ -1950,8 +1774,8 @@ static inline int jedec_match( __u32 base,
1950 */ 1774 */
1951 switch (cfi->device_type) { 1775 switch (cfi->device_type) {
1952 case CFI_DEVICETYPE_X8: 1776 case CFI_DEVICETYPE_X8:
1953 mfr = (__u8)finfo->mfr_id; 1777 mfr = (uint8_t)finfo->mfr_id;
1954 id = (__u8)finfo->dev_id; 1778 id = (uint8_t)finfo->dev_id;
1955 1779
1956 /* bjd: it seems that if we do this, we can end up 1780 /* bjd: it seems that if we do this, we can end up
1957 * detecting 16bit flashes as an 8bit device, even though 1781 * detecting 16bit flashes as an 8bit device, even though
@@ -1964,12 +1788,12 @@ static inline int jedec_match( __u32 base,
1964 } 1788 }
1965 break; 1789 break;
1966 case CFI_DEVICETYPE_X16: 1790 case CFI_DEVICETYPE_X16:
1967 mfr = (__u16)finfo->mfr_id; 1791 mfr = (uint16_t)finfo->mfr_id;
1968 id = (__u16)finfo->dev_id; 1792 id = (uint16_t)finfo->dev_id;
1969 break; 1793 break;
1970 case CFI_DEVICETYPE_X32: 1794 case CFI_DEVICETYPE_X32:
1971 mfr = (__u16)finfo->mfr_id; 1795 mfr = (uint16_t)finfo->mfr_id;
1972 id = (__u32)finfo->dev_id; 1796 id = (uint32_t)finfo->dev_id;
1973 break; 1797 break;
1974 default: 1798 default:
1975 printk(KERN_WARNING 1799 printk(KERN_WARNING
@@ -1984,25 +1808,25 @@ static inline int jedec_match( __u32 base,
1984 /* the part size must fit in the memory window */ 1808 /* the part size must fit in the memory window */
1985 DEBUG( MTD_DEBUG_LEVEL3, 1809 DEBUG( MTD_DEBUG_LEVEL3,
1986 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 1810 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
1987 __func__, base, 1 << finfo->DevSize, base + (1 << finfo->DevSize) ); 1811 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
1988 if ( base + cfi_interleave(cfi) * ( 1 << finfo->DevSize ) > map->size ) { 1812 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
1989 DEBUG( MTD_DEBUG_LEVEL3, 1813 DEBUG( MTD_DEBUG_LEVEL3,
1990 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 1814 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
1991 __func__, finfo->mfr_id, finfo->dev_id, 1815 __func__, finfo->mfr_id, finfo->dev_id,
1992 1 << finfo->DevSize ); 1816 1 << finfo->dev_size );
1993 goto match_done; 1817 goto match_done;
1994 } 1818 }
1995 1819
1996 uaddr = finfo_uaddr(finfo, cfi->device_type); 1820 if (! (finfo->devtypes & cfi->device_type))
1997 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1998 goto match_done; 1821 goto match_done;
1999 } 1822
1823 uaddr = finfo->uaddr;
2000 1824
2001 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 1825 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
2002 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 1826 __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
2003 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 1827 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
2004 && ( unlock_addrs[uaddr].addr1 != cfi->addr_unlock1 || 1828 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
2005 unlock_addrs[uaddr].addr2 != cfi->addr_unlock2 ) ) { 1829 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
2006 DEBUG( MTD_DEBUG_LEVEL3, 1830 DEBUG( MTD_DEBUG_LEVEL3,
2007 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 1831 "MTD %s(): 0x%.4x 0x%.4x did not match\n",
2008 __func__, 1832 __func__,
@@ -2042,7 +1866,7 @@ static inline int jedec_match( __u32 base,
2042 * were truly frobbing a real device. 1866 * were truly frobbing a real device.
2043 */ 1867 */
2044 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 1868 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
2045 if(cfi->addr_unlock1) { 1869 if (cfi->addr_unlock1) {
2046 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1870 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2047 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1871 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2048 } 1872 }
@@ -2068,8 +1892,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
2068 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 1892 if (MTD_UADDR_UNNECESSARY == uaddr_idx)
2069 return 0; 1893 return 0;
2070 1894
2071 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1; 1895 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
2072 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2; 1896 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
2073 } 1897 }
2074 1898
2075 /* Make certain we aren't probing past the end of map */ 1899 /* Make certain we aren't probing past the end of map */
@@ -2081,19 +1905,11 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
2081 1905
2082 } 1906 }
2083 /* Ensure the unlock addresses we try stay inside the map */ 1907 /* Ensure the unlock addresses we try stay inside the map */
2084 probe_offset1 = cfi_build_cmd_addr( 1908 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type);
2085 cfi->addr_unlock1, 1909 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type);
2086 cfi_interleave(cfi),
2087 cfi->device_type);
2088 probe_offset2 = cfi_build_cmd_addr(
2089 cfi->addr_unlock1,
2090 cfi_interleave(cfi),
2091 cfi->device_type);
2092 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 1910 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
2093 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 1911 ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
2094 {
2095 goto retry; 1912 goto retry;
2096 }
2097 1913
2098 /* Reset */ 1914 /* Reset */
2099 jedec_reset(base, map, cfi); 1915 jedec_reset(base, map, cfi);
@@ -2128,8 +1944,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
2128 } 1944 }
2129 goto retry; 1945 goto retry;
2130 } else { 1946 } else {
2131 __u16 mfr; 1947 uint16_t mfr;
2132 __u16 id; 1948 uint16_t id;
2133 1949
2134 /* Make sure it is a chip of the same manufacturer and id */ 1950 /* Make sure it is a chip of the same manufacturer and id */
2135 mfr = jedec_read_mfr(map, base, cfi); 1951 mfr = jedec_read_mfr(map, base, cfi);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 07:56:36 -0500