diff options
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/host/mmc_spi.c | 59 |
1 files changed, 11 insertions, 48 deletions
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c index 1145ea0792e6..62a35822003e 100644 --- a/drivers/mmc/host/mmc_spi.c +++ b/drivers/mmc/host/mmc_spi.c | |||
@@ -182,7 +182,7 @@ mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) | |||
182 | host->data_dma, sizeof(*host->data), | 182 | host->data_dma, sizeof(*host->data), |
183 | DMA_FROM_DEVICE); | 183 | DMA_FROM_DEVICE); |
184 | 184 | ||
185 | status = spi_sync(host->spi, &host->readback); | 185 | status = spi_sync_locked(host->spi, &host->readback); |
186 | 186 | ||
187 | if (host->dma_dev) | 187 | if (host->dma_dev) |
188 | dma_sync_single_for_cpu(host->dma_dev, | 188 | dma_sync_single_for_cpu(host->dma_dev, |
@@ -541,7 +541,7 @@ mmc_spi_command_send(struct mmc_spi_host *host, | |||
541 | host->data_dma, sizeof(*host->data), | 541 | host->data_dma, sizeof(*host->data), |
542 | DMA_BIDIRECTIONAL); | 542 | DMA_BIDIRECTIONAL); |
543 | } | 543 | } |
544 | status = spi_sync(host->spi, &host->m); | 544 | status = spi_sync_locked(host->spi, &host->m); |
545 | 545 | ||
546 | if (host->dma_dev) | 546 | if (host->dma_dev) |
547 | dma_sync_single_for_cpu(host->dma_dev, | 547 | dma_sync_single_for_cpu(host->dma_dev, |
@@ -685,7 +685,7 @@ mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, | |||
685 | host->data_dma, sizeof(*scratch), | 685 | host->data_dma, sizeof(*scratch), |
686 | DMA_BIDIRECTIONAL); | 686 | DMA_BIDIRECTIONAL); |
687 | 687 | ||
688 | status = spi_sync(spi, &host->m); | 688 | status = spi_sync_locked(spi, &host->m); |
689 | 689 | ||
690 | if (status != 0) { | 690 | if (status != 0) { |
691 | dev_dbg(&spi->dev, "write error (%d)\n", status); | 691 | dev_dbg(&spi->dev, "write error (%d)\n", status); |
@@ -822,7 +822,7 @@ mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, | |||
822 | DMA_FROM_DEVICE); | 822 | DMA_FROM_DEVICE); |
823 | } | 823 | } |
824 | 824 | ||
825 | status = spi_sync(spi, &host->m); | 825 | status = spi_sync_locked(spi, &host->m); |
826 | 826 | ||
827 | if (host->dma_dev) { | 827 | if (host->dma_dev) { |
828 | dma_sync_single_for_cpu(host->dma_dev, | 828 | dma_sync_single_for_cpu(host->dma_dev, |
@@ -1018,7 +1018,7 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, | |||
1018 | host->data_dma, sizeof(*scratch), | 1018 | host->data_dma, sizeof(*scratch), |
1019 | DMA_BIDIRECTIONAL); | 1019 | DMA_BIDIRECTIONAL); |
1020 | 1020 | ||
1021 | tmp = spi_sync(spi, &host->m); | 1021 | tmp = spi_sync_locked(spi, &host->m); |
1022 | 1022 | ||
1023 | if (host->dma_dev) | 1023 | if (host->dma_dev) |
1024 | dma_sync_single_for_cpu(host->dma_dev, | 1024 | dma_sync_single_for_cpu(host->dma_dev, |
@@ -1084,6 +1084,9 @@ static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) | |||
1084 | } | 1084 | } |
1085 | #endif | 1085 | #endif |
1086 | 1086 | ||
1087 | /* request exclusive bus access */ | ||
1088 | spi_bus_lock(host->spi->master); | ||
1089 | |||
1087 | /* issue command; then optionally data and stop */ | 1090 | /* issue command; then optionally data and stop */ |
1088 | status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); | 1091 | status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); |
1089 | if (status == 0 && mrq->data) { | 1092 | if (status == 0 && mrq->data) { |
@@ -1094,6 +1097,9 @@ static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) | |||
1094 | mmc_cs_off(host); | 1097 | mmc_cs_off(host); |
1095 | } | 1098 | } |
1096 | 1099 | ||
1100 | /* release the bus */ | ||
1101 | spi_bus_unlock(host->spi->master); | ||
1102 | |||
1097 | mmc_request_done(host->mmc, mrq); | 1103 | mmc_request_done(host->mmc, mrq); |
1098 | } | 1104 | } |
1099 | 1105 | ||
@@ -1290,23 +1296,6 @@ mmc_spi_detect_irq(int irq, void *mmc) | |||
1290 | return IRQ_HANDLED; | 1296 | return IRQ_HANDLED; |
1291 | } | 1297 | } |
1292 | 1298 | ||
1293 | struct count_children { | ||
1294 | unsigned n; | ||
1295 | struct bus_type *bus; | ||
1296 | }; | ||
1297 | |||
1298 | static int maybe_count_child(struct device *dev, void *c) | ||
1299 | { | ||
1300 | struct count_children *ccp = c; | ||
1301 | |||
1302 | if (dev->bus == ccp->bus) { | ||
1303 | if (ccp->n) | ||
1304 | return -EBUSY; | ||
1305 | ccp->n++; | ||
1306 | } | ||
1307 | return 0; | ||
1308 | } | ||
1309 | |||
1310 | static int mmc_spi_probe(struct spi_device *spi) | 1299 | static int mmc_spi_probe(struct spi_device *spi) |
1311 | { | 1300 | { |
1312 | void *ones; | 1301 | void *ones; |
@@ -1338,32 +1327,6 @@ static int mmc_spi_probe(struct spi_device *spi) | |||
1338 | return status; | 1327 | return status; |
1339 | } | 1328 | } |
1340 | 1329 | ||
1341 | /* We can use the bus safely iff nobody else will interfere with us. | ||
1342 | * Most commands consist of one SPI message to issue a command, then | ||
1343 | * several more to collect its response, then possibly more for data | ||
1344 | * transfer. Clocking access to other devices during that period will | ||
1345 | * corrupt the command execution. | ||
1346 | * | ||
1347 | * Until we have software primitives which guarantee non-interference, | ||
1348 | * we'll aim for a hardware-level guarantee. | ||
1349 | * | ||
1350 | * REVISIT we can't guarantee another device won't be added later... | ||
1351 | */ | ||
1352 | if (spi->master->num_chipselect > 1) { | ||
1353 | struct count_children cc; | ||
1354 | |||
1355 | cc.n = 0; | ||
1356 | cc.bus = spi->dev.bus; | ||
1357 | status = device_for_each_child(spi->dev.parent, &cc, | ||
1358 | maybe_count_child); | ||
1359 | if (status < 0) { | ||
1360 | dev_err(&spi->dev, "can't share SPI bus\n"); | ||
1361 | return status; | ||
1362 | } | ||
1363 | |||
1364 | dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n"); | ||
1365 | } | ||
1366 | |||
1367 | /* We need a supply of ones to transmit. This is the only time | 1330 | /* We need a supply of ones to transmit. This is the only time |
1368 | * the CPU touches these, so cache coherency isn't a concern. | 1331 | * the CPU touches these, so cache coherency isn't a concern. |
1369 | * | 1332 | * |