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-rw-r--r--drivers/mmc/sdhci.h185
1 files changed, 185 insertions, 0 deletions
diff --git a/drivers/mmc/sdhci.h b/drivers/mmc/sdhci.h
new file mode 100644
index 000000000000..3b270ef486b4
--- /dev/null
+++ b/drivers/mmc/sdhci.h
@@ -0,0 +1,185 @@
1/*
2 * linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * PCI registers
13 */
14
15#define PCI_SLOT_INFO 0x40 /* 8 bits */
16#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
17#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
18
19/*
20 * Controller registers
21 */
22
23#define SDHCI_DMA_ADDRESS 0x00
24
25#define SDHCI_BLOCK_SIZE 0x04
26
27#define SDHCI_BLOCK_COUNT 0x06
28
29#define SDHCI_ARGUMENT 0x08
30
31#define SDHCI_TRANSFER_MODE 0x0C
32#define SDHCI_TRNS_DMA 0x01
33#define SDHCI_TRNS_BLK_CNT_EN 0x02
34#define SDHCI_TRNS_ACMD12 0x04
35#define SDHCI_TRNS_READ 0x10
36#define SDHCI_TRNS_MULTI 0x20
37
38#define SDHCI_COMMAND 0x0E
39#define SDHCI_CMD_RESP_MASK 0x03
40#define SDHCI_CMD_CRC 0x08
41#define SDHCI_CMD_INDEX 0x10
42#define SDHCI_CMD_DATA 0x20
43
44#define SDHCI_CMD_RESP_NONE 0x00
45#define SDHCI_CMD_RESP_LONG 0x01
46#define SDHCI_CMD_RESP_SHORT 0x02
47#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
48
49#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
50
51#define SDHCI_RESPONSE 0x10
52
53#define SDHCI_BUFFER 0x20
54
55#define SDHCI_PRESENT_STATE 0x24
56#define SDHCI_CMD_INHIBIT 0x00000001
57#define SDHCI_DATA_INHIBIT 0x00000002
58#define SDHCI_DOING_WRITE 0x00000100
59#define SDHCI_DOING_READ 0x00000200
60#define SDHCI_SPACE_AVAILABLE 0x00000400
61#define SDHCI_DATA_AVAILABLE 0x00000800
62#define SDHCI_CARD_PRESENT 0x00010000
63#define SDHCI_WRITE_PROTECT 0x00080000
64
65#define SDHCI_HOST_CONTROL 0x28
66#define SDHCI_CTRL_LED 0x01
67#define SDHCI_CTRL_4BITBUS 0x02
68
69#define SDHCI_POWER_CONTROL 0x29
70
71#define SDHCI_BLOCK_GAP_CONTROL 0x2A
72
73#define SDHCI_WALK_UP_CONTROL 0x2B
74
75#define SDHCI_CLOCK_CONTROL 0x2C
76#define SDHCI_DIVIDER_SHIFT 8
77#define SDHCI_CLOCK_CARD_EN 0x0004
78#define SDHCI_CLOCK_INT_STABLE 0x0002
79#define SDHCI_CLOCK_INT_EN 0x0001
80
81#define SDHCI_TIMEOUT_CONTROL 0x2E
82
83#define SDHCI_SOFTWARE_RESET 0x2F
84#define SDHCI_RESET_ALL 0x01
85#define SDHCI_RESET_CMD 0x02
86#define SDHCI_RESET_DATA 0x04
87
88#define SDHCI_INT_STATUS 0x30
89#define SDHCI_INT_ENABLE 0x34
90#define SDHCI_SIGNAL_ENABLE 0x38
91#define SDHCI_INT_RESPONSE 0x00000001
92#define SDHCI_INT_DATA_END 0x00000002
93#define SDHCI_INT_DMA_END 0x00000008
94#define SDHCI_INT_BUF_EMPTY 0x00000010
95#define SDHCI_INT_BUF_FULL 0x00000020
96#define SDHCI_INT_CARD_INSERT 0x00000040
97#define SDHCI_INT_CARD_REMOVE 0x00000080
98#define SDHCI_INT_CARD_INT 0x00000100
99#define SDHCI_INT_TIMEOUT 0x00010000
100#define SDHCI_INT_CRC 0x00020000
101#define SDHCI_INT_END_BIT 0x00040000
102#define SDHCI_INT_INDEX 0x00080000
103#define SDHCI_INT_DATA_TIMEOUT 0x00100000
104#define SDHCI_INT_DATA_CRC 0x00200000
105#define SDHCI_INT_DATA_END_BIT 0x00400000
106#define SDHCI_INT_BUS_POWER 0x00800000
107#define SDHCI_INT_ACMD12ERR 0x01000000
108
109#define SDHCI_INT_NORMAL_MASK 0x00007FFF
110#define SDHCI_INT_ERROR_MASK 0xFFFF8000
111
112#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
113 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
114#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
115 SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL | \
116 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
117 SDHCI_INT_DATA_END_BIT)
118
119#define SDHCI_ACMD12_ERR 0x3C
120
121/* 3E-3F reserved */
122
123#define SDHCI_CAPABILITIES 0x40
124#define SDHCI_CAN_DO_DMA 0x00400000
125#define SDHCI_CLOCK_BASE_MASK 0x00003F00
126#define SDHCI_CLOCK_BASE_SHIFT 8
127
128/* 44-47 reserved for more caps */
129
130#define SDHCI_MAX_CURRENT 0x48
131
132/* 4C-4F reserved for more max current */
133
134/* 50-FB reserved */
135
136#define SDHCI_SLOT_INT_STATUS 0xFC
137
138#define SDHCI_HOST_VERSION 0xFE
139
140struct sdhci_chip;
141
142struct sdhci_host {
143 struct sdhci_chip *chip;
144 struct mmc_host *mmc; /* MMC structure */
145
146 spinlock_t lock; /* Mutex */
147
148 int flags; /* Host attributes */
149#define SDHCI_USE_DMA (1<<0)
150
151 unsigned int max_clk; /* Max possible freq (MHz) */
152
153 unsigned int clock; /* Current clock (MHz) */
154
155 struct mmc_request *mrq; /* Current request */
156 struct mmc_command *cmd; /* Current command */
157 struct mmc_data *data; /* Current data request */
158
159 struct scatterlist *cur_sg; /* We're working on this */
160 char *mapped_sg; /* This is where it's mapped */
161 int num_sg; /* Entries left */
162 int offset; /* Offset into current sg */
163 int remain; /* Bytes left in current */
164
165 int size; /* Remaining bytes in transfer */
166
167 char slot_descr[20]; /* Name for reservations */
168
169 int irq; /* Device IRQ */
170 int bar; /* PCI BAR index */
171 unsigned long addr; /* Bus address */
172 void __iomem * ioaddr; /* Mapped address */
173
174 struct tasklet_struct card_tasklet; /* Tasklet structures */
175 struct tasklet_struct finish_tasklet;
176
177 struct timer_list timer; /* Timer for timeouts */
178};
179
180struct sdhci_chip {
181 struct pci_dev *pdev;
182
183 int num_slots; /* Slots on controller */
184 struct sdhci_host *hosts[0]; /* Pointers to hosts */
185};