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path: root/drivers/mmc/sdhci.c
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Diffstat (limited to 'drivers/mmc/sdhci.c')
-rw-r--r--drivers/mmc/sdhci.c598
1 files changed, 426 insertions, 172 deletions
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 8e9100bd57ef..fdfc3838dd79 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -8,12 +8,6 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 /*
12 * Note that PIO transfer is rather crappy atm. The buffer full/empty
13 * interrupts aren't reliable so we currently transfer the entire buffer
14 * directly. Patches to solve the problem are welcome.
15 */
16
17#include <linux/delay.h> 11#include <linux/delay.h>
18#include <linux/highmem.h> 12#include <linux/highmem.h>
19#include <linux/pci.h> 13#include <linux/pci.h>
@@ -27,16 +21,50 @@
27#include "sdhci.h" 21#include "sdhci.h"
28 22
29#define DRIVER_NAME "sdhci" 23#define DRIVER_NAME "sdhci"
30#define DRIVER_VERSION "0.11" 24#define DRIVER_VERSION "0.12"
31 25
32#define BUGMAIL "<sdhci-devel@list.drzeus.cx>" 26#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
33 27
34#define DBG(f, x...) \ 28#define DBG(f, x...) \
35 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 29 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
36 30
31static unsigned int debug_nodma = 0;
32static unsigned int debug_forcedma = 0;
33static unsigned int debug_quirks = 0;
34
35#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
36#define SDHCI_QUIRK_FORCE_DMA (1<<1)
37
37static const struct pci_device_id pci_ids[] __devinitdata = { 38static const struct pci_device_id pci_ids[] __devinitdata = {
38 /* handle any SD host controller */ 39 {
39 {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)}, 40 .vendor = PCI_VENDOR_ID_RICOH,
41 .device = PCI_DEVICE_ID_RICOH_R5C822,
42 .subvendor = PCI_VENDOR_ID_IBM,
43 .subdevice = PCI_ANY_ID,
44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
45 SDHCI_QUIRK_FORCE_DMA,
46 },
47
48 {
49 .vendor = PCI_VENDOR_ID_RICOH,
50 .device = PCI_DEVICE_ID_RICOH_R5C822,
51 .subvendor = PCI_ANY_ID,
52 .subdevice = PCI_ANY_ID,
53 .driver_data = SDHCI_QUIRK_FORCE_DMA,
54 },
55
56 {
57 .vendor = PCI_VENDOR_ID_TI,
58 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
59 .subvendor = PCI_ANY_ID,
60 .subdevice = PCI_ANY_ID,
61 .driver_data = SDHCI_QUIRK_FORCE_DMA,
62 },
63
64 { /* Generic SD host controller */
65 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
66 },
67
40 { /* end: all zeroes */ }, 68 { /* end: all zeroes */ },
41}; 69};
42 70
@@ -94,12 +122,27 @@ static void sdhci_dumpregs(struct sdhci_host *host)
94 122
95static void sdhci_reset(struct sdhci_host *host, u8 mask) 123static void sdhci_reset(struct sdhci_host *host, u8 mask)
96{ 124{
125 unsigned long timeout;
126
97 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); 127 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
98 128
99 if (mask & SDHCI_RESET_ALL) { 129 if (mask & SDHCI_RESET_ALL)
100 host->clock = 0; 130 host->clock = 0;
101 131
102 mdelay(50); 132 /* Wait max 100 ms */
133 timeout = 100;
134
135 /* hw clears the bit when it's done */
136 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
137 if (timeout == 0) {
138 printk(KERN_ERR "%s: Reset 0x%x never completed. "
139 "Please report this to " BUGMAIL ".\n",
140 mmc_hostname(host->mmc), (int)mask);
141 sdhci_dumpregs(host);
142 return;
143 }
144 timeout--;
145 mdelay(1);
103 } 146 }
104} 147}
105 148
@@ -109,13 +152,15 @@ static void sdhci_init(struct sdhci_host *host)
109 152
110 sdhci_reset(host, SDHCI_RESET_ALL); 153 sdhci_reset(host, SDHCI_RESET_ALL);
111 154
112 intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL); 155 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
156 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
157 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
158 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
159 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
160 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
113 161
114 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); 162 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
115 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); 163 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
116
117 /* This is unknown magic. */
118 writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
119} 164}
120 165
121static void sdhci_activate_led(struct sdhci_host *host) 166static void sdhci_activate_led(struct sdhci_host *host)
@@ -172,79 +217,96 @@ static inline int sdhci_next_sg(struct sdhci_host* host)
172 return host->num_sg; 217 return host->num_sg;
173} 218}
174 219
175static void sdhci_transfer_pio(struct sdhci_host *host) 220static void sdhci_read_block_pio(struct sdhci_host *host)
176{ 221{
222 int blksize, chunk_remain;
223 u32 data;
177 char *buffer; 224 char *buffer;
178 u32 mask; 225 int size;
179 int bytes, size;
180 unsigned long max_jiffies;
181 226
182 BUG_ON(!host->data); 227 DBG("PIO reading\n");
183 228
184 if (host->num_sg == 0) 229 blksize = host->data->blksz;
185 return; 230 chunk_remain = 0;
186 231 data = 0;
187 bytes = 0;
188 if (host->data->flags & MMC_DATA_READ)
189 mask = SDHCI_DATA_AVAILABLE;
190 else
191 mask = SDHCI_SPACE_AVAILABLE;
192 232
193 buffer = sdhci_kmap_sg(host) + host->offset; 233 buffer = sdhci_kmap_sg(host) + host->offset;
194 234
195 /* Transfer shouldn't take more than 5 s */ 235 while (blksize) {
196 max_jiffies = jiffies + HZ * 5; 236 if (chunk_remain == 0) {
237 data = readl(host->ioaddr + SDHCI_BUFFER);
238 chunk_remain = min(blksize, 4);
239 }
197 240
198 while (host->size > 0) { 241 size = min(host->size, host->remain);
199 if (time_after(jiffies, max_jiffies)) { 242 size = min(size, chunk_remain);
200 printk(KERN_ERR "%s: PIO transfer stalled. "
201 "Please report this to "
202 BUGMAIL ".\n", mmc_hostname(host->mmc));
203 sdhci_dumpregs(host);
204 243
205 sdhci_kunmap_sg(host); 244 chunk_remain -= size;
245 blksize -= size;
246 host->offset += size;
247 host->remain -= size;
248 host->size -= size;
249 while (size) {
250 *buffer = data & 0xFF;
251 buffer++;
252 data >>= 8;
253 size--;
254 }
206 255
207 host->data->error = MMC_ERR_FAILED; 256 if (host->remain == 0) {
208 sdhci_finish_data(host); 257 sdhci_kunmap_sg(host);
209 return; 258 if (sdhci_next_sg(host) == 0) {
259 BUG_ON(blksize != 0);
260 return;
261 }
262 buffer = sdhci_kmap_sg(host);
210 } 263 }
264 }
211 265
212 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask)) 266 sdhci_kunmap_sg(host);
213 continue; 267}
214 268
215 size = min(host->size, host->remain); 269static void sdhci_write_block_pio(struct sdhci_host *host)
270{
271 int blksize, chunk_remain;
272 u32 data;
273 char *buffer;
274 int bytes, size;
216 275
217 if (size >= 4) { 276 DBG("PIO writing\n");
218 if (host->data->flags & MMC_DATA_READ)
219 *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
220 else
221 writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
222 size = 4;
223 } else if (size >= 2) {
224 if (host->data->flags & MMC_DATA_READ)
225 *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
226 else
227 writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
228 size = 2;
229 } else {
230 if (host->data->flags & MMC_DATA_READ)
231 *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
232 else
233 writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
234 size = 1;
235 }
236 277
237 buffer += size; 278 blksize = host->data->blksz;
279 chunk_remain = 4;
280 data = 0;
281
282 bytes = 0;
283 buffer = sdhci_kmap_sg(host) + host->offset;
284
285 while (blksize) {
286 size = min(host->size, host->remain);
287 size = min(size, chunk_remain);
288
289 chunk_remain -= size;
290 blksize -= size;
238 host->offset += size; 291 host->offset += size;
239 host->remain -= size; 292 host->remain -= size;
240
241 bytes += size;
242 host->size -= size; 293 host->size -= size;
294 while (size) {
295 data >>= 8;
296 data |= (u32)*buffer << 24;
297 buffer++;
298 size--;
299 }
300
301 if (chunk_remain == 0) {
302 writel(data, host->ioaddr + SDHCI_BUFFER);
303 chunk_remain = min(blksize, 4);
304 }
243 305
244 if (host->remain == 0) { 306 if (host->remain == 0) {
245 sdhci_kunmap_sg(host); 307 sdhci_kunmap_sg(host);
246 if (sdhci_next_sg(host) == 0) { 308 if (sdhci_next_sg(host) == 0) {
247 DBG("PIO transfer: %d bytes\n", bytes); 309 BUG_ON(blksize != 0);
248 return; 310 return;
249 } 311 }
250 buffer = sdhci_kmap_sg(host); 312 buffer = sdhci_kmap_sg(host);
@@ -252,38 +314,87 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
252 } 314 }
253 315
254 sdhci_kunmap_sg(host); 316 sdhci_kunmap_sg(host);
317}
318
319static void sdhci_transfer_pio(struct sdhci_host *host)
320{
321 u32 mask;
322
323 BUG_ON(!host->data);
324
325 if (host->size == 0)
326 return;
327
328 if (host->data->flags & MMC_DATA_READ)
329 mask = SDHCI_DATA_AVAILABLE;
330 else
331 mask = SDHCI_SPACE_AVAILABLE;
332
333 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
334 if (host->data->flags & MMC_DATA_READ)
335 sdhci_read_block_pio(host);
336 else
337 sdhci_write_block_pio(host);
255 338
256 DBG("PIO transfer: %d bytes\n", bytes); 339 if (host->size == 0)
340 break;
341
342 BUG_ON(host->num_sg == 0);
343 }
344
345 DBG("PIO transfer complete.\n");
257} 346}
258 347
259static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) 348static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
260{ 349{
261 u16 mode; 350 u8 count;
351 unsigned target_timeout, current_timeout;
262 352
263 WARN_ON(host->data); 353 WARN_ON(host->data);
264 354
265 if (data == NULL) { 355 if (data == NULL)
266 writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
267 return; 356 return;
268 }
269 357
270 DBG("blksz %04x blks %04x flags %08x\n", 358 DBG("blksz %04x blks %04x flags %08x\n",
271 data->blksz, data->blocks, data->flags); 359 data->blksz, data->blocks, data->flags);
272 DBG("tsac %d ms nsac %d clk\n", 360 DBG("tsac %d ms nsac %d clk\n",
273 data->timeout_ns / 1000000, data->timeout_clks); 361 data->timeout_ns / 1000000, data->timeout_clks);
274 362
275 mode = SDHCI_TRNS_BLK_CNT_EN; 363 /* Sanity checks */
276 if (data->blocks > 1) 364 BUG_ON(data->blksz * data->blocks > 524288);
277 mode |= SDHCI_TRNS_MULTI; 365 BUG_ON(data->blksz > host->max_block);
278 if (data->flags & MMC_DATA_READ) 366 BUG_ON(data->blocks > 65535);
279 mode |= SDHCI_TRNS_READ;
280 if (host->flags & SDHCI_USE_DMA)
281 mode |= SDHCI_TRNS_DMA;
282 367
283 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); 368 /* timeout in us */
369 target_timeout = data->timeout_ns / 1000 +
370 data->timeout_clks / host->clock;
284 371
285 writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE); 372 /*
286 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); 373 * Figure out needed cycles.
374 * We do this in steps in order to fit inside a 32 bit int.
375 * The first step is the minimum timeout, which will have a
376 * minimum resolution of 6 bits:
377 * (1) 2^13*1000 > 2^22,
378 * (2) host->timeout_clk < 2^16
379 * =>
380 * (1) / (2) > 2^6
381 */
382 count = 0;
383 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
384 while (current_timeout < target_timeout) {
385 count++;
386 current_timeout <<= 1;
387 if (count >= 0xF)
388 break;
389 }
390
391 if (count >= 0xF) {
392 printk(KERN_WARNING "%s: Too large timeout requested!\n",
393 mmc_hostname(host->mmc));
394 count = 0xE;
395 }
396
397 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
287 398
288 if (host->flags & SDHCI_USE_DMA) { 399 if (host->flags & SDHCI_USE_DMA) {
289 int count; 400 int count;
@@ -302,12 +413,37 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
302 host->offset = 0; 413 host->offset = 0;
303 host->remain = host->cur_sg->length; 414 host->remain = host->cur_sg->length;
304 } 415 }
416
417 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
418 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
419 host->ioaddr + SDHCI_BLOCK_SIZE);
420 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
421}
422
423static void sdhci_set_transfer_mode(struct sdhci_host *host,
424 struct mmc_data *data)
425{
426 u16 mode;
427
428 WARN_ON(host->data);
429
430 if (data == NULL)
431 return;
432
433 mode = SDHCI_TRNS_BLK_CNT_EN;
434 if (data->blocks > 1)
435 mode |= SDHCI_TRNS_MULTI;
436 if (data->flags & MMC_DATA_READ)
437 mode |= SDHCI_TRNS_READ;
438 if (host->flags & SDHCI_USE_DMA)
439 mode |= SDHCI_TRNS_DMA;
440
441 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
305} 442}
306 443
307static void sdhci_finish_data(struct sdhci_host *host) 444static void sdhci_finish_data(struct sdhci_host *host)
308{ 445{
309 struct mmc_data *data; 446 struct mmc_data *data;
310 u32 intmask;
311 u16 blocks; 447 u16 blocks;
312 448
313 BUG_ON(!host->data); 449 BUG_ON(!host->data);
@@ -318,14 +454,6 @@ static void sdhci_finish_data(struct sdhci_host *host)
318 if (host->flags & SDHCI_USE_DMA) { 454 if (host->flags & SDHCI_USE_DMA) {
319 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, 455 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
320 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); 456 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
321 } else {
322 intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
323 intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
324 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
325
326 intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
327 intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
328 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
329 } 457 }
330 458
331 /* 459 /*
@@ -342,9 +470,7 @@ static void sdhci_finish_data(struct sdhci_host *host)
342 "though there were blocks left. Please report this " 470 "though there were blocks left. Please report this "
343 "to " BUGMAIL ".\n", mmc_hostname(host->mmc)); 471 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
344 data->error = MMC_ERR_FAILED; 472 data->error = MMC_ERR_FAILED;
345 } 473 } else if (host->size != 0) {
346
347 if (host->size != 0) {
348 printk(KERN_ERR "%s: %d bytes were left untransferred. " 474 printk(KERN_ERR "%s: %d bytes were left untransferred. "
349 "Please report this to " BUGMAIL ".\n", 475 "Please report this to " BUGMAIL ".\n",
350 mmc_hostname(host->mmc), host->size); 476 mmc_hostname(host->mmc), host->size);
@@ -371,27 +497,38 @@ static void sdhci_finish_data(struct sdhci_host *host)
371static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 497static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
372{ 498{
373 int flags; 499 int flags;
374 u32 present; 500 u32 mask;
375 unsigned long max_jiffies; 501 unsigned long timeout;
376 502
377 WARN_ON(host->cmd); 503 WARN_ON(host->cmd);
378 504
379 DBG("Sending cmd (%x)\n", cmd->opcode); 505 DBG("Sending cmd (%x)\n", cmd->opcode);
380 506
381 /* Wait max 10 ms */ 507 /* Wait max 10 ms */
382 max_jiffies = jiffies + (HZ + 99)/100; 508 timeout = 10;
383 do { 509
384 if (time_after(jiffies, max_jiffies)) { 510 mask = SDHCI_CMD_INHIBIT;
511 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
512 mask |= SDHCI_DATA_INHIBIT;
513
514 /* We shouldn't wait for data inihibit for stop commands, even
515 though they might use busy signaling */
516 if (host->mrq->data && (cmd == host->mrq->data->stop))
517 mask &= ~SDHCI_DATA_INHIBIT;
518
519 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
520 if (timeout == 0) {
385 printk(KERN_ERR "%s: Controller never released " 521 printk(KERN_ERR "%s: Controller never released "
386 "inhibit bits. Please report this to " 522 "inhibit bit(s). Please report this to "
387 BUGMAIL ".\n", mmc_hostname(host->mmc)); 523 BUGMAIL ".\n", mmc_hostname(host->mmc));
388 sdhci_dumpregs(host); 524 sdhci_dumpregs(host);
389 cmd->error = MMC_ERR_FAILED; 525 cmd->error = MMC_ERR_FAILED;
390 tasklet_schedule(&host->finish_tasklet); 526 tasklet_schedule(&host->finish_tasklet);
391 return; 527 return;
392 } 528 }
393 present = readl(host->ioaddr + SDHCI_PRESENT_STATE); 529 timeout--;
394 } while (present & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)); 530 mdelay(1);
531 }
395 532
396 mod_timer(&host->timer, jiffies + 10 * HZ); 533 mod_timer(&host->timer, jiffies + 10 * HZ);
397 534
@@ -401,6 +538,8 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
401 538
402 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); 539 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
403 540
541 sdhci_set_transfer_mode(host, cmd->data);
542
404 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 543 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
405 printk(KERN_ERR "%s: Unsupported response type! " 544 printk(KERN_ERR "%s: Unsupported response type! "
406 "Please report this to " BUGMAIL ".\n", 545 "Please report this to " BUGMAIL ".\n",
@@ -426,7 +565,7 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
426 if (cmd->data) 565 if (cmd->data)
427 flags |= SDHCI_CMD_DATA; 566 flags |= SDHCI_CMD_DATA;
428 567
429 writel(SDHCI_MAKE_CMD(cmd->opcode, flags), 568 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
430 host->ioaddr + SDHCI_COMMAND); 569 host->ioaddr + SDHCI_COMMAND);
431} 570}
432 571
@@ -456,31 +595,9 @@ static void sdhci_finish_command(struct sdhci_host *host)
456 595
457 DBG("Ending cmd (%x)\n", host->cmd->opcode); 596 DBG("Ending cmd (%x)\n", host->cmd->opcode);
458 597
459 if (host->cmd->data) { 598 if (host->cmd->data)
460 u32 intmask;
461
462 host->data = host->cmd->data; 599 host->data = host->cmd->data;
463 600 else
464 if (!(host->flags & SDHCI_USE_DMA)) {
465 /*
466 * Don't enable the interrupts until now to make sure we
467 * get stable handling of the FIFO.
468 */
469 intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
470 intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
471 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
472
473 intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
474 intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
475 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
476
477 /*
478 * The buffer interrupts are to unreliable so we
479 * start the transfer immediatly.
480 */
481 sdhci_transfer_pio(host);
482 }
483 } else
484 tasklet_schedule(&host->finish_tasklet); 601 tasklet_schedule(&host->finish_tasklet);
485 602
486 host->cmd = NULL; 603 host->cmd = NULL;
@@ -490,7 +607,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
490{ 607{
491 int div; 608 int div;
492 u16 clk; 609 u16 clk;
493 unsigned long max_jiffies; 610 unsigned long timeout;
494 611
495 if (clock == host->clock) 612 if (clock == host->clock)
496 return; 613 return;
@@ -511,17 +628,19 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
511 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); 628 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
512 629
513 /* Wait max 10 ms */ 630 /* Wait max 10 ms */
514 max_jiffies = jiffies + (HZ + 99)/100; 631 timeout = 10;
515 do { 632 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
516 if (time_after(jiffies, max_jiffies)) { 633 & SDHCI_CLOCK_INT_STABLE)) {
634 if (timeout == 0) {
517 printk(KERN_ERR "%s: Internal clock never stabilised. " 635 printk(KERN_ERR "%s: Internal clock never stabilised. "
518 "Please report this to " BUGMAIL ".\n", 636 "Please report this to " BUGMAIL ".\n",
519 mmc_hostname(host->mmc)); 637 mmc_hostname(host->mmc));
520 sdhci_dumpregs(host); 638 sdhci_dumpregs(host);
521 return; 639 return;
522 } 640 }
523 clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL); 641 timeout--;
524 } while (!(clk & SDHCI_CLOCK_INT_STABLE)); 642 mdelay(1);
643 }
525 644
526 clk |= SDHCI_CLOCK_CARD_EN; 645 clk |= SDHCI_CLOCK_CARD_EN;
527 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); 646 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
@@ -530,6 +649,46 @@ out:
530 host->clock = clock; 649 host->clock = clock;
531} 650}
532 651
652static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
653{
654 u8 pwr;
655
656 if (host->power == power)
657 return;
658
659 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
660
661 if (power == (unsigned short)-1)
662 goto out;
663
664 pwr = SDHCI_POWER_ON;
665
666 switch (power) {
667 case MMC_VDD_170:
668 case MMC_VDD_180:
669 case MMC_VDD_190:
670 pwr |= SDHCI_POWER_180;
671 break;
672 case MMC_VDD_290:
673 case MMC_VDD_300:
674 case MMC_VDD_310:
675 pwr |= SDHCI_POWER_300;
676 break;
677 case MMC_VDD_320:
678 case MMC_VDD_330:
679 case MMC_VDD_340:
680 pwr |= SDHCI_POWER_330;
681 break;
682 default:
683 BUG();
684 }
685
686 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
687
688out:
689 host->power = power;
690}
691
533/*****************************************************************************\ 692/*****************************************************************************\
534 * * 693 * *
535 * MMC callbacks * 694 * MMC callbacks *
@@ -576,17 +735,15 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
576 */ 735 */
577 if (ios->power_mode == MMC_POWER_OFF) { 736 if (ios->power_mode == MMC_POWER_OFF) {
578 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); 737 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
579 spin_unlock_irqrestore(&host->lock, flags);
580 sdhci_init(host); 738 sdhci_init(host);
581 spin_lock_irqsave(&host->lock, flags);
582 } 739 }
583 740
584 sdhci_set_clock(host, ios->clock); 741 sdhci_set_clock(host, ios->clock);
585 742
586 if (ios->power_mode == MMC_POWER_OFF) 743 if (ios->power_mode == MMC_POWER_OFF)
587 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); 744 sdhci_set_power(host, -1);
588 else 745 else
589 writeb(0xFF, host->ioaddr + SDHCI_POWER_CONTROL); 746 sdhci_set_power(host, ios->vdd);
590 747
591 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); 748 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
592 if (ios->bus_width == MMC_BUS_WIDTH_4) 749 if (ios->bus_width == MMC_BUS_WIDTH_4)
@@ -679,6 +836,19 @@ static void sdhci_tasklet_finish(unsigned long param)
679 if ((mrq->cmd->error != MMC_ERR_NONE) || 836 if ((mrq->cmd->error != MMC_ERR_NONE) ||
680 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || 837 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
681 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) { 838 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
839
840 /* Some controllers need this kick or reset won't work here */
841 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
842 unsigned int clock;
843
844 /* This is to force an update */
845 clock = host->clock;
846 host->clock = 0;
847 sdhci_set_clock(host, clock);
848 }
849
850 /* Spec says we should do both at the same time, but Ricoh
851 controllers do not like that. */
682 sdhci_reset(host, SDHCI_RESET_CMD); 852 sdhci_reset(host, SDHCI_RESET_CMD);
683 sdhci_reset(host, SDHCI_RESET_DATA); 853 sdhci_reset(host, SDHCI_RESET_DATA);
684 } 854 }
@@ -793,7 +963,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
793 if (host->data->error != MMC_ERR_NONE) 963 if (host->data->error != MMC_ERR_NONE)
794 sdhci_finish_data(host); 964 sdhci_finish_data(host);
795 else { 965 else {
796 if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY)) 966 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
797 sdhci_transfer_pio(host); 967 sdhci_transfer_pio(host);
798 968
799 if (intmask & SDHCI_INT_DATA_END) 969 if (intmask & SDHCI_INT_DATA_END)
@@ -818,50 +988,44 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
818 988
819 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); 989 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
820 990
821 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) 991 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
992 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
993 host->ioaddr + SDHCI_INT_STATUS);
822 tasklet_schedule(&host->card_tasklet); 994 tasklet_schedule(&host->card_tasklet);
995 }
823 996
824 if (intmask & SDHCI_INT_CMD_MASK) { 997 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
825 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
826 998
999 if (intmask & SDHCI_INT_CMD_MASK) {
827 writel(intmask & SDHCI_INT_CMD_MASK, 1000 writel(intmask & SDHCI_INT_CMD_MASK,
828 host->ioaddr + SDHCI_INT_STATUS); 1001 host->ioaddr + SDHCI_INT_STATUS);
1002 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
829 } 1003 }
830 1004
831 if (intmask & SDHCI_INT_DATA_MASK) { 1005 if (intmask & SDHCI_INT_DATA_MASK) {
832 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
833
834 writel(intmask & SDHCI_INT_DATA_MASK, 1006 writel(intmask & SDHCI_INT_DATA_MASK,
835 host->ioaddr + SDHCI_INT_STATUS); 1007 host->ioaddr + SDHCI_INT_STATUS);
1008 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
836 } 1009 }
837 1010
838 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1011 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
839 1012
840 if (intmask & SDHCI_INT_CARD_INT) {
841 printk(KERN_ERR "%s: Unexpected card interrupt. Please "
842 "report this to " BUGMAIL ".\n",
843 mmc_hostname(host->mmc));
844 sdhci_dumpregs(host);
845 }
846
847 if (intmask & SDHCI_INT_BUS_POWER) { 1013 if (intmask & SDHCI_INT_BUS_POWER) {
848 printk(KERN_ERR "%s: Unexpected bus power interrupt. Please " 1014 printk(KERN_ERR "%s: Card is consuming too much power!\n",
849 "report this to " BUGMAIL ".\n",
850 mmc_hostname(host->mmc)); 1015 mmc_hostname(host->mmc));
851 sdhci_dumpregs(host); 1016 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
852 } 1017 }
853 1018
854 if (intmask & SDHCI_INT_ACMD12ERR) { 1019 intmask &= SDHCI_INT_BUS_POWER;
855 printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please " 1020
1021 if (intmask) {
1022 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
856 "report this to " BUGMAIL ".\n", 1023 "report this to " BUGMAIL ".\n",
857 mmc_hostname(host->mmc)); 1024 mmc_hostname(host->mmc), intmask);
858 sdhci_dumpregs(host); 1025 sdhci_dumpregs(host);
859 1026
860 writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
861 }
862
863 if (intmask)
864 writel(intmask, host->ioaddr + SDHCI_INT_STATUS); 1027 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1028 }
865 1029
866 result = IRQ_HANDLED; 1030 result = IRQ_HANDLED;
867 1031
@@ -954,6 +1118,7 @@ static int sdhci_resume (struct pci_dev *pdev)
954static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) 1118static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
955{ 1119{
956 int ret; 1120 int ret;
1121 unsigned int version;
957 struct sdhci_chip *chip; 1122 struct sdhci_chip *chip;
958 struct mmc_host *mmc; 1123 struct mmc_host *mmc;
959 struct sdhci_host *host; 1124 struct sdhci_host *host;
@@ -985,6 +1150,16 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
985 return -ENODEV; 1150 return -ENODEV;
986 } 1151 }
987 1152
1153 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1154 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1155 return -ENODEV;
1156 }
1157
1158 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1159 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1160 return -ENODEV;
1161 }
1162
988 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); 1163 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
989 if (!mmc) 1164 if (!mmc)
990 return -ENOMEM; 1165 return -ENOMEM;
@@ -1012,9 +1187,30 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1012 goto release; 1187 goto release;
1013 } 1188 }
1014 1189
1190 sdhci_reset(host, SDHCI_RESET_ALL);
1191
1192 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1193 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1194 if (version != 0) {
1195 printk(KERN_ERR "%s: Unknown controller version (%d). "
1196 "You may experience problems.\n", host->slot_descr,
1197 version);
1198 }
1199
1015 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); 1200 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1016 1201
1017 if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01)) 1202 if (debug_nodma)
1203 DBG("DMA forced off\n");
1204 else if (debug_forcedma) {
1205 DBG("DMA forced on\n");
1206 host->flags |= SDHCI_USE_DMA;
1207 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1208 host->flags |= SDHCI_USE_DMA;
1209 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1210 DBG("Controller doesn't have DMA interface\n");
1211 else if (!(caps & SDHCI_CAN_DO_DMA))
1212 DBG("Controller doesn't have DMA capability\n");
1213 else
1018 host->flags |= SDHCI_USE_DMA; 1214 host->flags |= SDHCI_USE_DMA;
1019 1215
1020 if (host->flags & SDHCI_USE_DMA) { 1216 if (host->flags & SDHCI_USE_DMA) {
@@ -1030,17 +1226,58 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1030 else /* XXX: Hack to get MMC layer to avoid highmem */ 1226 else /* XXX: Hack to get MMC layer to avoid highmem */
1031 pdev->dma_mask = 0; 1227 pdev->dma_mask = 0;
1032 1228
1033 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 1229 host->max_clk =
1230 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1231 if (host->max_clk == 0) {
1232 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1233 "frequency.\n", host->slot_descr);
1234 ret = -ENODEV;
1235 goto unmap;
1236 }
1034 host->max_clk *= 1000000; 1237 host->max_clk *= 1000000;
1035 1238
1239 host->timeout_clk =
1240 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1241 if (host->timeout_clk == 0) {
1242 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1243 "frequency.\n", host->slot_descr);
1244 ret = -ENODEV;
1245 goto unmap;
1246 }
1247 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1248 host->timeout_clk *= 1000;
1249
1250 host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1251 if (host->max_block >= 3) {
1252 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1253 host->slot_descr);
1254 ret = -ENODEV;
1255 goto unmap;
1256 }
1257 host->max_block = 512 << host->max_block;
1258
1036 /* 1259 /*
1037 * Set host parameters. 1260 * Set host parameters.
1038 */ 1261 */
1039 mmc->ops = &sdhci_ops; 1262 mmc->ops = &sdhci_ops;
1040 mmc->f_min = host->max_clk / 256; 1263 mmc->f_min = host->max_clk / 256;
1041 mmc->f_max = host->max_clk; 1264 mmc->f_max = host->max_clk;
1042 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; 1265 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1043 mmc->caps = MMC_CAP_4_BIT_DATA; 1266
1267 mmc->ocr_avail = 0;
1268 if (caps & SDHCI_CAN_VDD_330)
1269 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1270 else if (caps & SDHCI_CAN_VDD_300)
1271 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1272 else if (caps & SDHCI_CAN_VDD_180)
1273 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1274
1275 if (mmc->ocr_avail == 0) {
1276 printk(KERN_ERR "%s: Hardware doesn't report any "
1277 "support voltages.\n", host->slot_descr);
1278 ret = -ENODEV;
1279 goto unmap;
1280 }
1044 1281
1045 spin_lock_init(&host->lock); 1282 spin_lock_init(&host->lock);
1046 1283
@@ -1054,10 +1291,10 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1054 mmc->max_phys_segs = 16; 1291 mmc->max_phys_segs = 16;
1055 1292
1056 /* 1293 /*
1057 * Maximum number of sectors in one transfer. Limited by sector 1294 * Maximum number of sectors in one transfer. Limited by DMA boundary
1058 * count register. 1295 * size (512KiB), which means (512 KiB/512=) 1024 entries.
1059 */ 1296 */
1060 mmc->max_sectors = 0x3FFF; 1297 mmc->max_sectors = 1024;
1061 1298
1062 /* 1299 /*
1063 * Maximum segment size. Could be one segment with the maximum number 1300 * Maximum segment size. Could be one segment with the maximum number
@@ -1075,10 +1312,10 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1075 1312
1076 setup_timer(&host->timer, sdhci_timeout_timer, (long)host); 1313 setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
1077 1314
1078 ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ, 1315 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1079 host->slot_descr, host); 1316 host->slot_descr, host);
1080 if (ret) 1317 if (ret)
1081 goto unmap; 1318 goto untasklet;
1082 1319
1083 sdhci_init(host); 1320 sdhci_init(host);
1084 1321
@@ -1097,10 +1334,10 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1097 1334
1098 return 0; 1335 return 0;
1099 1336
1100unmap: 1337untasklet:
1101 tasklet_kill(&host->card_tasklet); 1338 tasklet_kill(&host->card_tasklet);
1102 tasklet_kill(&host->finish_tasklet); 1339 tasklet_kill(&host->finish_tasklet);
1103 1340unmap:
1104 iounmap(host->ioaddr); 1341 iounmap(host->ioaddr);
1105release: 1342release:
1106 pci_release_region(pdev, host->bar); 1343 pci_release_region(pdev, host->bar);
@@ -1144,13 +1381,18 @@ static int __devinit sdhci_probe(struct pci_dev *pdev,
1144 const struct pci_device_id *ent) 1381 const struct pci_device_id *ent)
1145{ 1382{
1146 int ret, i; 1383 int ret, i;
1147 u8 slots; 1384 u8 slots, rev;
1148 struct sdhci_chip *chip; 1385 struct sdhci_chip *chip;
1149 1386
1150 BUG_ON(pdev == NULL); 1387 BUG_ON(pdev == NULL);
1151 BUG_ON(ent == NULL); 1388 BUG_ON(ent == NULL);
1152 1389
1153 DBG("found at %s\n", pci_name(pdev)); 1390 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1391
1392 printk(KERN_INFO DRIVER_NAME
1393 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1394 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1395 (int)rev);
1154 1396
1155 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 1397 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1156 if (ret) 1398 if (ret)
@@ -1173,6 +1415,10 @@ static int __devinit sdhci_probe(struct pci_dev *pdev,
1173 } 1415 }
1174 1416
1175 chip->pdev = pdev; 1417 chip->pdev = pdev;
1418 chip->quirks = ent->driver_data;
1419
1420 if (debug_quirks)
1421 chip->quirks = debug_quirks;
1176 1422
1177 chip->num_slots = slots; 1423 chip->num_slots = slots;
1178 pci_set_drvdata(pdev, chip); 1424 pci_set_drvdata(pdev, chip);
@@ -1251,7 +1497,15 @@ static void __exit sdhci_drv_exit(void)
1251module_init(sdhci_drv_init); 1497module_init(sdhci_drv_init);
1252module_exit(sdhci_drv_exit); 1498module_exit(sdhci_drv_exit);
1253 1499
1500module_param(debug_nodma, uint, 0444);
1501module_param(debug_forcedma, uint, 0444);
1502module_param(debug_quirks, uint, 0444);
1503
1254MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); 1504MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1255MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); 1505MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1256MODULE_VERSION(DRIVER_VERSION); 1506MODULE_VERSION(DRIVER_VERSION);
1257MODULE_LICENSE("GPL"); 1507MODULE_LICENSE("GPL");
1508
1509MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1510MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1511MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");