diff options
Diffstat (limited to 'drivers/mmc/omap.c')
-rw-r--r-- | drivers/mmc/omap.c | 275 |
1 files changed, 168 insertions, 107 deletions
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c index 762fa2895891..435d331e772a 100644 --- a/drivers/mmc/omap.c +++ b/drivers/mmc/omap.c | |||
@@ -38,7 +38,57 @@ | |||
38 | #include <asm/arch/fpga.h> | 38 | #include <asm/arch/fpga.h> |
39 | #include <asm/arch/tps65010.h> | 39 | #include <asm/arch/tps65010.h> |
40 | 40 | ||
41 | #include "omap.h" | 41 | #define OMAP_MMC_REG_CMD 0x00 |
42 | #define OMAP_MMC_REG_ARGL 0x04 | ||
43 | #define OMAP_MMC_REG_ARGH 0x08 | ||
44 | #define OMAP_MMC_REG_CON 0x0c | ||
45 | #define OMAP_MMC_REG_STAT 0x10 | ||
46 | #define OMAP_MMC_REG_IE 0x14 | ||
47 | #define OMAP_MMC_REG_CTO 0x18 | ||
48 | #define OMAP_MMC_REG_DTO 0x1c | ||
49 | #define OMAP_MMC_REG_DATA 0x20 | ||
50 | #define OMAP_MMC_REG_BLEN 0x24 | ||
51 | #define OMAP_MMC_REG_NBLK 0x28 | ||
52 | #define OMAP_MMC_REG_BUF 0x2c | ||
53 | #define OMAP_MMC_REG_SDIO 0x34 | ||
54 | #define OMAP_MMC_REG_REV 0x3c | ||
55 | #define OMAP_MMC_REG_RSP0 0x40 | ||
56 | #define OMAP_MMC_REG_RSP1 0x44 | ||
57 | #define OMAP_MMC_REG_RSP2 0x48 | ||
58 | #define OMAP_MMC_REG_RSP3 0x4c | ||
59 | #define OMAP_MMC_REG_RSP4 0x50 | ||
60 | #define OMAP_MMC_REG_RSP5 0x54 | ||
61 | #define OMAP_MMC_REG_RSP6 0x58 | ||
62 | #define OMAP_MMC_REG_RSP7 0x5c | ||
63 | #define OMAP_MMC_REG_IOSR 0x60 | ||
64 | #define OMAP_MMC_REG_SYSC 0x64 | ||
65 | #define OMAP_MMC_REG_SYSS 0x68 | ||
66 | |||
67 | #define OMAP_MMC_STAT_CARD_ERR (1 << 14) | ||
68 | #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) | ||
69 | #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) | ||
70 | #define OMAP_MMC_STAT_A_EMPTY (1 << 11) | ||
71 | #define OMAP_MMC_STAT_A_FULL (1 << 10) | ||
72 | #define OMAP_MMC_STAT_CMD_CRC (1 << 8) | ||
73 | #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) | ||
74 | #define OMAP_MMC_STAT_DATA_CRC (1 << 6) | ||
75 | #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) | ||
76 | #define OMAP_MMC_STAT_END_BUSY (1 << 4) | ||
77 | #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) | ||
78 | #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) | ||
79 | #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) | ||
80 | |||
81 | #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg) | ||
82 | #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg) | ||
83 | |||
84 | /* | ||
85 | * Command types | ||
86 | */ | ||
87 | #define OMAP_MMC_CMDTYPE_BC 0 | ||
88 | #define OMAP_MMC_CMDTYPE_BCR 1 | ||
89 | #define OMAP_MMC_CMDTYPE_AC 2 | ||
90 | #define OMAP_MMC_CMDTYPE_ADTC 3 | ||
91 | |||
42 | 92 | ||
43 | #define DRIVER_NAME "mmci-omap" | 93 | #define DRIVER_NAME "mmci-omap" |
44 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) | 94 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
@@ -60,8 +110,9 @@ struct mmc_omap_host { | |||
60 | unsigned char id; /* 16xx chips have 2 MMC blocks */ | 110 | unsigned char id; /* 16xx chips have 2 MMC blocks */ |
61 | struct clk * iclk; | 111 | struct clk * iclk; |
62 | struct clk * fclk; | 112 | struct clk * fclk; |
63 | struct resource *res; | 113 | struct resource *mem_res; |
64 | void __iomem *base; | 114 | void __iomem *virt_base; |
115 | unsigned int phys_base; | ||
65 | int irq; | 116 | int irq; |
66 | unsigned char bus_mode; | 117 | unsigned char bus_mode; |
67 | unsigned char hw_bus_mode; | 118 | unsigned char hw_bus_mode; |
@@ -191,16 +242,16 @@ mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) | |||
191 | 242 | ||
192 | clk_enable(host->fclk); | 243 | clk_enable(host->fclk); |
193 | 244 | ||
194 | OMAP_MMC_WRITE(host->base, CTO, 200); | 245 | OMAP_MMC_WRITE(host, CTO, 200); |
195 | OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff); | 246 | OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); |
196 | OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16); | 247 | OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); |
197 | OMAP_MMC_WRITE(host->base, IE, | 248 | OMAP_MMC_WRITE(host, IE, |
198 | OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | | 249 | OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | |
199 | OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | | 250 | OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | |
200 | OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | | 251 | OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | |
201 | OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | | 252 | OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | |
202 | OMAP_MMC_STAT_END_OF_DATA); | 253 | OMAP_MMC_STAT_END_OF_DATA); |
203 | OMAP_MMC_WRITE(host->base, CMD, cmdreg); | 254 | OMAP_MMC_WRITE(host, CMD, cmdreg); |
204 | } | 255 | } |
205 | 256 | ||
206 | static void | 257 | static void |
@@ -296,22 +347,22 @@ mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) | |||
296 | if (cmd->flags & MMC_RSP_136) { | 347 | if (cmd->flags & MMC_RSP_136) { |
297 | /* response type 2 */ | 348 | /* response type 2 */ |
298 | cmd->resp[3] = | 349 | cmd->resp[3] = |
299 | OMAP_MMC_READ(host->base, RSP0) | | 350 | OMAP_MMC_READ(host, RSP0) | |
300 | (OMAP_MMC_READ(host->base, RSP1) << 16); | 351 | (OMAP_MMC_READ(host, RSP1) << 16); |
301 | cmd->resp[2] = | 352 | cmd->resp[2] = |
302 | OMAP_MMC_READ(host->base, RSP2) | | 353 | OMAP_MMC_READ(host, RSP2) | |
303 | (OMAP_MMC_READ(host->base, RSP3) << 16); | 354 | (OMAP_MMC_READ(host, RSP3) << 16); |
304 | cmd->resp[1] = | 355 | cmd->resp[1] = |
305 | OMAP_MMC_READ(host->base, RSP4) | | 356 | OMAP_MMC_READ(host, RSP4) | |
306 | (OMAP_MMC_READ(host->base, RSP5) << 16); | 357 | (OMAP_MMC_READ(host, RSP5) << 16); |
307 | cmd->resp[0] = | 358 | cmd->resp[0] = |
308 | OMAP_MMC_READ(host->base, RSP6) | | 359 | OMAP_MMC_READ(host, RSP6) | |
309 | (OMAP_MMC_READ(host->base, RSP7) << 16); | 360 | (OMAP_MMC_READ(host, RSP7) << 16); |
310 | } else { | 361 | } else { |
311 | /* response types 1, 1b, 3, 4, 5, 6 */ | 362 | /* response types 1, 1b, 3, 4, 5, 6 */ |
312 | cmd->resp[0] = | 363 | cmd->resp[0] = |
313 | OMAP_MMC_READ(host->base, RSP6) | | 364 | OMAP_MMC_READ(host, RSP6) | |
314 | (OMAP_MMC_READ(host->base, RSP7) << 16); | 365 | (OMAP_MMC_READ(host, RSP7) << 16); |
315 | } | 366 | } |
316 | } | 367 | } |
317 | 368 | ||
@@ -354,9 +405,9 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write) | |||
354 | host->data->bytes_xfered += n; | 405 | host->data->bytes_xfered += n; |
355 | 406 | ||
356 | if (write) { | 407 | if (write) { |
357 | __raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n); | 408 | __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); |
358 | } else { | 409 | } else { |
359 | __raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n); | 410 | __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); |
360 | } | 411 | } |
361 | } | 412 | } |
362 | 413 | ||
@@ -386,11 +437,11 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id) | |||
386 | int transfer_error; | 437 | int transfer_error; |
387 | 438 | ||
388 | if (host->cmd == NULL && host->data == NULL) { | 439 | if (host->cmd == NULL && host->data == NULL) { |
389 | status = OMAP_MMC_READ(host->base, STAT); | 440 | status = OMAP_MMC_READ(host, STAT); |
390 | dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status); | 441 | dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status); |
391 | if (status != 0) { | 442 | if (status != 0) { |
392 | OMAP_MMC_WRITE(host->base, STAT, status); | 443 | OMAP_MMC_WRITE(host, STAT, status); |
393 | OMAP_MMC_WRITE(host->base, IE, 0); | 444 | OMAP_MMC_WRITE(host, IE, 0); |
394 | } | 445 | } |
395 | return IRQ_HANDLED; | 446 | return IRQ_HANDLED; |
396 | } | 447 | } |
@@ -399,8 +450,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id) | |||
399 | end_transfer = 0; | 450 | end_transfer = 0; |
400 | transfer_error = 0; | 451 | transfer_error = 0; |
401 | 452 | ||
402 | while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) { | 453 | while ((status = OMAP_MMC_READ(host, STAT)) != 0) { |
403 | OMAP_MMC_WRITE(host->base, STAT, status); | 454 | OMAP_MMC_WRITE(host, STAT, status); |
404 | #ifdef CONFIG_MMC_DEBUG | 455 | #ifdef CONFIG_MMC_DEBUG |
405 | dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", | 456 | dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", |
406 | status, host->cmd != NULL ? host->cmd->opcode : -1); | 457 | status, host->cmd != NULL ? host->cmd->opcode : -1); |
@@ -470,8 +521,8 @@ static irqreturn_t mmc_omap_irq(int irq, void *dev_id) | |||
470 | 521 | ||
471 | if (status & OMAP_MMC_STAT_CARD_ERR) { | 522 | if (status & OMAP_MMC_STAT_CARD_ERR) { |
472 | if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) { | 523 | if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) { |
473 | u32 response = OMAP_MMC_READ(host->base, RSP6) | 524 | u32 response = OMAP_MMC_READ(host, RSP6) |
474 | | (OMAP_MMC_READ(host->base, RSP7) << 16); | 525 | | (OMAP_MMC_READ(host, RSP7) << 16); |
475 | /* STOP sometimes sets must-ignore bits */ | 526 | /* STOP sometimes sets must-ignore bits */ |
476 | if (!(response & (R1_CC_ERROR | 527 | if (!(response & (R1_CC_ERROR |
477 | | R1_ILLEGAL_COMMAND | 528 | | R1_ILLEGAL_COMMAND |
@@ -530,12 +581,6 @@ static void mmc_omap_switch_timer(unsigned long arg) | |||
530 | schedule_work(&host->switch_work); | 581 | schedule_work(&host->switch_work); |
531 | } | 582 | } |
532 | 583 | ||
533 | /* FIXME: Handle card insertion and removal properly. Maybe use a mask | ||
534 | * for MMC state? */ | ||
535 | static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask) | ||
536 | { | ||
537 | } | ||
538 | |||
539 | static void mmc_omap_switch_handler(void *data) | 584 | static void mmc_omap_switch_handler(void *data) |
540 | { | 585 | { |
541 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | 586 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; |
@@ -581,7 +626,7 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) | |||
581 | int dst_port = 0; | 626 | int dst_port = 0; |
582 | int sync_dev = 0; | 627 | int sync_dev = 0; |
583 | 628 | ||
584 | data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA; | 629 | data_addr = host->phys_base + OMAP_MMC_REG_DATA; |
585 | frame = data->blksz; | 630 | frame = data->blksz; |
586 | count = sg_dma_len(sg); | 631 | count = sg_dma_len(sg); |
587 | 632 | ||
@@ -640,10 +685,9 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) | |||
640 | } | 685 | } |
641 | 686 | ||
642 | /* Max limit for DMA frame count is 0xffff */ | 687 | /* Max limit for DMA frame count is 0xffff */ |
643 | if (unlikely(count > 0xffff)) | 688 | BUG_ON(count > 0xffff); |
644 | BUG(); | ||
645 | 689 | ||
646 | OMAP_MMC_WRITE(host->base, BUF, buf); | 690 | OMAP_MMC_WRITE(host, BUF, buf); |
647 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, | 691 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, |
648 | frame, count, OMAP_DMA_SYNC_FRAME, | 692 | frame, count, OMAP_DMA_SYNC_FRAME, |
649 | sync_dev, 0); | 693 | sync_dev, 0); |
@@ -728,11 +772,11 @@ static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_reques | |||
728 | { | 772 | { |
729 | u16 reg; | 773 | u16 reg; |
730 | 774 | ||
731 | reg = OMAP_MMC_READ(host->base, SDIO); | 775 | reg = OMAP_MMC_READ(host, SDIO); |
732 | reg &= ~(1 << 5); | 776 | reg &= ~(1 << 5); |
733 | OMAP_MMC_WRITE(host->base, SDIO, reg); | 777 | OMAP_MMC_WRITE(host, SDIO, reg); |
734 | /* Set maximum timeout */ | 778 | /* Set maximum timeout */ |
735 | OMAP_MMC_WRITE(host->base, CTO, 0xff); | 779 | OMAP_MMC_WRITE(host, CTO, 0xff); |
736 | } | 780 | } |
737 | 781 | ||
738 | static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) | 782 | static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) |
@@ -746,14 +790,14 @@ static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_reque | |||
746 | timeout = req->data->timeout_clks + req->data->timeout_ns / 500; | 790 | timeout = req->data->timeout_clks + req->data->timeout_ns / 500; |
747 | 791 | ||
748 | /* Check if we need to use timeout multiplier register */ | 792 | /* Check if we need to use timeout multiplier register */ |
749 | reg = OMAP_MMC_READ(host->base, SDIO); | 793 | reg = OMAP_MMC_READ(host, SDIO); |
750 | if (timeout > 0xffff) { | 794 | if (timeout > 0xffff) { |
751 | reg |= (1 << 5); | 795 | reg |= (1 << 5); |
752 | timeout /= 1024; | 796 | timeout /= 1024; |
753 | } else | 797 | } else |
754 | reg &= ~(1 << 5); | 798 | reg &= ~(1 << 5); |
755 | OMAP_MMC_WRITE(host->base, SDIO, reg); | 799 | OMAP_MMC_WRITE(host, SDIO, reg); |
756 | OMAP_MMC_WRITE(host->base, DTO, timeout); | 800 | OMAP_MMC_WRITE(host, DTO, timeout); |
757 | } | 801 | } |
758 | 802 | ||
759 | static void | 803 | static void |
@@ -765,19 +809,18 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |||
765 | 809 | ||
766 | host->data = data; | 810 | host->data = data; |
767 | if (data == NULL) { | 811 | if (data == NULL) { |
768 | OMAP_MMC_WRITE(host->base, BLEN, 0); | 812 | OMAP_MMC_WRITE(host, BLEN, 0); |
769 | OMAP_MMC_WRITE(host->base, NBLK, 0); | 813 | OMAP_MMC_WRITE(host, NBLK, 0); |
770 | OMAP_MMC_WRITE(host->base, BUF, 0); | 814 | OMAP_MMC_WRITE(host, BUF, 0); |
771 | host->dma_in_use = 0; | 815 | host->dma_in_use = 0; |
772 | set_cmd_timeout(host, req); | 816 | set_cmd_timeout(host, req); |
773 | return; | 817 | return; |
774 | } | 818 | } |
775 | 819 | ||
776 | |||
777 | block_size = data->blksz; | 820 | block_size = data->blksz; |
778 | 821 | ||
779 | OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1); | 822 | OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); |
780 | OMAP_MMC_WRITE(host->base, BLEN, block_size - 1); | 823 | OMAP_MMC_WRITE(host, BLEN, block_size - 1); |
781 | set_data_timeout(host, req); | 824 | set_data_timeout(host, req); |
782 | 825 | ||
783 | /* cope with calling layer confusion; it issues "single | 826 | /* cope with calling layer confusion; it issues "single |
@@ -819,7 +862,7 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |||
819 | 862 | ||
820 | /* Revert to PIO? */ | 863 | /* Revert to PIO? */ |
821 | if (!use_dma) { | 864 | if (!use_dma) { |
822 | OMAP_MMC_WRITE(host->base, BUF, 0x1f1f); | 865 | OMAP_MMC_WRITE(host, BUF, 0x1f1f); |
823 | host->total_bytes_left = data->blocks * block_size; | 866 | host->total_bytes_left = data->blocks * block_size; |
824 | host->sg_len = sg_len; | 867 | host->sg_len = sg_len; |
825 | mmc_omap_sg_to_buf(host); | 868 | mmc_omap_sg_to_buf(host); |
@@ -845,7 +888,6 @@ static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) | |||
845 | static void innovator_fpga_socket_power(int on) | 888 | static void innovator_fpga_socket_power(int on) |
846 | { | 889 | { |
847 | #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) | 890 | #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) |
848 | |||
849 | if (on) { | 891 | if (on) { |
850 | fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), | 892 | fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), |
851 | OMAP1510_FPGA_POWER); | 893 | OMAP1510_FPGA_POWER); |
@@ -871,8 +913,8 @@ static void mmc_omap_power(struct mmc_omap_host *host, int on) | |||
871 | /* GPIO 4 of TPS65010 sends SD_EN signal */ | 913 | /* GPIO 4 of TPS65010 sends SD_EN signal */ |
872 | tps65010_set_gpio_out_value(GPIO4, HIGH); | 914 | tps65010_set_gpio_out_value(GPIO4, HIGH); |
873 | else if (cpu_is_omap24xx()) { | 915 | else if (cpu_is_omap24xx()) { |
874 | u16 reg = OMAP_MMC_READ(host->base, CON); | 916 | u16 reg = OMAP_MMC_READ(host, CON); |
875 | OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11)); | 917 | OMAP_MMC_WRITE(host, CON, reg | (1 << 11)); |
876 | } else | 918 | } else |
877 | if (host->power_pin >= 0) | 919 | if (host->power_pin >= 0) |
878 | omap_set_gpio_dataout(host->power_pin, 1); | 920 | omap_set_gpio_dataout(host->power_pin, 1); |
@@ -884,8 +926,8 @@ static void mmc_omap_power(struct mmc_omap_host *host, int on) | |||
884 | else if (machine_is_omap_h3()) | 926 | else if (machine_is_omap_h3()) |
885 | tps65010_set_gpio_out_value(GPIO4, LOW); | 927 | tps65010_set_gpio_out_value(GPIO4, LOW); |
886 | else if (cpu_is_omap24xx()) { | 928 | else if (cpu_is_omap24xx()) { |
887 | u16 reg = OMAP_MMC_READ(host->base, CON); | 929 | u16 reg = OMAP_MMC_READ(host, CON); |
888 | OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11)); | 930 | OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11)); |
889 | } else | 931 | } else |
890 | if (host->power_pin >= 0) | 932 | if (host->power_pin >= 0) |
891 | omap_set_gpio_dataout(host->power_pin, 0); | 933 | omap_set_gpio_dataout(host->power_pin, 0); |
@@ -927,7 +969,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
927 | case MMC_POWER_UP: | 969 | case MMC_POWER_UP: |
928 | case MMC_POWER_ON: | 970 | case MMC_POWER_ON: |
929 | mmc_omap_power(host, 1); | 971 | mmc_omap_power(host, 1); |
930 | dsor |= 1<<11; | 972 | dsor |= 1 << 11; |
931 | break; | 973 | break; |
932 | } | 974 | } |
933 | 975 | ||
@@ -941,14 +983,14 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
941 | * which results in the while loop below getting stuck. | 983 | * which results in the while loop below getting stuck. |
942 | * Writing to the CON register twice seems to do the trick. */ | 984 | * Writing to the CON register twice seems to do the trick. */ |
943 | for (i = 0; i < 2; i++) | 985 | for (i = 0; i < 2; i++) |
944 | OMAP_MMC_WRITE(host->base, CON, dsor); | 986 | OMAP_MMC_WRITE(host, CON, dsor); |
945 | if (ios->power_mode == MMC_POWER_UP) { | 987 | if (ios->power_mode == MMC_POWER_UP) { |
946 | /* Send clock cycles, poll completion */ | 988 | /* Send clock cycles, poll completion */ |
947 | OMAP_MMC_WRITE(host->base, IE, 0); | 989 | OMAP_MMC_WRITE(host, IE, 0); |
948 | OMAP_MMC_WRITE(host->base, STAT, 0xffff); | 990 | OMAP_MMC_WRITE(host, STAT, 0xffff); |
949 | OMAP_MMC_WRITE(host->base, CMD, 1<<7); | 991 | OMAP_MMC_WRITE(host, CMD, 1 << 7); |
950 | while (0 == (OMAP_MMC_READ(host->base, STAT) & 1)); | 992 | while ((OMAP_MMC_READ(host, STAT) & 1) == 0); |
951 | OMAP_MMC_WRITE(host->base, STAT, 1); | 993 | OMAP_MMC_WRITE(host, STAT, 1); |
952 | } | 994 | } |
953 | clk_disable(host->fclk); | 995 | clk_disable(host->fclk); |
954 | } | 996 | } |
@@ -960,7 +1002,7 @@ static int mmc_omap_get_ro(struct mmc_host *mmc) | |||
960 | return host->wp_pin && omap_get_gpio_datain(host->wp_pin); | 1002 | return host->wp_pin && omap_get_gpio_datain(host->wp_pin); |
961 | } | 1003 | } |
962 | 1004 | ||
963 | static struct mmc_host_ops mmc_omap_ops = { | 1005 | static const struct mmc_host_ops mmc_omap_ops = { |
964 | .request = mmc_omap_request, | 1006 | .request = mmc_omap_request, |
965 | .set_ios = mmc_omap_set_ios, | 1007 | .set_ios = mmc_omap_set_ios, |
966 | .get_ro = mmc_omap_get_ro, | 1008 | .get_ro = mmc_omap_get_ro, |
@@ -971,25 +1013,29 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
971 | struct omap_mmc_conf *minfo = pdev->dev.platform_data; | 1013 | struct omap_mmc_conf *minfo = pdev->dev.platform_data; |
972 | struct mmc_host *mmc; | 1014 | struct mmc_host *mmc; |
973 | struct mmc_omap_host *host = NULL; | 1015 | struct mmc_omap_host *host = NULL; |
974 | struct resource *r; | 1016 | struct resource *res; |
975 | int ret = 0; | 1017 | int ret = 0; |
976 | int irq; | 1018 | int irq; |
977 | 1019 | ||
978 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1020 | if (minfo == NULL) { |
1021 | dev_err(&pdev->dev, "platform data missing\n"); | ||
1022 | return -ENXIO; | ||
1023 | } | ||
1024 | |||
1025 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
979 | irq = platform_get_irq(pdev, 0); | 1026 | irq = platform_get_irq(pdev, 0); |
980 | if (!r || irq < 0) | 1027 | if (res == NULL || irq < 0) |
981 | return -ENXIO; | 1028 | return -ENXIO; |
982 | 1029 | ||
983 | r = request_mem_region(pdev->resource[0].start, | 1030 | res = request_mem_region(res->start, res->end - res->start + 1, |
984 | pdev->resource[0].end - pdev->resource[0].start + 1, | 1031 | pdev->name); |
985 | pdev->name); | 1032 | if (res == NULL) |
986 | if (!r) | ||
987 | return -EBUSY; | 1033 | return -EBUSY; |
988 | 1034 | ||
989 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); | 1035 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); |
990 | if (!mmc) { | 1036 | if (mmc == NULL) { |
991 | ret = -ENOMEM; | 1037 | ret = -ENOMEM; |
992 | goto out; | 1038 | goto err_free_mem_region; |
993 | } | 1039 | } |
994 | 1040 | ||
995 | host = mmc_priv(mmc); | 1041 | host = mmc_priv(mmc); |
@@ -1001,13 +1047,13 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
1001 | host->dma_timer.data = (unsigned long) host; | 1047 | host->dma_timer.data = (unsigned long) host; |
1002 | 1048 | ||
1003 | host->id = pdev->id; | 1049 | host->id = pdev->id; |
1004 | host->res = r; | 1050 | host->mem_res = res; |
1005 | host->irq = irq; | 1051 | host->irq = irq; |
1006 | 1052 | ||
1007 | if (cpu_is_omap24xx()) { | 1053 | if (cpu_is_omap24xx()) { |
1008 | host->iclk = clk_get(&pdev->dev, "mmc_ick"); | 1054 | host->iclk = clk_get(&pdev->dev, "mmc_ick"); |
1009 | if (IS_ERR(host->iclk)) | 1055 | if (IS_ERR(host->iclk)) |
1010 | goto out; | 1056 | goto err_free_mmc_host; |
1011 | clk_enable(host->iclk); | 1057 | clk_enable(host->iclk); |
1012 | } | 1058 | } |
1013 | 1059 | ||
@@ -1018,7 +1064,7 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
1018 | 1064 | ||
1019 | if (IS_ERR(host->fclk)) { | 1065 | if (IS_ERR(host->fclk)) { |
1020 | ret = PTR_ERR(host->fclk); | 1066 | ret = PTR_ERR(host->fclk); |
1021 | goto out; | 1067 | goto err_free_iclk; |
1022 | } | 1068 | } |
1023 | 1069 | ||
1024 | /* REVISIT: | 1070 | /* REVISIT: |
@@ -1031,14 +1077,15 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
1031 | host->use_dma = 1; | 1077 | host->use_dma = 1; |
1032 | host->dma_ch = -1; | 1078 | host->dma_ch = -1; |
1033 | 1079 | ||
1034 | host->irq = pdev->resource[1].start; | 1080 | host->irq = irq; |
1035 | host->base = (void __iomem*)IO_ADDRESS(r->start); | 1081 | host->phys_base = host->mem_res->start; |
1082 | host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base); | ||
1036 | 1083 | ||
1037 | mmc->ops = &mmc_omap_ops; | 1084 | mmc->ops = &mmc_omap_ops; |
1038 | mmc->f_min = 400000; | 1085 | mmc->f_min = 400000; |
1039 | mmc->f_max = 24000000; | 1086 | mmc->f_max = 24000000; |
1040 | mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; | 1087 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
1041 | mmc->caps = MMC_CAP_BYTEBLOCK; | 1088 | mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; |
1042 | 1089 | ||
1043 | if (minfo->wire4) | 1090 | if (minfo->wire4) |
1044 | mmc->caps |= MMC_CAP_4_BIT_DATA; | 1091 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
@@ -1056,20 +1103,18 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
1056 | if ((ret = omap_request_gpio(host->power_pin)) != 0) { | 1103 | if ((ret = omap_request_gpio(host->power_pin)) != 0) { |
1057 | dev_err(mmc_dev(host->mmc), | 1104 | dev_err(mmc_dev(host->mmc), |
1058 | "Unable to get GPIO pin for MMC power\n"); | 1105 | "Unable to get GPIO pin for MMC power\n"); |
1059 | goto out; | 1106 | goto err_free_fclk; |
1060 | } | 1107 | } |
1061 | omap_set_gpio_direction(host->power_pin, 0); | 1108 | omap_set_gpio_direction(host->power_pin, 0); |
1062 | } | 1109 | } |
1063 | 1110 | ||
1064 | ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); | 1111 | ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); |
1065 | if (ret) | 1112 | if (ret) |
1066 | goto out; | 1113 | goto err_free_power_gpio; |
1067 | 1114 | ||
1068 | host->dev = &pdev->dev; | 1115 | host->dev = &pdev->dev; |
1069 | platform_set_drvdata(pdev, host); | 1116 | platform_set_drvdata(pdev, host); |
1070 | 1117 | ||
1071 | mmc_add_host(mmc); | ||
1072 | |||
1073 | if (host->switch_pin >= 0) { | 1118 | if (host->switch_pin >= 0) { |
1074 | INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host); | 1119 | INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host); |
1075 | init_timer(&host->switch_timer); | 1120 | init_timer(&host->switch_timer); |
@@ -1107,10 +1152,11 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
1107 | schedule_work(&host->switch_work); | 1152 | schedule_work(&host->switch_work); |
1108 | } | 1153 | } |
1109 | 1154 | ||
1110 | no_switch: | 1155 | mmc_add_host(mmc); |
1156 | |||
1111 | return 0; | 1157 | return 0; |
1112 | 1158 | ||
1113 | out: | 1159 | no_switch: |
1114 | /* FIXME: Free other resources too. */ | 1160 | /* FIXME: Free other resources too. */ |
1115 | if (host) { | 1161 | if (host) { |
1116 | if (host->iclk && !IS_ERR(host->iclk)) | 1162 | if (host->iclk && !IS_ERR(host->iclk)) |
@@ -1119,6 +1165,20 @@ out: | |||
1119 | clk_put(host->fclk); | 1165 | clk_put(host->fclk); |
1120 | mmc_free_host(host->mmc); | 1166 | mmc_free_host(host->mmc); |
1121 | } | 1167 | } |
1168 | err_free_power_gpio: | ||
1169 | if (host->power_pin >= 0) | ||
1170 | omap_free_gpio(host->power_pin); | ||
1171 | err_free_fclk: | ||
1172 | clk_put(host->fclk); | ||
1173 | err_free_iclk: | ||
1174 | if (host->iclk != NULL) { | ||
1175 | clk_disable(host->iclk); | ||
1176 | clk_put(host->iclk); | ||
1177 | } | ||
1178 | err_free_mmc_host: | ||
1179 | mmc_free_host(host->mmc); | ||
1180 | err_free_mem_region: | ||
1181 | release_mem_region(res->start, res->end - res->start + 1); | ||
1122 | return ret; | 1182 | return ret; |
1123 | } | 1183 | } |
1124 | 1184 | ||
@@ -1128,30 +1188,31 @@ static int mmc_omap_remove(struct platform_device *pdev) | |||
1128 | 1188 | ||
1129 | platform_set_drvdata(pdev, NULL); | 1189 | platform_set_drvdata(pdev, NULL); |
1130 | 1190 | ||
1131 | if (host) { | 1191 | BUG_ON(host == NULL); |
1132 | mmc_remove_host(host->mmc); | 1192 | |
1133 | free_irq(host->irq, host); | 1193 | mmc_remove_host(host->mmc); |
1134 | 1194 | free_irq(host->irq, host); | |
1135 | if (host->power_pin >= 0) | 1195 | |
1136 | omap_free_gpio(host->power_pin); | 1196 | if (host->power_pin >= 0) |
1137 | if (host->switch_pin >= 0) { | 1197 | omap_free_gpio(host->power_pin); |
1138 | device_remove_file(&pdev->dev, &dev_attr_enable_poll); | 1198 | if (host->switch_pin >= 0) { |
1139 | device_remove_file(&pdev->dev, &dev_attr_cover_switch); | 1199 | device_remove_file(&pdev->dev, &dev_attr_enable_poll); |
1140 | free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); | 1200 | device_remove_file(&pdev->dev, &dev_attr_cover_switch); |
1141 | omap_free_gpio(host->switch_pin); | 1201 | free_irq(OMAP_GPIO_IRQ(host->switch_pin), host); |
1142 | host->switch_pin = -1; | 1202 | omap_free_gpio(host->switch_pin); |
1143 | del_timer_sync(&host->switch_timer); | 1203 | host->switch_pin = -1; |
1144 | flush_scheduled_work(); | 1204 | del_timer_sync(&host->switch_timer); |
1145 | } | 1205 | flush_scheduled_work(); |
1146 | if (host->iclk && !IS_ERR(host->iclk)) | ||
1147 | clk_put(host->iclk); | ||
1148 | if (host->fclk && !IS_ERR(host->fclk)) | ||
1149 | clk_put(host->fclk); | ||
1150 | mmc_free_host(host->mmc); | ||
1151 | } | 1206 | } |
1207 | if (host->iclk && !IS_ERR(host->iclk)) | ||
1208 | clk_put(host->iclk); | ||
1209 | if (host->fclk && !IS_ERR(host->fclk)) | ||
1210 | clk_put(host->fclk); | ||
1152 | 1211 | ||
1153 | release_mem_region(pdev->resource[0].start, | 1212 | release_mem_region(pdev->resource[0].start, |
1154 | pdev->resource[0].end - pdev->resource[0].start + 1); | 1213 | pdev->resource[0].end - pdev->resource[0].start + 1); |
1214 | |||
1215 | mmc_free_host(host->mmc); | ||
1155 | 1216 | ||
1156 | return 0; | 1217 | return 0; |
1157 | } | 1218 | } |