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-rw-r--r--drivers/mmc/host/Kconfig20
-rw-r--r--drivers/mmc/host/Makefile2
-rw-r--r--drivers/mmc/host/atmel-mci.c5
-rw-r--r--drivers/mmc/host/mmci.c37
-rw-r--r--drivers/mmc/host/mmci.h28
-rw-r--r--drivers/mmc/host/mxcmmc.c880
-rw-r--r--drivers/mmc/host/omap_hsmmc.c1280
-rw-r--r--drivers/mmc/host/pxamci.c25
-rw-r--r--drivers/mmc/host/ricoh_mmc.c8
-rw-r--r--drivers/mmc/host/s3cmci.c4
-rw-r--r--drivers/mmc/host/sdhci-pci.c4
-rw-r--r--drivers/mmc/host/sdhci.c12
-rw-r--r--drivers/mmc/host/sdhci.h5
13 files changed, 2284 insertions, 26 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index dfa585f7feaf..99d4b28d52ed 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -76,6 +76,16 @@ config MMC_OMAP
76 76
77 If unsure, say N. 77 If unsure, say N.
78 78
79config MMC_OMAP_HS
80 tristate "TI OMAP High Speed Multimedia Card Interface support"
81 depends on ARCH_OMAP2430 || ARCH_OMAP3
82 help
83 This selects the TI OMAP High Speed Multimedia card Interface.
84 If you have an OMAP2430 or OMAP3 board with a Multimedia Card slot,
85 say Y or M here.
86
87 If unsure, say N.
88
79config MMC_WBSD 89config MMC_WBSD
80 tristate "Winbond W83L51xD SD/MMC Card Interface support" 90 tristate "Winbond W83L51xD SD/MMC Card Interface support"
81 depends on ISA_DMA_API 91 depends on ISA_DMA_API
@@ -135,6 +145,16 @@ config MMC_IMX
135 145
136 If unsure, say N. 146 If unsure, say N.
137 147
148config MMC_MXC
149 tristate "Freescale i.MX2/3 Multimedia Card Interface support"
150 depends on ARCH_MXC
151 help
152 This selects the Freescale i.MX2/3 Multimedia card Interface.
153 If you have a i.MX platform with a Multimedia Card slot,
154 say Y or M here.
155
156 If unsure, say N.
157
138config MMC_TIFM_SD 158config MMC_TIFM_SD
139 tristate "TI Flash Media MMC/SD Interface support (EXPERIMENTAL)" 159 tristate "TI Flash Media MMC/SD Interface support (EXPERIMENTAL)"
140 depends on EXPERIMENTAL && PCI 160 depends on EXPERIMENTAL && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index f4853288bbb1..dedec55861d9 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -9,12 +9,14 @@ endif
9obj-$(CONFIG_MMC_ARMMMCI) += mmci.o 9obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
10obj-$(CONFIG_MMC_PXA) += pxamci.o 10obj-$(CONFIG_MMC_PXA) += pxamci.o
11obj-$(CONFIG_MMC_IMX) += imxmmc.o 11obj-$(CONFIG_MMC_IMX) += imxmmc.o
12obj-$(CONFIG_MMC_MXC) += mxcmmc.o
12obj-$(CONFIG_MMC_SDHCI) += sdhci.o 13obj-$(CONFIG_MMC_SDHCI) += sdhci.o
13obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o 14obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
14obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o 15obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o
15obj-$(CONFIG_MMC_WBSD) += wbsd.o 16obj-$(CONFIG_MMC_WBSD) += wbsd.o
16obj-$(CONFIG_MMC_AU1X) += au1xmmc.o 17obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
17obj-$(CONFIG_MMC_OMAP) += omap.o 18obj-$(CONFIG_MMC_OMAP) += omap.o
19obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
18obj-$(CONFIG_MMC_AT91) += at91_mci.o 20obj-$(CONFIG_MMC_AT91) += at91_mci.o
19obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o 21obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
20obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o 22obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 76bfe16c09b1..2b1196e6142c 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -1548,9 +1548,10 @@ static bool filter(struct dma_chan *chan, void *slave)
1548{ 1548{
1549 struct dw_dma_slave *dws = slave; 1549 struct dw_dma_slave *dws = slave;
1550 1550
1551 if (dws->dma_dev == chan->device->dev) 1551 if (dws->dma_dev == chan->device->dev) {
1552 chan->private = dws;
1552 return true; 1553 return true;
1553 else 1554 } else
1554 return false; 1555 return false;
1555} 1556}
1556#endif 1557#endif
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 1bcbdd6763ac..2909bbc8ad00 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -430,6 +430,8 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
430 clk = 255; 430 clk = 255;
431 host->cclk = host->mclk / (2 * (clk + 1)); 431 host->cclk = host->mclk / (2 * (clk + 1));
432 } 432 }
433 if (host->hw_designer == 0x80)
434 clk |= MCI_FCEN; /* Bug fix in ST IP block */
433 clk |= MCI_CLK_ENABLE; 435 clk |= MCI_CLK_ENABLE;
434 } 436 }
435 437
@@ -440,15 +442,27 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
440 case MMC_POWER_OFF: 442 case MMC_POWER_OFF:
441 break; 443 break;
442 case MMC_POWER_UP: 444 case MMC_POWER_UP:
443 pwr |= MCI_PWR_UP; 445 /* The ST version does not have this, fall through to POWER_ON */
444 break; 446 if (host->hw_designer != 0x80) {
447 pwr |= MCI_PWR_UP;
448 break;
449 }
445 case MMC_POWER_ON: 450 case MMC_POWER_ON:
446 pwr |= MCI_PWR_ON; 451 pwr |= MCI_PWR_ON;
447 break; 452 break;
448 } 453 }
449 454
450 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 455 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
451 pwr |= MCI_ROD; 456 if (host->hw_designer != 0x80)
457 pwr |= MCI_ROD;
458 else {
459 /*
460 * The ST Micro variant use the ROD bit for something
461 * else and only has OD (Open Drain).
462 */
463 pwr |= MCI_OD;
464 }
465 }
452 466
453 writel(clk, host->base + MMCICLOCK); 467 writel(clk, host->base + MMCICLOCK);
454 468
@@ -500,6 +514,12 @@ static int mmci_probe(struct amba_device *dev, void *id)
500 } 514 }
501 515
502 host = mmc_priv(mmc); 516 host = mmc_priv(mmc);
517 /* Bits 12 thru 19 is the designer */
518 host->hw_designer = (dev->periphid >> 12) & 0xff;
519 /* Bits 20 thru 23 is the revison */
520 host->hw_revision = (dev->periphid >> 20) & 0xf;
521 DBG(host, "designer ID = 0x%02x\n", host->hw_designer);
522 DBG(host, "revision = 0x%01x\n", host->hw_revision);
503 host->clk = clk_get(&dev->dev, NULL); 523 host->clk = clk_get(&dev->dev, NULL);
504 if (IS_ERR(host->clk)) { 524 if (IS_ERR(host->clk)) {
505 ret = PTR_ERR(host->clk); 525 ret = PTR_ERR(host->clk);
@@ -693,6 +713,15 @@ static struct amba_id mmci_ids[] = {
693 .id = 0x00041181, 713 .id = 0x00041181,
694 .mask = 0x000fffff, 714 .mask = 0x000fffff,
695 }, 715 },
716 /* ST Micro variants */
717 {
718 .id = 0x00180180,
719 .mask = 0x00ffffff,
720 },
721 {
722 .id = 0x00280180,
723 .mask = 0x00ffffff,
724 },
696 { 0, 0 }, 725 { 0, 0 },
697}; 726};
698 727
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 0f39c490f022..0441bac1c0ec 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -11,13 +11,23 @@
11#define MCI_PWR_OFF 0x00 11#define MCI_PWR_OFF 0x00
12#define MCI_PWR_UP 0x02 12#define MCI_PWR_UP 0x02
13#define MCI_PWR_ON 0x03 13#define MCI_PWR_ON 0x03
14#define MCI_DATA2DIREN (1 << 2)
15#define MCI_CMDDIREN (1 << 3)
16#define MCI_DATA0DIREN (1 << 4)
17#define MCI_DATA31DIREN (1 << 5)
14#define MCI_OD (1 << 6) 18#define MCI_OD (1 << 6)
15#define MCI_ROD (1 << 7) 19#define MCI_ROD (1 << 7)
20/* The ST Micro version does not have ROD */
21#define MCI_FBCLKEN (1 << 7)
22#define MCI_DATA74DIREN (1 << 8)
16 23
17#define MMCICLOCK 0x004 24#define MMCICLOCK 0x004
18#define MCI_CLK_ENABLE (1 << 8) 25#define MCI_CLK_ENABLE (1 << 8)
19#define MCI_CLK_PWRSAVE (1 << 9) 26#define MCI_CLK_PWRSAVE (1 << 9)
20#define MCI_CLK_BYPASS (1 << 10) 27#define MCI_CLK_BYPASS (1 << 10)
28#define MCI_WIDE_BUS (1 << 11)
29/* HW flow control on the ST Micro version */
30#define MCI_FCEN (1 << 13)
21 31
22#define MMCIARGUMENT 0x008 32#define MMCIARGUMENT 0x008
23#define MMCICOMMAND 0x00c 33#define MMCICOMMAND 0x00c
@@ -26,6 +36,10 @@
26#define MCI_CPSM_INTERRUPT (1 << 8) 36#define MCI_CPSM_INTERRUPT (1 << 8)
27#define MCI_CPSM_PENDING (1 << 9) 37#define MCI_CPSM_PENDING (1 << 9)
28#define MCI_CPSM_ENABLE (1 << 10) 38#define MCI_CPSM_ENABLE (1 << 10)
39#define MCI_SDIO_SUSP (1 << 11)
40#define MCI_ENCMD_COMPL (1 << 12)
41#define MCI_NIEN (1 << 13)
42#define MCI_CE_ATACMD (1 << 14)
29 43
30#define MMCIRESPCMD 0x010 44#define MMCIRESPCMD 0x010
31#define MMCIRESPONSE0 0x014 45#define MMCIRESPONSE0 0x014
@@ -39,6 +53,11 @@
39#define MCI_DPSM_DIRECTION (1 << 1) 53#define MCI_DPSM_DIRECTION (1 << 1)
40#define MCI_DPSM_MODE (1 << 2) 54#define MCI_DPSM_MODE (1 << 2)
41#define MCI_DPSM_DMAENABLE (1 << 3) 55#define MCI_DPSM_DMAENABLE (1 << 3)
56#define MCI_DPSM_BLOCKSIZE (1 << 4)
57#define MCI_DPSM_RWSTART (1 << 8)
58#define MCI_DPSM_RWSTOP (1 << 9)
59#define MCI_DPSM_RWMOD (1 << 10)
60#define MCI_DPSM_SDIOEN (1 << 11)
42 61
43#define MMCIDATACNT 0x030 62#define MMCIDATACNT 0x030
44#define MMCISTATUS 0x034 63#define MMCISTATUS 0x034
@@ -63,6 +82,8 @@
63#define MCI_RXFIFOEMPTY (1 << 19) 82#define MCI_RXFIFOEMPTY (1 << 19)
64#define MCI_TXDATAAVLBL (1 << 20) 83#define MCI_TXDATAAVLBL (1 << 20)
65#define MCI_RXDATAAVLBL (1 << 21) 84#define MCI_RXDATAAVLBL (1 << 21)
85#define MCI_SDIOIT (1 << 22)
86#define MCI_CEATAEND (1 << 23)
66 87
67#define MMCICLEAR 0x038 88#define MMCICLEAR 0x038
68#define MCI_CMDCRCFAILCLR (1 << 0) 89#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -75,6 +96,8 @@
75#define MCI_CMDSENTCLR (1 << 7) 96#define MCI_CMDSENTCLR (1 << 7)
76#define MCI_DATAENDCLR (1 << 8) 97#define MCI_DATAENDCLR (1 << 8)
77#define MCI_DATABLOCKENDCLR (1 << 10) 98#define MCI_DATABLOCKENDCLR (1 << 10)
99#define MCI_SDIOITC (1 << 22)
100#define MCI_CEATAENDC (1 << 23)
78 101
79#define MMCIMASK0 0x03c 102#define MMCIMASK0 0x03c
80#define MCI_CMDCRCFAILMASK (1 << 0) 103#define MCI_CMDCRCFAILMASK (1 << 0)
@@ -98,6 +121,8 @@
98#define MCI_RXFIFOEMPTYMASK (1 << 19) 121#define MCI_RXFIFOEMPTYMASK (1 << 19)
99#define MCI_TXDATAAVLBLMASK (1 << 20) 122#define MCI_TXDATAAVLBLMASK (1 << 20)
100#define MCI_RXDATAAVLBLMASK (1 << 21) 123#define MCI_RXDATAAVLBLMASK (1 << 21)
124#define MCI_SDIOITMASK (1 << 22)
125#define MCI_CEATAENDMASK (1 << 23)
101 126
102#define MMCIMASK1 0x040 127#define MMCIMASK1 0x040
103#define MMCIFIFOCNT 0x048 128#define MMCIFIFOCNT 0x048
@@ -136,6 +161,9 @@ struct mmci_host {
136 u32 pwr; 161 u32 pwr;
137 struct mmc_platform_data *plat; 162 struct mmc_platform_data *plat;
138 163
164 u8 hw_designer;
165 u8 hw_revision:4;
166
139 struct timer_list timer; 167 struct timer_list timer;
140 unsigned int oldstat; 168 unsigned int oldstat;
141 169
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
new file mode 100644
index 000000000000..dda0be4e25dc
--- /dev/null
+++ b/drivers/mmc/host/mxcmmc.c
@@ -0,0 +1,880 @@
1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the seperate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
34
35#include <asm/dma.h>
36#include <asm/irq.h>
37#include <asm/sizes.h>
38#include <mach/mmc.h>
39
40#ifdef CONFIG_ARCH_MX2
41#include <mach/dma-mx1-mx2.h>
42#define HAS_DMA
43#endif
44
45#define DRIVER_NAME "imx-mmc"
46
47#define MMC_REG_STR_STP_CLK 0x00
48#define MMC_REG_STATUS 0x04
49#define MMC_REG_CLK_RATE 0x08
50#define MMC_REG_CMD_DAT_CONT 0x0C
51#define MMC_REG_RES_TO 0x10
52#define MMC_REG_READ_TO 0x14
53#define MMC_REG_BLK_LEN 0x18
54#define MMC_REG_NOB 0x1C
55#define MMC_REG_REV_NO 0x20
56#define MMC_REG_INT_CNTR 0x24
57#define MMC_REG_CMD 0x28
58#define MMC_REG_ARG 0x2C
59#define MMC_REG_RES_FIFO 0x34
60#define MMC_REG_BUFFER_ACCESS 0x38
61
62#define STR_STP_CLK_RESET (1 << 3)
63#define STR_STP_CLK_START_CLK (1 << 1)
64#define STR_STP_CLK_STOP_CLK (1 << 0)
65
66#define STATUS_CARD_INSERTION (1 << 31)
67#define STATUS_CARD_REMOVAL (1 << 30)
68#define STATUS_YBUF_EMPTY (1 << 29)
69#define STATUS_XBUF_EMPTY (1 << 28)
70#define STATUS_YBUF_FULL (1 << 27)
71#define STATUS_XBUF_FULL (1 << 26)
72#define STATUS_BUF_UND_RUN (1 << 25)
73#define STATUS_BUF_OVFL (1 << 24)
74#define STATUS_SDIO_INT_ACTIVE (1 << 14)
75#define STATUS_END_CMD_RESP (1 << 13)
76#define STATUS_WRITE_OP_DONE (1 << 12)
77#define STATUS_DATA_TRANS_DONE (1 << 11)
78#define STATUS_READ_OP_DONE (1 << 11)
79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81#define STATUS_BUF_READ_RDY (1 << 7)
82#define STATUS_BUF_WRITE_RDY (1 << 6)
83#define STATUS_RESP_CRC_ERR (1 << 5)
84#define STATUS_CRC_READ_ERR (1 << 3)
85#define STATUS_CRC_WRITE_ERR (1 << 2)
86#define STATUS_TIME_OUT_RESP (1 << 1)
87#define STATUS_TIME_OUT_READ (1 << 0)
88#define STATUS_ERR_MASK 0x2f
89
90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92#define CMD_DAT_CONT_START_READWAIT (1 << 10)
93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94#define CMD_DAT_CONT_INIT (1 << 7)
95#define CMD_DAT_CONT_WRITE (1 << 4)
96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101#define INT_SDIO_INT_WKP_EN (1 << 18)
102#define INT_CARD_INSERTION_WKP_EN (1 << 17)
103#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104#define INT_CARD_INSERTION_EN (1 << 15)
105#define INT_CARD_REMOVAL_EN (1 << 14)
106#define INT_SDIO_IRQ_EN (1 << 13)
107#define INT_DAT0_EN (1 << 12)
108#define INT_BUF_READ_EN (1 << 4)
109#define INT_BUF_WRITE_EN (1 << 3)
110#define INT_END_CMD_RES_EN (1 << 2)
111#define INT_WRITE_OP_DONE_EN (1 << 1)
112#define INT_READ_OP_EN (1 << 0)
113
114struct mxcmci_host {
115 struct mmc_host *mmc;
116 struct resource *res;
117 void __iomem *base;
118 int irq;
119 int detect_irq;
120 int dma;
121 int do_dma;
122 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata;
124
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127 struct mmc_data *data;
128
129 unsigned int dma_nents;
130 unsigned int datasize;
131 unsigned int dma_dir;
132
133 u16 rev_no;
134 unsigned int cmdat;
135
136 struct clk *clk;
137
138 int clock;
139
140 struct work_struct datawork;
141};
142
143static inline int mxcmci_use_dma(struct mxcmci_host *host)
144{
145 return host->do_dma;
146}
147
148static void mxcmci_softreset(struct mxcmci_host *host)
149{
150 int i;
151
152 /* reset sequence */
153 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
154 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
155 host->base + MMC_REG_STR_STP_CLK);
156
157 for (i = 0; i < 8; i++)
158 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
159
160 writew(0xff, host->base + MMC_REG_RES_TO);
161}
162
163static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
164{
165 unsigned int nob = data->blocks;
166 unsigned int blksz = data->blksz;
167 unsigned int datasize = nob * blksz;
168#ifdef HAS_DMA
169 struct scatterlist *sg;
170 int i;
171#endif
172 if (data->flags & MMC_DATA_STREAM)
173 nob = 0xffff;
174
175 host->data = data;
176 data->bytes_xfered = 0;
177
178 writew(nob, host->base + MMC_REG_NOB);
179 writew(blksz, host->base + MMC_REG_BLK_LEN);
180 host->datasize = datasize;
181
182#ifdef HAS_DMA
183 for_each_sg(data->sg, sg, data->sg_len, i) {
184 if (sg->offset & 3 || sg->length & 3) {
185 host->do_dma = 0;
186 return;
187 }
188 }
189
190 if (data->flags & MMC_DATA_READ) {
191 host->dma_dir = DMA_FROM_DEVICE;
192 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
193 data->sg_len, host->dma_dir);
194
195 imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize,
196 host->res->start + MMC_REG_BUFFER_ACCESS,
197 DMA_MODE_READ);
198 } else {
199 host->dma_dir = DMA_TO_DEVICE;
200 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
201 data->sg_len, host->dma_dir);
202
203 imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, datasize,
204 host->res->start + MMC_REG_BUFFER_ACCESS,
205 DMA_MODE_WRITE);
206 }
207
208 wmb();
209
210 imx_dma_enable(host->dma);
211#endif /* HAS_DMA */
212}
213
214static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
215 unsigned int cmdat)
216{
217 WARN_ON(host->cmd != NULL);
218 host->cmd = cmd;
219
220 switch (mmc_resp_type(cmd)) {
221 case MMC_RSP_R1: /* short CRC, OPCODE */
222 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
223 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
224 break;
225 case MMC_RSP_R2: /* long 136 bit + CRC */
226 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
227 break;
228 case MMC_RSP_R3: /* short */
229 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
230 break;
231 case MMC_RSP_NONE:
232 break;
233 default:
234 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
235 mmc_resp_type(cmd));
236 cmd->error = -EINVAL;
237 return -EINVAL;
238 }
239
240 if (mxcmci_use_dma(host))
241 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
242 INT_END_CMD_RES_EN,
243 host->base + MMC_REG_INT_CNTR);
244 else
245 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
246
247 writew(cmd->opcode, host->base + MMC_REG_CMD);
248 writel(cmd->arg, host->base + MMC_REG_ARG);
249 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
250
251 return 0;
252}
253
254static void mxcmci_finish_request(struct mxcmci_host *host,
255 struct mmc_request *req)
256{
257 writel(0, host->base + MMC_REG_INT_CNTR);
258
259 host->req = NULL;
260 host->cmd = NULL;
261 host->data = NULL;
262
263 mmc_request_done(host->mmc, req);
264}
265
266static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
267{
268 struct mmc_data *data = host->data;
269 int data_error;
270
271#ifdef HAS_DMA
272 if (mxcmci_use_dma(host)) {
273 imx_dma_disable(host->dma);
274 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
275 host->dma_dir);
276 }
277#endif
278
279 if (stat & STATUS_ERR_MASK) {
280 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
281 stat);
282 if (stat & STATUS_CRC_READ_ERR) {
283 data->error = -EILSEQ;
284 } else if (stat & STATUS_CRC_WRITE_ERR) {
285 u32 err_code = (stat >> 9) & 0x3;
286 if (err_code == 2) /* No CRC response */
287 data->error = -ETIMEDOUT;
288 else
289 data->error = -EILSEQ;
290 } else if (stat & STATUS_TIME_OUT_READ) {
291 data->error = -ETIMEDOUT;
292 } else {
293 data->error = -EIO;
294 }
295 } else {
296 data->bytes_xfered = host->datasize;
297 }
298
299 data_error = data->error;
300
301 host->data = NULL;
302
303 return data_error;
304}
305
306static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
307{
308 struct mmc_command *cmd = host->cmd;
309 int i;
310 u32 a, b, c;
311
312 if (!cmd)
313 return;
314
315 if (stat & STATUS_TIME_OUT_RESP) {
316 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
317 cmd->error = -ETIMEDOUT;
318 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
319 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
320 cmd->error = -EILSEQ;
321 }
322
323 if (cmd->flags & MMC_RSP_PRESENT) {
324 if (cmd->flags & MMC_RSP_136) {
325 for (i = 0; i < 4; i++) {
326 a = readw(host->base + MMC_REG_RES_FIFO);
327 b = readw(host->base + MMC_REG_RES_FIFO);
328 cmd->resp[i] = a << 16 | b;
329 }
330 } else {
331 a = readw(host->base + MMC_REG_RES_FIFO);
332 b = readw(host->base + MMC_REG_RES_FIFO);
333 c = readw(host->base + MMC_REG_RES_FIFO);
334 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
335 }
336 }
337}
338
339static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
340{
341 u32 stat;
342 unsigned long timeout = jiffies + HZ;
343
344 do {
345 stat = readl(host->base + MMC_REG_STATUS);
346 if (stat & STATUS_ERR_MASK)
347 return stat;
348 if (time_after(jiffies, timeout))
349 return STATUS_TIME_OUT_READ;
350 if (stat & mask)
351 return 0;
352 cpu_relax();
353 } while (1);
354}
355
356static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
357{
358 unsigned int stat;
359 u32 *buf = _buf;
360
361 while (bytes > 3) {
362 stat = mxcmci_poll_status(host,
363 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
364 if (stat)
365 return stat;
366 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
367 bytes -= 4;
368 }
369
370 if (bytes) {
371 u8 *b = (u8 *)buf;
372 u32 tmp;
373
374 stat = mxcmci_poll_status(host,
375 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
376 if (stat)
377 return stat;
378 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
379 memcpy(b, &tmp, bytes);
380 }
381
382 return 0;
383}
384
385static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
386{
387 unsigned int stat;
388 u32 *buf = _buf;
389
390 while (bytes > 3) {
391 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
392 if (stat)
393 return stat;
394 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
395 bytes -= 4;
396 }
397
398 if (bytes) {
399 u8 *b = (u8 *)buf;
400 u32 tmp;
401
402 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
403 if (stat)
404 return stat;
405
406 memcpy(&tmp, b, bytes);
407 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
408 }
409
410 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
411 if (stat)
412 return stat;
413
414 return 0;
415}
416
417static int mxcmci_transfer_data(struct mxcmci_host *host)
418{
419 struct mmc_data *data = host->req->data;
420 struct scatterlist *sg;
421 int stat, i;
422
423 host->datasize = 0;
424
425 host->data = data;
426 host->datasize = 0;
427
428 if (data->flags & MMC_DATA_READ) {
429 for_each_sg(data->sg, sg, data->sg_len, i) {
430 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
431 if (stat)
432 return stat;
433 host->datasize += sg->length;
434 }
435 } else {
436 for_each_sg(data->sg, sg, data->sg_len, i) {
437 stat = mxcmci_push(host, sg_virt(sg), sg->length);
438 if (stat)
439 return stat;
440 host->datasize += sg->length;
441 }
442 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
443 if (stat)
444 return stat;
445 }
446 return 0;
447}
448
449static void mxcmci_datawork(struct work_struct *work)
450{
451 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
452 datawork);
453 int datastat = mxcmci_transfer_data(host);
454 mxcmci_finish_data(host, datastat);
455
456 if (host->req->stop) {
457 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
458 mxcmci_finish_request(host, host->req);
459 return;
460 }
461 } else {
462 mxcmci_finish_request(host, host->req);
463 }
464}
465
466#ifdef HAS_DMA
467static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
468{
469 struct mmc_data *data = host->data;
470 int data_error;
471
472 if (!data)
473 return;
474
475 data_error = mxcmci_finish_data(host, stat);
476
477 mxcmci_read_response(host, stat);
478 host->cmd = NULL;
479
480 if (host->req->stop) {
481 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
482 mxcmci_finish_request(host, host->req);
483 return;
484 }
485 } else {
486 mxcmci_finish_request(host, host->req);
487 }
488}
489#endif /* HAS_DMA */
490
491static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
492{
493 mxcmci_read_response(host, stat);
494 host->cmd = NULL;
495
496 if (!host->data && host->req) {
497 mxcmci_finish_request(host, host->req);
498 return;
499 }
500
501 /* For the DMA case the DMA engine handles the data transfer
502 * automatically. For non DMA we have to to it ourselves.
503 * Don't do it in interrupt context though.
504 */
505 if (!mxcmci_use_dma(host) && host->data)
506 schedule_work(&host->datawork);
507
508}
509
510static irqreturn_t mxcmci_irq(int irq, void *devid)
511{
512 struct mxcmci_host *host = devid;
513 u32 stat;
514
515 stat = readl(host->base + MMC_REG_STATUS);
516 writel(stat, host->base + MMC_REG_STATUS);
517
518 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
519
520 if (stat & STATUS_END_CMD_RESP)
521 mxcmci_cmd_done(host, stat);
522#ifdef HAS_DMA
523 if (mxcmci_use_dma(host) &&
524 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
525 mxcmci_data_done(host, stat);
526#endif
527 return IRQ_HANDLED;
528}
529
530static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
531{
532 struct mxcmci_host *host = mmc_priv(mmc);
533 unsigned int cmdat = host->cmdat;
534
535 WARN_ON(host->req != NULL);
536
537 host->req = req;
538 host->cmdat &= ~CMD_DAT_CONT_INIT;
539#ifdef HAS_DMA
540 host->do_dma = 1;
541#endif
542 if (req->data) {
543 mxcmci_setup_data(host, req->data);
544
545 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
546
547 if (req->data->flags & MMC_DATA_WRITE)
548 cmdat |= CMD_DAT_CONT_WRITE;
549 }
550
551 if (mxcmci_start_cmd(host, req->cmd, cmdat))
552 mxcmci_finish_request(host, req);
553}
554
555static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
556{
557 unsigned int divider;
558 int prescaler = 0;
559 unsigned int clk_in = clk_get_rate(host->clk);
560
561 while (prescaler <= 0x800) {
562 for (divider = 1; divider <= 0xF; divider++) {
563 int x;
564
565 x = (clk_in / (divider + 1));
566
567 if (prescaler)
568 x /= (prescaler * 2);
569
570 if (x <= clk_ios)
571 break;
572 }
573 if (divider < 0x10)
574 break;
575
576 if (prescaler == 0)
577 prescaler = 1;
578 else
579 prescaler <<= 1;
580 }
581
582 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
583
584 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
585 prescaler, divider, clk_in, clk_ios);
586}
587
588static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
589{
590 struct mxcmci_host *host = mmc_priv(mmc);
591#ifdef HAS_DMA
592 unsigned int blen;
593 /*
594 * use burstlen of 64 in 4 bit mode (--> reg value 0)
595 * use burstlen of 16 in 1 bit mode (--> reg value 16)
596 */
597 if (ios->bus_width == MMC_BUS_WIDTH_4)
598 blen = 0;
599 else
600 blen = 16;
601
602 imx_dma_config_burstlen(host->dma, blen);
603#endif
604 if (ios->bus_width == MMC_BUS_WIDTH_4)
605 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
606 else
607 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
608
609 if (host->power_mode != ios->power_mode) {
610 if (host->pdata && host->pdata->setpower)
611 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
612 host->power_mode = ios->power_mode;
613 if (ios->power_mode == MMC_POWER_ON)
614 host->cmdat |= CMD_DAT_CONT_INIT;
615 }
616
617 if (ios->clock) {
618 mxcmci_set_clk_rate(host, ios->clock);
619 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
620 } else {
621 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
622 }
623
624 host->clock = ios->clock;
625}
626
627static irqreturn_t mxcmci_detect_irq(int irq, void *data)
628{
629 struct mmc_host *mmc = data;
630
631 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
632
633 mmc_detect_change(mmc, msecs_to_jiffies(250));
634 return IRQ_HANDLED;
635}
636
637static int mxcmci_get_ro(struct mmc_host *mmc)
638{
639 struct mxcmci_host *host = mmc_priv(mmc);
640
641 if (host->pdata && host->pdata->get_ro)
642 return !!host->pdata->get_ro(mmc_dev(mmc));
643 /*
644 * Board doesn't support read only detection; let the mmc core
645 * decide what to do.
646 */
647 return -ENOSYS;
648}
649
650
651static const struct mmc_host_ops mxcmci_ops = {
652 .request = mxcmci_request,
653 .set_ios = mxcmci_set_ios,
654 .get_ro = mxcmci_get_ro,
655};
656
657static int mxcmci_probe(struct platform_device *pdev)
658{
659 struct mmc_host *mmc;
660 struct mxcmci_host *host = NULL;
661 struct resource *r;
662 int ret = 0, irq;
663
664 printk(KERN_INFO "i.MX SDHC driver\n");
665
666 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
667 irq = platform_get_irq(pdev, 0);
668 if (!r || irq < 0)
669 return -EINVAL;
670
671 r = request_mem_region(r->start, resource_size(r), pdev->name);
672 if (!r)
673 return -EBUSY;
674
675 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
676 if (!mmc) {
677 ret = -ENOMEM;
678 goto out_release_mem;
679 }
680
681 mmc->ops = &mxcmci_ops;
682 mmc->caps = MMC_CAP_4_BIT_DATA;
683
684 /* MMC core transfer sizes tunable parameters */
685 mmc->max_hw_segs = 64;
686 mmc->max_phys_segs = 64;
687 mmc->max_blk_size = 2048;
688 mmc->max_blk_count = 65535;
689 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
690 mmc->max_seg_size = mmc->max_seg_size;
691
692 host = mmc_priv(mmc);
693 host->base = ioremap(r->start, resource_size(r));
694 if (!host->base) {
695 ret = -ENOMEM;
696 goto out_free;
697 }
698
699 host->mmc = mmc;
700 host->pdata = pdev->dev.platform_data;
701
702 if (host->pdata && host->pdata->ocr_avail)
703 mmc->ocr_avail = host->pdata->ocr_avail;
704 else
705 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
706
707 host->res = r;
708 host->irq = irq;
709
710 host->clk = clk_get(&pdev->dev, "sdhc_clk");
711 if (IS_ERR(host->clk)) {
712 ret = PTR_ERR(host->clk);
713 goto out_iounmap;
714 }
715 clk_enable(host->clk);
716
717 mxcmci_softreset(host);
718
719 host->rev_no = readw(host->base + MMC_REG_REV_NO);
720 if (host->rev_no != 0x400) {
721 ret = -ENODEV;
722 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
723 host->rev_no);
724 goto out_clk_put;
725 }
726
727 mmc->f_min = clk_get_rate(host->clk) >> 7;
728 mmc->f_max = clk_get_rate(host->clk) >> 1;
729
730 /* recommended in data sheet */
731 writew(0x2db4, host->base + MMC_REG_READ_TO);
732
733 writel(0, host->base + MMC_REG_INT_CNTR);
734
735#ifdef HAS_DMA
736 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
737 if (host->dma < 0) {
738 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
739 ret = -EBUSY;
740 goto out_clk_put;
741 }
742
743 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
744 if (!r) {
745 ret = -EINVAL;
746 goto out_free_dma;
747 }
748
749 ret = imx_dma_config_channel(host->dma,
750 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
751 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
752 r->start, 0);
753 if (ret) {
754 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
755 goto out_free_dma;
756 }
757#endif
758 INIT_WORK(&host->datawork, mxcmci_datawork);
759
760 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
761 if (ret)
762 goto out_free_dma;
763
764 platform_set_drvdata(pdev, mmc);
765
766 if (host->pdata && host->pdata->init) {
767 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
768 host->mmc);
769 if (ret)
770 goto out_free_irq;
771 }
772
773 mmc_add_host(mmc);
774
775 return 0;
776
777out_free_irq:
778 free_irq(host->irq, host);
779out_free_dma:
780#ifdef HAS_DMA
781 imx_dma_free(host->dma);
782#endif
783out_clk_put:
784 clk_disable(host->clk);
785 clk_put(host->clk);
786out_iounmap:
787 iounmap(host->base);
788out_free:
789 mmc_free_host(mmc);
790out_release_mem:
791 release_mem_region(host->res->start, resource_size(host->res));
792 return ret;
793}
794
795static int mxcmci_remove(struct platform_device *pdev)
796{
797 struct mmc_host *mmc = platform_get_drvdata(pdev);
798 struct mxcmci_host *host = mmc_priv(mmc);
799
800 platform_set_drvdata(pdev, NULL);
801
802 mmc_remove_host(mmc);
803
804 if (host->pdata && host->pdata->exit)
805 host->pdata->exit(&pdev->dev, mmc);
806
807 free_irq(host->irq, host);
808 iounmap(host->base);
809#ifdef HAS_DMA
810 imx_dma_free(host->dma);
811#endif
812 clk_disable(host->clk);
813 clk_put(host->clk);
814
815 release_mem_region(host->res->start, resource_size(host->res));
816 release_resource(host->res);
817
818 mmc_free_host(mmc);
819
820 return 0;
821}
822
823#ifdef CONFIG_PM
824static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
825{
826 struct mmc_host *mmc = platform_get_drvdata(dev);
827 int ret = 0;
828
829 if (mmc)
830 ret = mmc_suspend_host(mmc, state);
831
832 return ret;
833}
834
835static int mxcmci_resume(struct platform_device *dev)
836{
837 struct mmc_host *mmc = platform_get_drvdata(dev);
838 struct mxcmci_host *host;
839 int ret = 0;
840
841 if (mmc) {
842 host = mmc_priv(mmc);
843 ret = mmc_resume_host(mmc);
844 }
845
846 return ret;
847}
848#else
849#define mxcmci_suspend NULL
850#define mxcmci_resume NULL
851#endif /* CONFIG_PM */
852
853static struct platform_driver mxcmci_driver = {
854 .probe = mxcmci_probe,
855 .remove = mxcmci_remove,
856 .suspend = mxcmci_suspend,
857 .resume = mxcmci_resume,
858 .driver = {
859 .name = DRIVER_NAME,
860 .owner = THIS_MODULE,
861 }
862};
863
864static int __init mxcmci_init(void)
865{
866 return platform_driver_register(&mxcmci_driver);
867}
868
869static void __exit mxcmci_exit(void)
870{
871 platform_driver_unregister(&mxcmci_driver);
872}
873
874module_init(mxcmci_init);
875module_exit(mxcmci_exit);
876
877MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
878MODULE_AUTHOR("Sascha Hauer, Pengutronix");
879MODULE_LICENSE("GPL");
880MODULE_ALIAS("platform:imx-mmc");
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
new file mode 100644
index 000000000000..a631c81dce12
--- /dev/null
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -0,0 +1,1280 @@
1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
24#include <linux/workqueue.h>
25#include <linux/timer.h>
26#include <linux/clk.h>
27#include <linux/mmc/host.h>
28#include <linux/io.h>
29#include <linux/semaphore.h>
30#include <mach/dma.h>
31#include <mach/hardware.h>
32#include <mach/board.h>
33#include <mach/mmc.h>
34#include <mach/cpu.h>
35
36/* OMAP HSMMC Host Controller Registers */
37#define OMAP_HSMMC_SYSCONFIG 0x0010
38#define OMAP_HSMMC_CON 0x002C
39#define OMAP_HSMMC_BLK 0x0104
40#define OMAP_HSMMC_ARG 0x0108
41#define OMAP_HSMMC_CMD 0x010C
42#define OMAP_HSMMC_RSP10 0x0110
43#define OMAP_HSMMC_RSP32 0x0114
44#define OMAP_HSMMC_RSP54 0x0118
45#define OMAP_HSMMC_RSP76 0x011C
46#define OMAP_HSMMC_DATA 0x0120
47#define OMAP_HSMMC_HCTL 0x0128
48#define OMAP_HSMMC_SYSCTL 0x012C
49#define OMAP_HSMMC_STAT 0x0130
50#define OMAP_HSMMC_IE 0x0134
51#define OMAP_HSMMC_ISE 0x0138
52#define OMAP_HSMMC_CAPA 0x0140
53
54#define VS18 (1 << 26)
55#define VS30 (1 << 25)
56#define SDVS18 (0x5 << 9)
57#define SDVS30 (0x6 << 9)
58#define SDVS33 (0x7 << 9)
59#define SDVSCLR 0xFFFFF1FF
60#define SDVSDET 0x00000400
61#define AUTOIDLE 0x1
62#define SDBP (1 << 8)
63#define DTO 0xe
64#define ICE 0x1
65#define ICS 0x2
66#define CEN (1 << 2)
67#define CLKD_MASK 0x0000FFC0
68#define CLKD_SHIFT 6
69#define DTO_MASK 0x000F0000
70#define DTO_SHIFT 16
71#define INT_EN_MASK 0x307F0033
72#define INIT_STREAM (1 << 1)
73#define DP_SELECT (1 << 21)
74#define DDIR (1 << 4)
75#define DMA_EN 0x1
76#define MSBS (1 << 5)
77#define BCE (1 << 1)
78#define FOUR_BIT (1 << 1)
79#define CC 0x1
80#define TC 0x02
81#define OD 0x1
82#define ERR (1 << 15)
83#define CMD_TIMEOUT (1 << 16)
84#define DATA_TIMEOUT (1 << 20)
85#define CMD_CRC (1 << 17)
86#define DATA_CRC (1 << 21)
87#define CARD_ERR (1 << 28)
88#define STAT_CLEAR 0xFFFFFFFF
89#define INIT_STREAM_CMD 0x00000000
90#define DUAL_VOLT_OCR_BIT 7
91#define SRC (1 << 25)
92#define SRD (1 << 26)
93
94/*
95 * FIXME: Most likely all the data using these _DEVID defines should come
96 * from the platform_data, or implemented in controller and slot specific
97 * functions.
98 */
99#define OMAP_MMC1_DEVID 0
100#define OMAP_MMC2_DEVID 1
101
102#define OMAP_MMC_DATADIR_NONE 0
103#define OMAP_MMC_DATADIR_READ 1
104#define OMAP_MMC_DATADIR_WRITE 2
105#define MMC_TIMEOUT_MS 20
106#define OMAP_MMC_MASTER_CLOCK 96000000
107#define DRIVER_NAME "mmci-omap-hs"
108
109/*
110 * One controller can have multiple slots, like on some omap boards using
111 * omap.c controller driver. Luckily this is not currently done on any known
112 * omap_hsmmc.c device.
113 */
114#define mmc_slot(host) (host->pdata->slots[host->slot_id])
115
116/*
117 * MMC Host controller read/write API's
118 */
119#define OMAP_HSMMC_READ(base, reg) \
120 __raw_readl((base) + OMAP_HSMMC_##reg)
121
122#define OMAP_HSMMC_WRITE(base, reg, val) \
123 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
124
125struct mmc_omap_host {
126 struct device *dev;
127 struct mmc_host *mmc;
128 struct mmc_request *mrq;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
131 struct clk *fclk;
132 struct clk *iclk;
133 struct clk *dbclk;
134 struct semaphore sem;
135 struct work_struct mmc_carddetect_work;
136 void __iomem *base;
137 resource_size_t mapbase;
138 unsigned int id;
139 unsigned int dma_len;
140 unsigned int dma_dir;
141 unsigned char bus_mode;
142 unsigned char datadir;
143 u32 *buffer;
144 u32 bytesleft;
145 int suspended;
146 int irq;
147 int carddetect;
148 int use_dma, dma_ch;
149 int initstr;
150 int slot_id;
151 int dbclk_enabled;
152 struct omap_mmc_platform_data *pdata;
153};
154
155/*
156 * Stop clock to the card
157 */
158static void omap_mmc_stop_clock(struct mmc_omap_host *host)
159{
160 OMAP_HSMMC_WRITE(host->base, SYSCTL,
161 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
162 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
163 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
164}
165
166/*
167 * Send init stream sequence to card
168 * before sending IDLE command
169 */
170static void send_init_stream(struct mmc_omap_host *host)
171{
172 int reg = 0;
173 unsigned long timeout;
174
175 disable_irq(host->irq);
176 OMAP_HSMMC_WRITE(host->base, CON,
177 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
178 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
179
180 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
181 while ((reg != CC) && time_before(jiffies, timeout))
182 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
183
184 OMAP_HSMMC_WRITE(host->base, CON,
185 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
186 enable_irq(host->irq);
187}
188
189static inline
190int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
191{
192 int r = 1;
193
194 if (host->pdata->slots[host->slot_id].get_cover_state)
195 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
196 host->slot_id);
197 return r;
198}
199
200static ssize_t
201mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
202 char *buf)
203{
204 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
205 struct mmc_omap_host *host = mmc_priv(mmc);
206
207 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
208 "open");
209}
210
211static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
212
213static ssize_t
214mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
215 char *buf)
216{
217 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
218 struct mmc_omap_host *host = mmc_priv(mmc);
219 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
220
221 return sprintf(buf, "slot:%s\n", slot.name);
222}
223
224static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
225
226/*
227 * Configure the response type and send the cmd.
228 */
229static void
230mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
231 struct mmc_data *data)
232{
233 int cmdreg = 0, resptype = 0, cmdtype = 0;
234
235 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
236 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
237 host->cmd = cmd;
238
239 /*
240 * Clear status bits and enable interrupts
241 */
242 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
243 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
244 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
245
246 if (cmd->flags & MMC_RSP_PRESENT) {
247 if (cmd->flags & MMC_RSP_136)
248 resptype = 1;
249 else
250 resptype = 2;
251 }
252
253 /*
254 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
255 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
256 * a val of 0x3, rest 0x0.
257 */
258 if (cmd == host->mrq->stop)
259 cmdtype = 0x3;
260
261 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
262
263 if (data) {
264 cmdreg |= DP_SELECT | MSBS | BCE;
265 if (data->flags & MMC_DATA_READ)
266 cmdreg |= DDIR;
267 else
268 cmdreg &= ~(DDIR);
269 }
270
271 if (host->use_dma)
272 cmdreg |= DMA_EN;
273
274 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
275 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
276}
277
278/*
279 * Notify the transfer complete to MMC core
280 */
281static void
282mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
283{
284 host->data = NULL;
285
286 if (host->use_dma && host->dma_ch != -1)
287 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
288 host->dma_dir);
289
290 host->datadir = OMAP_MMC_DATADIR_NONE;
291
292 if (!data->error)
293 data->bytes_xfered += data->blocks * (data->blksz);
294 else
295 data->bytes_xfered = 0;
296
297 if (!data->stop) {
298 host->mrq = NULL;
299 mmc_request_done(host->mmc, data->mrq);
300 return;
301 }
302 mmc_omap_start_command(host, data->stop, NULL);
303}
304
305/*
306 * Notify the core about command completion
307 */
308static void
309mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
310{
311 host->cmd = NULL;
312
313 if (cmd->flags & MMC_RSP_PRESENT) {
314 if (cmd->flags & MMC_RSP_136) {
315 /* response type 2 */
316 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
317 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
318 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
319 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
320 } else {
321 /* response types 1, 1b, 3, 4, 5, 6 */
322 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
323 }
324 }
325 if (host->data == NULL || cmd->error) {
326 host->mrq = NULL;
327 mmc_request_done(host->mmc, cmd->mrq);
328 }
329}
330
331/*
332 * DMA clean up for command errors
333 */
334static void mmc_dma_cleanup(struct mmc_omap_host *host)
335{
336 host->data->error = -ETIMEDOUT;
337
338 if (host->use_dma && host->dma_ch != -1) {
339 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
340 host->dma_dir);
341 omap_free_dma(host->dma_ch);
342 host->dma_ch = -1;
343 up(&host->sem);
344 }
345 host->data = NULL;
346 host->datadir = OMAP_MMC_DATADIR_NONE;
347}
348
349/*
350 * Readable error output
351 */
352#ifdef CONFIG_MMC_DEBUG
353static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
354{
355 /* --- means reserved bit without definition at documentation */
356 static const char *mmc_omap_status_bits[] = {
357 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
358 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
359 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
360 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
361 };
362 char res[256];
363 char *buf = res;
364 int len, i;
365
366 len = sprintf(buf, "MMC IRQ 0x%x :", status);
367 buf += len;
368
369 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
370 if (status & (1 << i)) {
371 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
372 buf += len;
373 }
374
375 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
376}
377#endif /* CONFIG_MMC_DEBUG */
378
379/*
380 * MMC controller internal state machines reset
381 *
382 * Used to reset command or data internal state machines, using respectively
383 * SRC or SRD bit of SYSCTL register
384 * Can be called from interrupt context
385 */
386static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
387 unsigned long bit)
388{
389 unsigned long i = 0;
390 unsigned long limit = (loops_per_jiffy *
391 msecs_to_jiffies(MMC_TIMEOUT_MS));
392
393 OMAP_HSMMC_WRITE(host->base, SYSCTL,
394 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
395
396 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
397 (i++ < limit))
398 cpu_relax();
399
400 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
401 dev_err(mmc_dev(host->mmc),
402 "Timeout waiting on controller reset in %s\n",
403 __func__);
404}
405
406/*
407 * MMC controller IRQ handler
408 */
409static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
410{
411 struct mmc_omap_host *host = dev_id;
412 struct mmc_data *data;
413 int end_cmd = 0, end_trans = 0, status;
414
415 if (host->cmd == NULL && host->data == NULL) {
416 OMAP_HSMMC_WRITE(host->base, STAT,
417 OMAP_HSMMC_READ(host->base, STAT));
418 return IRQ_HANDLED;
419 }
420
421 data = host->data;
422 status = OMAP_HSMMC_READ(host->base, STAT);
423 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
424
425 if (status & ERR) {
426#ifdef CONFIG_MMC_DEBUG
427 mmc_omap_report_irq(host, status);
428#endif
429 if ((status & CMD_TIMEOUT) ||
430 (status & CMD_CRC)) {
431 if (host->cmd) {
432 if (status & CMD_TIMEOUT) {
433 mmc_omap_reset_controller_fsm(host, SRC);
434 host->cmd->error = -ETIMEDOUT;
435 } else {
436 host->cmd->error = -EILSEQ;
437 }
438 end_cmd = 1;
439 }
440 if (host->data) {
441 mmc_dma_cleanup(host);
442 mmc_omap_reset_controller_fsm(host, SRD);
443 }
444 }
445 if ((status & DATA_TIMEOUT) ||
446 (status & DATA_CRC)) {
447 if (host->data) {
448 if (status & DATA_TIMEOUT)
449 mmc_dma_cleanup(host);
450 else
451 host->data->error = -EILSEQ;
452 mmc_omap_reset_controller_fsm(host, SRD);
453 end_trans = 1;
454 }
455 }
456 if (status & CARD_ERR) {
457 dev_dbg(mmc_dev(host->mmc),
458 "Ignoring card err CMD%d\n", host->cmd->opcode);
459 if (host->cmd)
460 end_cmd = 1;
461 if (host->data)
462 end_trans = 1;
463 }
464 }
465
466 OMAP_HSMMC_WRITE(host->base, STAT, status);
467
468 if (end_cmd || (status & CC))
469 mmc_omap_cmd_done(host, host->cmd);
470 if (end_trans || (status & TC))
471 mmc_omap_xfer_done(host, data);
472
473 return IRQ_HANDLED;
474}
475
476/*
477 * Switch MMC interface voltage ... only relevant for MMC1.
478 *
479 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
480 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
481 * Some chips, like eMMC ones, use internal transceivers.
482 */
483static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
484{
485 u32 reg_val = 0;
486 int ret;
487
488 if (host->id != OMAP_MMC1_DEVID)
489 return 0;
490
491 /* Disable the clocks */
492 clk_disable(host->fclk);
493 clk_disable(host->iclk);
494 clk_disable(host->dbclk);
495
496 /* Turn the power off */
497 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
498 if (ret != 0)
499 goto err;
500
501 /* Turn the power ON with given VDD 1.8 or 3.0v */
502 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
503 if (ret != 0)
504 goto err;
505
506 clk_enable(host->fclk);
507 clk_enable(host->iclk);
508 clk_enable(host->dbclk);
509
510 OMAP_HSMMC_WRITE(host->base, HCTL,
511 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
512 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
513
514 /*
515 * If a MMC dual voltage card is detected, the set_ios fn calls
516 * this fn with VDD bit set for 1.8V. Upon card removal from the
517 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
518 *
519 * Cope with a bit of slop in the range ... per data sheets:
520 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
521 * but recommended values are 1.71V to 1.89V
522 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
523 * but recommended values are 2.7V to 3.3V
524 *
525 * Board setup code shouldn't permit anything very out-of-range.
526 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
527 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
528 */
529 if ((1 << vdd) <= MMC_VDD_23_24)
530 reg_val |= SDVS18;
531 else
532 reg_val |= SDVS30;
533
534 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
535
536 OMAP_HSMMC_WRITE(host->base, HCTL,
537 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
538
539 return 0;
540err:
541 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
542 return ret;
543}
544
545/*
546 * Work Item to notify the core about card insertion/removal
547 */
548static void mmc_omap_detect(struct work_struct *work)
549{
550 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
551 mmc_carddetect_work);
552 struct omap_mmc_slot_data *slot = &mmc_slot(host);
553
554 host->carddetect = slot->card_detect(slot->card_detect_irq);
555
556 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
557 if (host->carddetect) {
558 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
559 } else {
560 mmc_omap_reset_controller_fsm(host, SRD);
561 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
562 }
563}
564
565/*
566 * ISR for handling card insertion and removal
567 */
568static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
569{
570 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
571
572 schedule_work(&host->mmc_carddetect_work);
573
574 return IRQ_HANDLED;
575}
576
577/*
578 * DMA call back function
579 */
580static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
581{
582 struct mmc_omap_host *host = data;
583
584 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
585 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
586
587 if (host->dma_ch < 0)
588 return;
589
590 omap_free_dma(host->dma_ch);
591 host->dma_ch = -1;
592 /*
593 * DMA Callback: run in interrupt context.
594 * mutex_unlock will through a kernel warning if used.
595 */
596 up(&host->sem);
597}
598
599/*
600 * Configure dma src and destination parameters
601 */
602static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
603 struct mmc_data *data)
604{
605 if (sync_dir == 0) {
606 omap_set_dma_dest_params(host->dma_ch, 0,
607 OMAP_DMA_AMODE_CONSTANT,
608 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
609 omap_set_dma_src_params(host->dma_ch, 0,
610 OMAP_DMA_AMODE_POST_INC,
611 sg_dma_address(&data->sg[0]), 0, 0);
612 } else {
613 omap_set_dma_src_params(host->dma_ch, 0,
614 OMAP_DMA_AMODE_CONSTANT,
615 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
616 omap_set_dma_dest_params(host->dma_ch, 0,
617 OMAP_DMA_AMODE_POST_INC,
618 sg_dma_address(&data->sg[0]), 0, 0);
619 }
620 return 0;
621}
622/*
623 * Routine to configure and start DMA for the MMC card
624 */
625static int
626mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
627{
628 int sync_dev, sync_dir = 0;
629 int dma_ch = 0, ret = 0, err = 1;
630 struct mmc_data *data = req->data;
631
632 /*
633 * If for some reason the DMA transfer is still active,
634 * we wait for timeout period and free the dma
635 */
636 if (host->dma_ch != -1) {
637 set_current_state(TASK_UNINTERRUPTIBLE);
638 schedule_timeout(100);
639 if (down_trylock(&host->sem)) {
640 omap_free_dma(host->dma_ch);
641 host->dma_ch = -1;
642 up(&host->sem);
643 return err;
644 }
645 } else {
646 if (down_trylock(&host->sem))
647 return err;
648 }
649
650 if (!(data->flags & MMC_DATA_WRITE)) {
651 host->dma_dir = DMA_FROM_DEVICE;
652 if (host->id == OMAP_MMC1_DEVID)
653 sync_dev = OMAP24XX_DMA_MMC1_RX;
654 else
655 sync_dev = OMAP24XX_DMA_MMC2_RX;
656 } else {
657 host->dma_dir = DMA_TO_DEVICE;
658 if (host->id == OMAP_MMC1_DEVID)
659 sync_dev = OMAP24XX_DMA_MMC1_TX;
660 else
661 sync_dev = OMAP24XX_DMA_MMC2_TX;
662 }
663
664 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
665 host, &dma_ch);
666 if (ret != 0) {
667 dev_dbg(mmc_dev(host->mmc),
668 "%s: omap_request_dma() failed with %d\n",
669 mmc_hostname(host->mmc), ret);
670 return ret;
671 }
672
673 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
674 data->sg_len, host->dma_dir);
675 host->dma_ch = dma_ch;
676
677 if (!(data->flags & MMC_DATA_WRITE))
678 mmc_omap_config_dma_param(1, host, data);
679 else
680 mmc_omap_config_dma_param(0, host, data);
681
682 if ((data->blksz % 4) == 0)
683 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
684 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
685 sync_dev, sync_dir);
686 else
687 /* REVISIT: The MMC buffer increments only when MSB is written.
688 * Return error for blksz which is non multiple of four.
689 */
690 return -EINVAL;
691
692 omap_start_dma(dma_ch);
693 return 0;
694}
695
696static void set_data_timeout(struct mmc_omap_host *host,
697 struct mmc_request *req)
698{
699 unsigned int timeout, cycle_ns;
700 uint32_t reg, clkd, dto = 0;
701
702 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
703 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
704 if (clkd == 0)
705 clkd = 1;
706
707 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
708 timeout = req->data->timeout_ns / cycle_ns;
709 timeout += req->data->timeout_clks;
710 if (timeout) {
711 while ((timeout & 0x80000000) == 0) {
712 dto += 1;
713 timeout <<= 1;
714 }
715 dto = 31 - dto;
716 timeout <<= 1;
717 if (timeout && dto)
718 dto += 1;
719 if (dto >= 13)
720 dto -= 13;
721 else
722 dto = 0;
723 if (dto > 14)
724 dto = 14;
725 }
726
727 reg &= ~DTO_MASK;
728 reg |= dto << DTO_SHIFT;
729 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
730}
731
732/*
733 * Configure block length for MMC/SD cards and initiate the transfer.
734 */
735static int
736mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
737{
738 int ret;
739 host->data = req->data;
740
741 if (req->data == NULL) {
742 host->datadir = OMAP_MMC_DATADIR_NONE;
743 OMAP_HSMMC_WRITE(host->base, BLK, 0);
744 return 0;
745 }
746
747 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
748 | (req->data->blocks << 16));
749 set_data_timeout(host, req);
750
751 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
752 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
753
754 if (host->use_dma) {
755 ret = mmc_omap_start_dma_transfer(host, req);
756 if (ret != 0) {
757 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
758 return ret;
759 }
760 }
761 return 0;
762}
763
764/*
765 * Request function. for read/write operation
766 */
767static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
768{
769 struct mmc_omap_host *host = mmc_priv(mmc);
770
771 WARN_ON(host->mrq != NULL);
772 host->mrq = req;
773 mmc_omap_prepare_data(host, req);
774 mmc_omap_start_command(host, req->cmd, req->data);
775}
776
777
778/* Routine to configure clock values. Exposed API to core */
779static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
780{
781 struct mmc_omap_host *host = mmc_priv(mmc);
782 u16 dsor = 0;
783 unsigned long regval;
784 unsigned long timeout;
785
786 switch (ios->power_mode) {
787 case MMC_POWER_OFF:
788 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
789 /*
790 * Reset interface voltage to 3V if it's 1.8V now;
791 * only relevant on MMC-1, the others always use 1.8V.
792 *
793 * REVISIT: If we are able to detect cards after unplugging
794 * a 1.8V card, this code should not be needed.
795 */
796 if (host->id != OMAP_MMC1_DEVID)
797 break;
798 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
799 int vdd = fls(host->mmc->ocr_avail) - 1;
800 if (omap_mmc_switch_opcond(host, vdd) != 0)
801 host->mmc->ios.vdd = vdd;
802 }
803 break;
804 case MMC_POWER_UP:
805 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
806 break;
807 }
808
809 switch (mmc->ios.bus_width) {
810 case MMC_BUS_WIDTH_4:
811 OMAP_HSMMC_WRITE(host->base, HCTL,
812 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
813 break;
814 case MMC_BUS_WIDTH_1:
815 OMAP_HSMMC_WRITE(host->base, HCTL,
816 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
817 break;
818 }
819
820 if (host->id == OMAP_MMC1_DEVID) {
821 /* Only MMC1 can interface at 3V without some flavor
822 * of external transceiver; but they all handle 1.8V.
823 */
824 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
825 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
826 /*
827 * The mmc_select_voltage fn of the core does
828 * not seem to set the power_mode to
829 * MMC_POWER_UP upon recalculating the voltage.
830 * vdd 1.8v.
831 */
832 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
833 dev_dbg(mmc_dev(host->mmc),
834 "Switch operation failed\n");
835 }
836 }
837
838 if (ios->clock) {
839 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
840 if (dsor < 1)
841 dsor = 1;
842
843 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
844 dsor++;
845
846 if (dsor > 250)
847 dsor = 250;
848 }
849 omap_mmc_stop_clock(host);
850 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
851 regval = regval & ~(CLKD_MASK);
852 regval = regval | (dsor << 6) | (DTO << 16);
853 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
854 OMAP_HSMMC_WRITE(host->base, SYSCTL,
855 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
856
857 /* Wait till the ICS bit is set */
858 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
859 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
860 && time_before(jiffies, timeout))
861 msleep(1);
862
863 OMAP_HSMMC_WRITE(host->base, SYSCTL,
864 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
865
866 if (ios->power_mode == MMC_POWER_ON)
867 send_init_stream(host);
868
869 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
870 OMAP_HSMMC_WRITE(host->base, CON,
871 OMAP_HSMMC_READ(host->base, CON) | OD);
872}
873
874static int omap_hsmmc_get_cd(struct mmc_host *mmc)
875{
876 struct mmc_omap_host *host = mmc_priv(mmc);
877 struct omap_mmc_platform_data *pdata = host->pdata;
878
879 if (!pdata->slots[0].card_detect)
880 return -ENOSYS;
881 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
882}
883
884static int omap_hsmmc_get_ro(struct mmc_host *mmc)
885{
886 struct mmc_omap_host *host = mmc_priv(mmc);
887 struct omap_mmc_platform_data *pdata = host->pdata;
888
889 if (!pdata->slots[0].get_ro)
890 return -ENOSYS;
891 return pdata->slots[0].get_ro(host->dev, 0);
892}
893
894static struct mmc_host_ops mmc_omap_ops = {
895 .request = omap_mmc_request,
896 .set_ios = omap_mmc_set_ios,
897 .get_cd = omap_hsmmc_get_cd,
898 .get_ro = omap_hsmmc_get_ro,
899 /* NYET -- enable_sdio_irq */
900};
901
902static int __init omap_mmc_probe(struct platform_device *pdev)
903{
904 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
905 struct mmc_host *mmc;
906 struct mmc_omap_host *host = NULL;
907 struct resource *res;
908 int ret = 0, irq;
909 u32 hctl, capa;
910
911 if (pdata == NULL) {
912 dev_err(&pdev->dev, "Platform Data is missing\n");
913 return -ENXIO;
914 }
915
916 if (pdata->nr_slots == 0) {
917 dev_err(&pdev->dev, "No Slots\n");
918 return -ENXIO;
919 }
920
921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 irq = platform_get_irq(pdev, 0);
923 if (res == NULL || irq < 0)
924 return -ENXIO;
925
926 res = request_mem_region(res->start, res->end - res->start + 1,
927 pdev->name);
928 if (res == NULL)
929 return -EBUSY;
930
931 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
932 if (!mmc) {
933 ret = -ENOMEM;
934 goto err;
935 }
936
937 host = mmc_priv(mmc);
938 host->mmc = mmc;
939 host->pdata = pdata;
940 host->dev = &pdev->dev;
941 host->use_dma = 1;
942 host->dev->dma_mask = &pdata->dma_mask;
943 host->dma_ch = -1;
944 host->irq = irq;
945 host->id = pdev->id;
946 host->slot_id = 0;
947 host->mapbase = res->start;
948 host->base = ioremap(host->mapbase, SZ_4K);
949
950 platform_set_drvdata(pdev, host);
951 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
952
953 mmc->ops = &mmc_omap_ops;
954 mmc->f_min = 400000;
955 mmc->f_max = 52000000;
956
957 sema_init(&host->sem, 1);
958
959 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
960 if (IS_ERR(host->iclk)) {
961 ret = PTR_ERR(host->iclk);
962 host->iclk = NULL;
963 goto err1;
964 }
965 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
966 if (IS_ERR(host->fclk)) {
967 ret = PTR_ERR(host->fclk);
968 host->fclk = NULL;
969 clk_put(host->iclk);
970 goto err1;
971 }
972
973 if (clk_enable(host->fclk) != 0) {
974 clk_put(host->iclk);
975 clk_put(host->fclk);
976 goto err1;
977 }
978
979 if (clk_enable(host->iclk) != 0) {
980 clk_disable(host->fclk);
981 clk_put(host->iclk);
982 clk_put(host->fclk);
983 goto err1;
984 }
985
986 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
987 /*
988 * MMC can still work without debounce clock.
989 */
990 if (IS_ERR(host->dbclk))
991 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
992 else
993 if (clk_enable(host->dbclk) != 0)
994 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
995 " clk failed\n");
996 else
997 host->dbclk_enabled = 1;
998
999#ifdef CONFIG_MMC_BLOCK_BOUNCE
1000 mmc->max_phys_segs = 1;
1001 mmc->max_hw_segs = 1;
1002#endif
1003 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1004 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1005 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1006 mmc->max_seg_size = mmc->max_req_size;
1007
1008 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1009 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1010
1011 if (pdata->slots[host->slot_id].wires >= 4)
1012 mmc->caps |= MMC_CAP_4_BIT_DATA;
1013
1014 /* Only MMC1 supports 3.0V */
1015 if (host->id == OMAP_MMC1_DEVID) {
1016 hctl = SDVS30;
1017 capa = VS30 | VS18;
1018 } else {
1019 hctl = SDVS18;
1020 capa = VS18;
1021 }
1022
1023 OMAP_HSMMC_WRITE(host->base, HCTL,
1024 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1025
1026 OMAP_HSMMC_WRITE(host->base, CAPA,
1027 OMAP_HSMMC_READ(host->base, CAPA) | capa);
1028
1029 /* Set the controller to AUTO IDLE mode */
1030 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1031 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1032
1033 /* Set SD bus power bit */
1034 OMAP_HSMMC_WRITE(host->base, HCTL,
1035 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1036
1037 /* Request IRQ for MMC operations */
1038 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1039 mmc_hostname(mmc), host);
1040 if (ret) {
1041 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1042 goto err_irq;
1043 }
1044
1045 if (pdata->init != NULL) {
1046 if (pdata->init(&pdev->dev) != 0) {
1047 dev_dbg(mmc_dev(host->mmc),
1048 "Unable to configure MMC IRQs\n");
1049 goto err_irq_cd_init;
1050 }
1051 }
1052
1053 /* Request IRQ for card detect */
1054 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1055 ret = request_irq(mmc_slot(host).card_detect_irq,
1056 omap_mmc_cd_handler,
1057 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1058 | IRQF_DISABLED,
1059 mmc_hostname(mmc), host);
1060 if (ret) {
1061 dev_dbg(mmc_dev(host->mmc),
1062 "Unable to grab MMC CD IRQ\n");
1063 goto err_irq_cd;
1064 }
1065 }
1066
1067 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1068 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1069
1070 mmc_add_host(mmc);
1071
1072 if (host->pdata->slots[host->slot_id].name != NULL) {
1073 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1074 if (ret < 0)
1075 goto err_slot_name;
1076 }
1077 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1078 host->pdata->slots[host->slot_id].get_cover_state) {
1079 ret = device_create_file(&mmc->class_dev,
1080 &dev_attr_cover_switch);
1081 if (ret < 0)
1082 goto err_cover_switch;
1083 }
1084
1085 return 0;
1086
1087err_cover_switch:
1088 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1089err_slot_name:
1090 mmc_remove_host(mmc);
1091err_irq_cd:
1092 free_irq(mmc_slot(host).card_detect_irq, host);
1093err_irq_cd_init:
1094 free_irq(host->irq, host);
1095err_irq:
1096 clk_disable(host->fclk);
1097 clk_disable(host->iclk);
1098 clk_put(host->fclk);
1099 clk_put(host->iclk);
1100 if (host->dbclk_enabled) {
1101 clk_disable(host->dbclk);
1102 clk_put(host->dbclk);
1103 }
1104
1105err1:
1106 iounmap(host->base);
1107err:
1108 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1109 release_mem_region(res->start, res->end - res->start + 1);
1110 if (host)
1111 mmc_free_host(mmc);
1112 return ret;
1113}
1114
1115static int omap_mmc_remove(struct platform_device *pdev)
1116{
1117 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1118 struct resource *res;
1119
1120 if (host) {
1121 mmc_remove_host(host->mmc);
1122 if (host->pdata->cleanup)
1123 host->pdata->cleanup(&pdev->dev);
1124 free_irq(host->irq, host);
1125 if (mmc_slot(host).card_detect_irq)
1126 free_irq(mmc_slot(host).card_detect_irq, host);
1127 flush_scheduled_work();
1128
1129 clk_disable(host->fclk);
1130 clk_disable(host->iclk);
1131 clk_put(host->fclk);
1132 clk_put(host->iclk);
1133 if (host->dbclk_enabled) {
1134 clk_disable(host->dbclk);
1135 clk_put(host->dbclk);
1136 }
1137
1138 mmc_free_host(host->mmc);
1139 iounmap(host->base);
1140 }
1141
1142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1143 if (res)
1144 release_mem_region(res->start, res->end - res->start + 1);
1145 platform_set_drvdata(pdev, NULL);
1146
1147 return 0;
1148}
1149
1150#ifdef CONFIG_PM
1151static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1152{
1153 int ret = 0;
1154 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1155
1156 if (host && host->suspended)
1157 return 0;
1158
1159 if (host) {
1160 ret = mmc_suspend_host(host->mmc, state);
1161 if (ret == 0) {
1162 host->suspended = 1;
1163
1164 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1165 OMAP_HSMMC_WRITE(host->base, IE, 0);
1166
1167 if (host->pdata->suspend) {
1168 ret = host->pdata->suspend(&pdev->dev,
1169 host->slot_id);
1170 if (ret)
1171 dev_dbg(mmc_dev(host->mmc),
1172 "Unable to handle MMC board"
1173 " level suspend\n");
1174 }
1175
1176 if (host->id == OMAP_MMC1_DEVID
1177 && !(OMAP_HSMMC_READ(host->base, HCTL)
1178 & SDVSDET)) {
1179 OMAP_HSMMC_WRITE(host->base, HCTL,
1180 OMAP_HSMMC_READ(host->base, HCTL)
1181 & SDVSCLR);
1182 OMAP_HSMMC_WRITE(host->base, HCTL,
1183 OMAP_HSMMC_READ(host->base, HCTL)
1184 | SDVS30);
1185 OMAP_HSMMC_WRITE(host->base, HCTL,
1186 OMAP_HSMMC_READ(host->base, HCTL)
1187 | SDBP);
1188 }
1189
1190 clk_disable(host->fclk);
1191 clk_disable(host->iclk);
1192 clk_disable(host->dbclk);
1193 }
1194
1195 }
1196 return ret;
1197}
1198
1199/* Routine to resume the MMC device */
1200static int omap_mmc_resume(struct platform_device *pdev)
1201{
1202 int ret = 0;
1203 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1204
1205 if (host && !host->suspended)
1206 return 0;
1207
1208 if (host) {
1209
1210 ret = clk_enable(host->fclk);
1211 if (ret)
1212 goto clk_en_err;
1213
1214 ret = clk_enable(host->iclk);
1215 if (ret) {
1216 clk_disable(host->fclk);
1217 clk_put(host->fclk);
1218 goto clk_en_err;
1219 }
1220
1221 if (clk_enable(host->dbclk) != 0)
1222 dev_dbg(mmc_dev(host->mmc),
1223 "Enabling debounce clk failed\n");
1224
1225 if (host->pdata->resume) {
1226 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1227 if (ret)
1228 dev_dbg(mmc_dev(host->mmc),
1229 "Unmask interrupt failed\n");
1230 }
1231
1232 /* Notify the core to resume the host */
1233 ret = mmc_resume_host(host->mmc);
1234 if (ret == 0)
1235 host->suspended = 0;
1236 }
1237
1238 return ret;
1239
1240clk_en_err:
1241 dev_dbg(mmc_dev(host->mmc),
1242 "Failed to enable MMC clocks during resume\n");
1243 return ret;
1244}
1245
1246#else
1247#define omap_mmc_suspend NULL
1248#define omap_mmc_resume NULL
1249#endif
1250
1251static struct platform_driver omap_mmc_driver = {
1252 .probe = omap_mmc_probe,
1253 .remove = omap_mmc_remove,
1254 .suspend = omap_mmc_suspend,
1255 .resume = omap_mmc_resume,
1256 .driver = {
1257 .name = DRIVER_NAME,
1258 .owner = THIS_MODULE,
1259 },
1260};
1261
1262static int __init omap_mmc_init(void)
1263{
1264 /* Register the MMC driver */
1265 return platform_driver_register(&omap_mmc_driver);
1266}
1267
1268static void __exit omap_mmc_cleanup(void)
1269{
1270 /* Unregister MMC driver */
1271 platform_driver_unregister(&omap_mmc_driver);
1272}
1273
1274module_init(omap_mmc_init);
1275module_exit(omap_mmc_cleanup);
1276
1277MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1278MODULE_LICENSE("GPL");
1279MODULE_ALIAS("platform:" DRIVER_NAME);
1280MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 3c5483b75da4..9702ad3774cf 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -180,7 +180,15 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
180 else 180 else
181 DALGN &= ~(1 << host->dma); 181 DALGN &= ~(1 << host->dma);
182 DDADR(host->dma) = host->sg_dma; 182 DDADR(host->dma) = host->sg_dma;
183 DCSR(host->dma) = DCSR_RUN; 183
184 /*
185 * workaround for erratum #91:
186 * only start DMA now if we are doing a read,
187 * otherwise we wait until CMD/RESP has finished
188 * before starting DMA.
189 */
190 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
191 DCSR(host->dma) = DCSR_RUN;
184} 192}
185 193
186static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) 194static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
@@ -251,23 +259,28 @@ static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
251 if (stat & STAT_TIME_OUT_RESPONSE) { 259 if (stat & STAT_TIME_OUT_RESPONSE) {
252 cmd->error = -ETIMEDOUT; 260 cmd->error = -ETIMEDOUT;
253 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 261 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
254#ifdef CONFIG_PXA27x
255 /* 262 /*
256 * workaround for erratum #42: 263 * workaround for erratum #42:
257 * Intel PXA27x Family Processor Specification Update Rev 001 264 * Intel PXA27x Family Processor Specification Update Rev 001
258 * A bogus CRC error can appear if the msb of a 136 bit 265 * A bogus CRC error can appear if the msb of a 136 bit
259 * response is a one. 266 * response is a one.
260 */ 267 */
261 if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) { 268 if (cpu_is_pxa27x() &&
269 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
262 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); 270 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
263 } else 271 else
264#endif 272 cmd->error = -EILSEQ;
265 cmd->error = -EILSEQ;
266 } 273 }
267 274
268 pxamci_disable_irq(host, END_CMD_RES); 275 pxamci_disable_irq(host, END_CMD_RES);
269 if (host->data && !cmd->error) { 276 if (host->data && !cmd->error) {
270 pxamci_enable_irq(host, DATA_TRAN_DONE); 277 pxamci_enable_irq(host, DATA_TRAN_DONE);
278 /*
279 * workaround for erratum #91, if doing write
280 * enable DMA late
281 */
282 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
283 DCSR(host->dma) = DCSR_RUN;
271 } else { 284 } else {
272 pxamci_finish_request(host, host->mrq); 285 pxamci_finish_request(host, host->mrq);
273 } 286 }
diff --git a/drivers/mmc/host/ricoh_mmc.c b/drivers/mmc/host/ricoh_mmc.c
index be9e7b32b34e..f62790513322 100644
--- a/drivers/mmc/host/ricoh_mmc.c
+++ b/drivers/mmc/host/ricoh_mmc.c
@@ -196,7 +196,7 @@ static void __devexit ricoh_mmc_remove(struct pci_dev *pdev)
196 pci_set_drvdata(pdev, NULL); 196 pci_set_drvdata(pdev, NULL);
197} 197}
198 198
199static int ricoh_mmc_suspend(struct pci_dev *pdev, pm_message_t state) 199static int ricoh_mmc_suspend_late(struct pci_dev *pdev, pm_message_t state)
200{ 200{
201 struct pci_dev *fw_dev = NULL; 201 struct pci_dev *fw_dev = NULL;
202 202
@@ -210,7 +210,7 @@ static int ricoh_mmc_suspend(struct pci_dev *pdev, pm_message_t state)
210 return 0; 210 return 0;
211} 211}
212 212
213static int ricoh_mmc_resume(struct pci_dev *pdev) 213static int ricoh_mmc_resume_early(struct pci_dev *pdev)
214{ 214{
215 struct pci_dev *fw_dev = NULL; 215 struct pci_dev *fw_dev = NULL;
216 216
@@ -229,8 +229,8 @@ static struct pci_driver ricoh_mmc_driver = {
229 .id_table = pci_ids, 229 .id_table = pci_ids,
230 .probe = ricoh_mmc_probe, 230 .probe = ricoh_mmc_probe,
231 .remove = __devexit_p(ricoh_mmc_remove), 231 .remove = __devexit_p(ricoh_mmc_remove),
232 .suspend = ricoh_mmc_suspend, 232 .suspend_late = ricoh_mmc_suspend_late,
233 .resume = ricoh_mmc_resume, 233 .resume_early = ricoh_mmc_resume_early,
234}; 234};
235 235
236/*****************************************************************************\ 236/*****************************************************************************\
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index fcc98a4cce3c..f4a67c65d301 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -20,7 +20,7 @@
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/dma.h> 23#include <mach/dma.h>
24 24
25#include <mach/regs-sdi.h> 25#include <mach/regs-sdi.h>
26#include <mach/regs-gpio.h> 26#include <mach/regs-gpio.h>
@@ -329,7 +329,7 @@ static void do_pio_write(struct s3cmci_host *host)
329 329
330 to_ptr = host->base + host->sdidata; 330 to_ptr = host->base + host->sdidata;
331 331
332 while ((fifo = fifo_free(host))) { 332 while ((fifo = fifo_free(host)) > 3) {
333 if (!host->pio_bytes) { 333 if (!host->pio_bytes) {
334 res = get_data_buffer(host, &host->pio_bytes, 334 res = get_data_buffer(host, &host->pio_bytes,
335 &host->pio_ptr); 335 &host->pio_ptr);
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index f07255cb17ee..406da9a8d453 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -107,6 +107,7 @@ static const struct sdhci_pci_fixes sdhci_ene_714 = {
107 107
108static const struct sdhci_pci_fixes sdhci_cafe = { 108static const struct sdhci_pci_fixes sdhci_cafe = {
109 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 109 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
110 SDHCI_QUIRK_NO_BUSY_IRQ |
110 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 111 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
111}; 112};
112 113
@@ -144,8 +145,7 @@ static int jmicron_probe(struct sdhci_pci_chip *chip)
144 SDHCI_QUIRK_32BIT_DMA_SIZE | 145 SDHCI_QUIRK_32BIT_DMA_SIZE |
145 SDHCI_QUIRK_32BIT_ADMA_SIZE | 146 SDHCI_QUIRK_32BIT_ADMA_SIZE |
146 SDHCI_QUIRK_RESET_AFTER_REQUEST | 147 SDHCI_QUIRK_RESET_AFTER_REQUEST |
147 SDHCI_QUIRK_BROKEN_SMALL_PIO | 148 SDHCI_QUIRK_BROKEN_SMALL_PIO;
148 SDHCI_QUIRK_FORCE_HIGHSPEED;
149 } 149 }
150 150
151 /* 151 /*
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6b2d1f99af67..accb592764ed 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1291,8 +1291,11 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1291 if (host->cmd->data) 1291 if (host->cmd->data)
1292 DBG("Cannot wait for busy signal when also " 1292 DBG("Cannot wait for busy signal when also "
1293 "doing a data transfer"); 1293 "doing a data transfer");
1294 else 1294 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1295 return; 1295 return;
1296
1297 /* The controller does not support the end-of-busy IRQ,
1298 * fall through and take the SDHCI_INT_RESPONSE */
1296 } 1299 }
1297 1300
1298 if (intmask & SDHCI_INT_RESPONSE) 1301 if (intmask & SDHCI_INT_RESPONSE)
@@ -1636,8 +1639,7 @@ int sdhci_add_host(struct sdhci_host *host)
1636 mmc->f_max = host->max_clk; 1639 mmc->f_max = host->max_clk;
1637 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1640 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1638 1641
1639 if ((caps & SDHCI_CAN_DO_HISPD) || 1642 if (caps & SDHCI_CAN_DO_HISPD)
1640 (host->quirks & SDHCI_QUIRK_FORCE_HIGHSPEED))
1641 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1643 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1642 1644
1643 mmc->ocr_avail = 0; 1645 mmc->ocr_avail = 0;
@@ -1723,7 +1725,9 @@ int sdhci_add_host(struct sdhci_host *host)
1723#endif 1725#endif
1724 1726
1725#ifdef SDHCI_USE_LEDS_CLASS 1727#ifdef SDHCI_USE_LEDS_CLASS
1726 host->led.name = mmc_hostname(mmc); 1728 snprintf(host->led_name, sizeof(host->led_name),
1729 "%s::", mmc_hostname(mmc));
1730 host->led.name = host->led_name;
1727 host->led.brightness = LED_OFF; 1731 host->led.brightness = LED_OFF;
1728 host->led.default_trigger = mmc_hostname(mmc); 1732 host->led.default_trigger = mmc_hostname(mmc);
1729 host->led.brightness_set = sdhci_led_control; 1733 host->led.brightness_set = sdhci_led_control;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3efba2363941..43c37c68d07a 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -208,8 +208,8 @@ struct sdhci_host {
208#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 208#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
209/* Controller has an issue with buffer bits for small transfers */ 209/* Controller has an issue with buffer bits for small transfers */
210#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 210#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
211/* Controller supports high speed but doesn't have the caps bit set */ 211/* Controller does not provide transfer-complete interrupt when not busy */
212#define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14) 212#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
213 213
214 int irq; /* Device IRQ */ 214 int irq; /* Device IRQ */
215 void __iomem * ioaddr; /* Mapped address */ 215 void __iomem * ioaddr; /* Mapped address */
@@ -222,6 +222,7 @@ struct sdhci_host {
222 222
223#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 223#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
224 struct led_classdev led; /* LED control */ 224 struct led_classdev led; /* LED control */
225 char led_name[32];
225#endif 226#endif
226 227
227 spinlock_t lock; /* Mutex */ 228 spinlock_t lock; /* Mutex */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 01:49:52 -0500