2 files changed, 45 insertions, 2 deletions

diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 65210fca37ed..d89475d36988 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -114,6 +114,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
         unsigned int nob = data->blocks;
         unsigned long long clks;
         unsigned int timeout;
+        bool dalgn = 0;
         u32 dcmd;
         int i;
 
@@ -152,6 +153,9 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
                 host->sg_cpu[i].dcmd = dcmd | length;
                 if (length & 31 && !(data->flags & MMC_DATA_READ))
                         host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
+                /* Not aligned to 8-byte boundary? */
+                if (sg_dma_address(&data->sg[i]) & 0x7)
+                        dalgn = 1;
                 if (data->flags & MMC_DATA_READ) {
                         host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
                         host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
@@ -165,6 +169,15 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
         host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
         wmb();
 
+        /*
+         * The PXA27x DMA controller encounters overhead when working with
+         * unaligned (to 8-byte boundaries) data, so switch on byte alignment
+         * mode only if we have unaligned data.
+         */
+        if (dalgn)
+                DALGN |= (1 << host->dma);
+        else
+                DALGN &= (1 << host->dma);
         DDADR(host->dma) = host->sg_dma;
         DCSR(host->dma) = DCSR_RUN;
 }
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 07c2048b230b..b413aa6c246b 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -55,6 +55,10 @@ static unsigned int debug_quirks = 0;
 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<7)
 /* Controller needs to be reset after each request to stay stable */
 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<8)
+/* Controller needs voltage and power writes to happen separately */
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<9)
+/* Controller has an off-by-one issue with timeout value */
+#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL                (1<<10)
 
 static const struct pci_device_id pci_ids[] __devinitdata = {
         {
@@ -115,7 +119,8 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
                 .subvendor      = PCI_ANY_ID,
                 .subdevice      = PCI_ANY_ID,
                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
-                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
+                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
+                                  SDHCI_QUIRK_BROKEN_DMA,
         },
 
         {
@@ -124,7 +129,17 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
                 .subvendor      = PCI_ANY_ID,
                 .subdevice      = PCI_ANY_ID,
                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
-                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
+                                  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
+                                  SDHCI_QUIRK_BROKEN_DMA,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_MARVELL,
+                .device         = PCI_DEVICE_ID_MARVELL_CAFE_SD,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+                                  SDHCI_QUIRK_INCR_TIMEOUT_CONTROL,
         },
 
         {
@@ -469,6 +484,13 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
                         break;
         }
 
+        /*
+         * Compensate for an off-by-one error in the CaFe hardware; otherwise,
+         * a too-small count gives us interrupt timeouts.
+         */
+        if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
+                count++;
+
         if (count >= 0xF) {
                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
                         mmc_hostname(host->mmc));
@@ -774,6 +796,14 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
                 BUG();
         }
 
+        /*
+         * At least the CaFe chip gets confused if we set the voltage
+         * and set turn on power at the same time, so set the voltage first.
+         */
+        if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
+                writeb(pwr & ~SDHCI_POWER_ON,
+                                host->ioaddr + SDHCI_POWER_CONTROL);
+
         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 
 out: