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-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/sdhci-pci-o2micro.c321
-rw-r--r--drivers/mmc/host/sdhci-pci-o2micro.h72
-rw-r--r--drivers/mmc/host/sdhci-pci.c105
4 files changed, 439 insertions, 60 deletions
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index c41d0c364509..5dd3de9b2677 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
9obj-$(CONFIG_MMC_SDHCI) += sdhci.o 9obj-$(CONFIG_MMC_SDHCI) += sdhci.o
10obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o 10obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
11obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o 11obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o
12obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-o2micro.o
12obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o 13obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
13obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o 14obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
14obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o 15obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
new file mode 100644
index 000000000000..f49666bcc52a
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -0,0 +1,321 @@
1/*
2 * Copyright (C) 2013 BayHub Technology Ltd.
3 *
4 * Authors: Peter Guo <peter.guo@bayhubtech.com>
5 * Adam Lee <adam.lee@canonical.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/pci.h>
19
20#include "sdhci.h"
21#include "sdhci-pci.h"
22#include "sdhci-pci-o2micro.h"
23
24void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
25{
26 u32 scratch_32;
27 int ret;
28 /* Improve write performance for SD3.0 */
29 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
30 if (ret)
31 return;
32 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
33 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
34
35 /* Enable Link abnormal reset generating Reset */
36 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
37 if (ret)
38 return;
39 scratch_32 &= ~((1 << 19) | (1 << 11));
40 scratch_32 |= (1 << 10);
41 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
42
43 /* set card power over current protection */
44 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
45 if (ret)
46 return;
47 scratch_32 |= (1 << 4);
48 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
49
50 /* adjust the output delay for SD mode */
51 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
52
53 /* Set the output voltage setting of Aux 1.2v LDO */
54 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
55 if (ret)
56 return;
57 scratch_32 &= ~(3 << 12);
58 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
59
60 /* Set Max power supply capability of SD host */
61 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
62 if (ret)
63 return;
64 scratch_32 &= ~(0x01FE);
65 scratch_32 |= 0x00CC;
66 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
67 /* Set DLL Tuning Window */
68 ret = pci_read_config_dword(chip->pdev,
69 O2_SD_TUNING_CTRL, &scratch_32);
70 if (ret)
71 return;
72 scratch_32 &= ~(0x000000FF);
73 scratch_32 |= 0x00000066;
74 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
75
76 /* Set UHS2 T_EIDLE */
77 ret = pci_read_config_dword(chip->pdev,
78 O2_SD_UHS2_L1_CTRL, &scratch_32);
79 if (ret)
80 return;
81 scratch_32 &= ~(0x000000FC);
82 scratch_32 |= 0x00000084;
83 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
84
85 /* Set UHS2 Termination */
86 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
87 if (ret)
88 return;
89 scratch_32 &= ~((1 << 21) | (1 << 30));
90
91 /* Set RTD3 function disabled */
92 scratch_32 |= ((1 << 29) | (1 << 28));
93 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
94
95 /* Set L1 Entrance Timer */
96 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
97 if (ret)
98 return;
99 scratch_32 &= ~(0xf0000000);
100 scratch_32 |= 0x30000000;
101 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
102
103 ret = pci_read_config_dword(chip->pdev,
104 O2_SD_MISC_CTRL4, &scratch_32);
105 if (ret)
106 return;
107 scratch_32 &= ~(0x000f0000);
108 scratch_32 |= 0x00080000;
109 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
110}
111EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
112
113int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
114{
115 struct sdhci_pci_chip *chip;
116 struct sdhci_host *host;
117 u32 reg;
118
119 chip = slot->chip;
120 host = slot->host;
121 switch (chip->pdev->device) {
122 case PCI_DEVICE_ID_O2_SDS0:
123 case PCI_DEVICE_ID_O2_SEABIRD0:
124 case PCI_DEVICE_ID_O2_SEABIRD1:
125 case PCI_DEVICE_ID_O2_SDS1:
126 case PCI_DEVICE_ID_O2_FUJIN2:
127 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
128 if (reg & 0x1)
129 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
130
131 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
132 break;
133 /* set dll watch dog timer */
134 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
135 reg |= (1 << 12);
136 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
137
138 break;
139 default:
140 break;
141 }
142
143 return 0;
144}
145EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
146
147int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
148{
149 int ret;
150 u8 scratch;
151 u32 scratch_32;
152
153 switch (chip->pdev->device) {
154 case PCI_DEVICE_ID_O2_8220:
155 case PCI_DEVICE_ID_O2_8221:
156 case PCI_DEVICE_ID_O2_8320:
157 case PCI_DEVICE_ID_O2_8321:
158 /* This extra setup is required due to broken ADMA. */
159 ret = pci_read_config_byte(chip->pdev,
160 O2_SD_LOCK_WP, &scratch);
161 if (ret)
162 return ret;
163 scratch &= 0x7f;
164 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
165
166 /* Set Multi 3 to VCC3V# */
167 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
168
169 /* Disable CLK_REQ# support after media DET */
170 ret = pci_read_config_byte(chip->pdev,
171 O2_SD_CLKREQ, &scratch);
172 if (ret)
173 return ret;
174 scratch |= 0x20;
175 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
176
177 /* Choose capabilities, enable SDMA. We have to write 0x01
178 * to the capabilities register first to unlock it.
179 */
180 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
181 if (ret)
182 return ret;
183 scratch |= 0x01;
184 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
185 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
186
187 /* Disable ADMA1/2 */
188 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
189 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
190
191 /* Disable the infinite transfer mode */
192 ret = pci_read_config_byte(chip->pdev,
193 O2_SD_INF_MOD, &scratch);
194 if (ret)
195 return ret;
196 scratch |= 0x08;
197 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
198
199 /* Lock WP */
200 ret = pci_read_config_byte(chip->pdev,
201 O2_SD_LOCK_WP, &scratch);
202 if (ret)
203 return ret;
204 scratch |= 0x80;
205 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
206 break;
207 case PCI_DEVICE_ID_O2_SDS0:
208 case PCI_DEVICE_ID_O2_SDS1:
209 case PCI_DEVICE_ID_O2_FUJIN2:
210 /* UnLock WP */
211 ret = pci_read_config_byte(chip->pdev,
212 O2_SD_LOCK_WP, &scratch);
213 if (ret)
214 return ret;
215
216 scratch &= 0x7f;
217 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
218
219 /* Set timeout CLK */
220 ret = pci_read_config_dword(chip->pdev,
221 O2_SD_CLK_SETTING, &scratch_32);
222 if (ret)
223 return ret;
224
225 scratch_32 &= ~(0xFF00);
226 scratch_32 |= 0x07E0C800;
227 pci_write_config_dword(chip->pdev,
228 O2_SD_CLK_SETTING, scratch_32);
229
230 ret = pci_read_config_dword(chip->pdev,
231 O2_SD_CLKREQ, &scratch_32);
232 if (ret)
233 return ret;
234 scratch_32 |= 0x3;
235 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
236
237 ret = pci_read_config_dword(chip->pdev,
238 O2_SD_PLL_SETTING, &scratch_32);
239 if (ret)
240 return ret;
241
242 scratch_32 &= ~(0x1F3F070E);
243 scratch_32 |= 0x18270106;
244 pci_write_config_dword(chip->pdev,
245 O2_SD_PLL_SETTING, scratch_32);
246
247 /* Disable UHS1 funciton */
248 ret = pci_read_config_dword(chip->pdev,
249 O2_SD_CAP_REG2, &scratch_32);
250 if (ret)
251 return ret;
252 scratch_32 &= ~(0xE0);
253 pci_write_config_dword(chip->pdev,
254 O2_SD_CAP_REG2, scratch_32);
255
256 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
257 sdhci_pci_o2_fujin2_pci_init(chip);
258
259 /* Lock WP */
260 ret = pci_read_config_byte(chip->pdev,
261 O2_SD_LOCK_WP, &scratch);
262 if (ret)
263 return ret;
264 scratch |= 0x80;
265 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
266 break;
267 case PCI_DEVICE_ID_O2_SEABIRD0:
268 case PCI_DEVICE_ID_O2_SEABIRD1:
269 /* UnLock WP */
270 ret = pci_read_config_byte(chip->pdev,
271 O2_SD_LOCK_WP, &scratch);
272 if (ret)
273 return ret;
274
275 scratch &= 0x7f;
276 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
277
278 ret = pci_read_config_dword(chip->pdev,
279 O2_SD_FUNC_REG0, &scratch_32);
280
281 if ((scratch_32 & 0xff000000) == 0x01000000) {
282 scratch_32 &= 0x0000FFFF;
283 scratch_32 |= 0x1F340000;
284
285 pci_write_config_dword(chip->pdev,
286 O2_SD_PLL_SETTING, scratch_32);
287 } else {
288 scratch_32 &= 0x0000FFFF;
289 scratch_32 |= 0x2c280000;
290
291 pci_write_config_dword(chip->pdev,
292 O2_SD_PLL_SETTING, scratch_32);
293
294 ret = pci_read_config_dword(chip->pdev,
295 O2_SD_FUNC_REG4,
296 &scratch_32);
297 scratch_32 |= (1 << 22);
298 pci_write_config_dword(chip->pdev,
299 O2_SD_FUNC_REG4, scratch_32);
300 }
301
302 /* Lock WP */
303 ret = pci_read_config_byte(chip->pdev,
304 O2_SD_LOCK_WP, &scratch);
305 if (ret)
306 return ret;
307 scratch |= 0x80;
308 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
309 break;
310 }
311
312 return 0;
313}
314EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
315
316int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
317{
318 sdhci_pci_o2_probe(chip);
319 return 0;
320}
321EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.h b/drivers/mmc/host/sdhci-pci-o2micro.h
new file mode 100644
index 000000000000..dbec4c933488
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pci-o2micro.h
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) 2013 BayHub Technology Ltd.
3 *
4 * Authors: Peter Guo <peter.guo@bayhubtech.com>
5 * Adam Lee <adam.lee@canonical.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __SDHCI_PCI_O2MICRO_H
19#define __SDHCI_PCI_O2MICRO_H
20
21#include "sdhci-pci.h"
22
23/*
24 * O2Micro device IDs
25 */
26
27#define PCI_DEVICE_ID_O2_SDS0 0x8420
28#define PCI_DEVICE_ID_O2_SDS1 0x8421
29#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
30#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
31#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
32
33/*
34 * O2Micro device registers
35 */
36
37#define O2_SD_MISC_REG5 0x64
38#define O2_SD_LD0_CTRL 0x68
39#define O2_SD_DEV_CTRL 0x88
40#define O2_SD_LOCK_WP 0xD3
41#define O2_SD_TEST_REG 0xD4
42#define O2_SD_FUNC_REG0 0xDC
43#define O2_SD_MULTI_VCC3V 0xEE
44#define O2_SD_CLKREQ 0xEC
45#define O2_SD_CAPS 0xE0
46#define O2_SD_ADMA1 0xE2
47#define O2_SD_ADMA2 0xE7
48#define O2_SD_INF_MOD 0xF1
49#define O2_SD_MISC_CTRL4 0xFC
50#define O2_SD_TUNING_CTRL 0x300
51#define O2_SD_PLL_SETTING 0x304
52#define O2_SD_CLK_SETTING 0x328
53#define O2_SD_CAP_REG2 0x330
54#define O2_SD_CAP_REG0 0x334
55#define O2_SD_UHS1_CAP_SETTING 0x33C
56#define O2_SD_DELAY_CTRL 0x350
57#define O2_SD_UHS2_L1_CTRL 0x35C
58#define O2_SD_FUNC_REG3 0x3E0
59#define O2_SD_FUNC_REG4 0x3E4
60
61#define O2_SD_VENDOR_SETTING 0x110
62#define O2_SD_VENDOR_SETTING2 0x1C8
63
64extern void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip);
65
66extern int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
67
68extern int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
69
70extern int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
71
72#endif /* __SDHCI_PCI_O2MICRO_H */
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index af446592d974..c1a7f31c66a9 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -28,6 +28,7 @@
28 28
29#include "sdhci.h" 29#include "sdhci.h"
30#include "sdhci-pci.h" 30#include "sdhci-pci.h"
31#include "sdhci-pci-o2micro.h"
31 32
32/*****************************************************************************\ 33/*****************************************************************************\
33 * * 34 * *
@@ -321,65 +322,6 @@ static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
321#define O2_SD_ADMA2 0xE7 322#define O2_SD_ADMA2 0xE7
322#define O2_SD_INF_MOD 0xF1 323#define O2_SD_INF_MOD 0xF1
323 324
324static int o2_probe(struct sdhci_pci_chip *chip)
325{
326 int ret;
327 u8 scratch;
328
329 switch (chip->pdev->device) {
330 case PCI_DEVICE_ID_O2_8220:
331 case PCI_DEVICE_ID_O2_8221:
332 case PCI_DEVICE_ID_O2_8320:
333 case PCI_DEVICE_ID_O2_8321:
334 /* This extra setup is required due to broken ADMA. */
335 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
336 if (ret)
337 return ret;
338 scratch &= 0x7f;
339 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
340
341 /* Set Multi 3 to VCC3V# */
342 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
343
344 /* Disable CLK_REQ# support after media DET */
345 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
346 if (ret)
347 return ret;
348 scratch |= 0x20;
349 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
350
351 /* Choose capabilities, enable SDMA. We have to write 0x01
352 * to the capabilities register first to unlock it.
353 */
354 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
355 if (ret)
356 return ret;
357 scratch |= 0x01;
358 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
359 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
360
361 /* Disable ADMA1/2 */
362 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
363 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
364
365 /* Disable the infinite transfer mode */
366 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
367 if (ret)
368 return ret;
369 scratch |= 0x08;
370 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
371
372 /* Lock WP */
373 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
374 if (ret)
375 return ret;
376 scratch |= 0x80;
377 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
378 }
379
380 return 0;
381}
382
383static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 325static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
384{ 326{
385 u8 scratch; 327 u8 scratch;
@@ -570,7 +512,10 @@ static int jmicron_resume(struct sdhci_pci_chip *chip)
570} 512}
571 513
572static const struct sdhci_pci_fixes sdhci_o2 = { 514static const struct sdhci_pci_fixes sdhci_o2 = {
573 .probe = o2_probe, 515 .probe = sdhci_pci_o2_probe,
516 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
517 .probe_slot = sdhci_pci_o2_probe_slot,
518 .resume = sdhci_pci_o2_resume,
574}; 519};
575 520
576static const struct sdhci_pci_fixes sdhci_jmicron = { 521static const struct sdhci_pci_fixes sdhci_jmicron = {
@@ -983,6 +928,46 @@ static const struct pci_device_id pci_ids[] = {
983 .driver_data = (kernel_ulong_t)&sdhci_o2, 928 .driver_data = (kernel_ulong_t)&sdhci_o2,
984 }, 929 },
985 930
931 {
932 .vendor = PCI_VENDOR_ID_O2,
933 .device = PCI_DEVICE_ID_O2_FUJIN2,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .driver_data = (kernel_ulong_t)&sdhci_o2,
937 },
938
939 {
940 .vendor = PCI_VENDOR_ID_O2,
941 .device = PCI_DEVICE_ID_O2_SDS0,
942 .subvendor = PCI_ANY_ID,
943 .subdevice = PCI_ANY_ID,
944 .driver_data = (kernel_ulong_t)&sdhci_o2,
945 },
946
947 {
948 .vendor = PCI_VENDOR_ID_O2,
949 .device = PCI_DEVICE_ID_O2_SDS1,
950 .subvendor = PCI_ANY_ID,
951 .subdevice = PCI_ANY_ID,
952 .driver_data = (kernel_ulong_t)&sdhci_o2,
953 },
954
955 {
956 .vendor = PCI_VENDOR_ID_O2,
957 .device = PCI_DEVICE_ID_O2_SEABIRD0,
958 .subvendor = PCI_ANY_ID,
959 .subdevice = PCI_ANY_ID,
960 .driver_data = (kernel_ulong_t)&sdhci_o2,
961 },
962
963 {
964 .vendor = PCI_VENDOR_ID_O2,
965 .device = PCI_DEVICE_ID_O2_SEABIRD1,
966 .subvendor = PCI_ANY_ID,
967 .subdevice = PCI_ANY_ID,
968 .driver_data = (kernel_ulong_t)&sdhci_o2,
969 },
970
986 { /* Generic SD host controller */ 971 { /* Generic SD host controller */
987 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) 972 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
988 }, 973 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 05:38:18 -0500