diff options
Diffstat (limited to 'drivers/mmc/host/sdhci.h')
-rw-r--r-- | drivers/mmc/host/sdhci.h | 59 |
1 files changed, 55 insertions, 4 deletions
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 25e8bde600d1..745c42fa41ed 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h | |||
@@ -25,6 +25,7 @@ | |||
25 | */ | 25 | */ |
26 | 26 | ||
27 | #define SDHCI_DMA_ADDRESS 0x00 | 27 | #define SDHCI_DMA_ADDRESS 0x00 |
28 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS | ||
28 | 29 | ||
29 | #define SDHCI_BLOCK_SIZE 0x04 | 30 | #define SDHCI_BLOCK_SIZE 0x04 |
30 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
@@ -36,7 +37,8 @@ | |||
36 | #define SDHCI_TRANSFER_MODE 0x0C | 37 | #define SDHCI_TRANSFER_MODE 0x0C |
37 | #define SDHCI_TRNS_DMA 0x01 | 38 | #define SDHCI_TRNS_DMA 0x01 |
38 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | 39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
39 | #define SDHCI_TRNS_ACMD12 0x04 | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 | ||
40 | #define SDHCI_TRNS_READ 0x10 | 42 | #define SDHCI_TRNS_READ 0x10 |
41 | #define SDHCI_TRNS_MULTI 0x20 | 43 | #define SDHCI_TRNS_MULTI 0x20 |
42 | 44 | ||
@@ -68,8 +70,10 @@ | |||
68 | #define SDHCI_DATA_AVAILABLE 0x00000800 | 70 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
69 | #define SDHCI_CARD_PRESENT 0x00010000 | 71 | #define SDHCI_CARD_PRESENT 0x00010000 |
70 | #define SDHCI_WRITE_PROTECT 0x00080000 | 72 | #define SDHCI_WRITE_PROTECT 0x00080000 |
73 | #define SDHCI_DATA_LVL_MASK 0x00F00000 | ||
74 | #define SDHCI_DATA_LVL_SHIFT 20 | ||
71 | 75 | ||
72 | #define SDHCI_HOST_CONTROL 0x28 | 76 | #define SDHCI_HOST_CONTROL 0x28 |
73 | #define SDHCI_CTRL_LED 0x01 | 77 | #define SDHCI_CTRL_LED 0x01 |
74 | #define SDHCI_CTRL_4BITBUS 0x02 | 78 | #define SDHCI_CTRL_4BITBUS 0x02 |
75 | #define SDHCI_CTRL_HISPD 0x04 | 79 | #define SDHCI_CTRL_HISPD 0x04 |
@@ -99,6 +103,7 @@ | |||
99 | #define SDHCI_DIV_MASK 0xFF | 103 | #define SDHCI_DIV_MASK 0xFF |
100 | #define SDHCI_DIV_MASK_LEN 8 | 104 | #define SDHCI_DIV_MASK_LEN 8 |
101 | #define SDHCI_DIV_HI_MASK 0x300 | 105 | #define SDHCI_DIV_HI_MASK 0x300 |
106 | #define SDHCI_PROG_CLOCK_MODE 0x0020 | ||
102 | #define SDHCI_CLOCK_CARD_EN 0x0004 | 107 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
103 | #define SDHCI_CLOCK_INT_STABLE 0x0002 | 108 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
104 | #define SDHCI_CLOCK_INT_EN 0x0001 | 109 | #define SDHCI_CLOCK_INT_EN 0x0001 |
@@ -146,7 +151,22 @@ | |||
146 | 151 | ||
147 | #define SDHCI_ACMD12_ERR 0x3C | 152 | #define SDHCI_ACMD12_ERR 0x3C |
148 | 153 | ||
149 | /* 3E-3F reserved */ | 154 | #define SDHCI_HOST_CONTROL2 0x3E |
155 | #define SDHCI_CTRL_UHS_MASK 0x0007 | ||
156 | #define SDHCI_CTRL_UHS_SDR12 0x0000 | ||
157 | #define SDHCI_CTRL_UHS_SDR25 0x0001 | ||
158 | #define SDHCI_CTRL_UHS_SDR50 0x0002 | ||
159 | #define SDHCI_CTRL_UHS_SDR104 0x0003 | ||
160 | #define SDHCI_CTRL_UHS_DDR50 0x0004 | ||
161 | #define SDHCI_CTRL_VDD_180 0x0008 | ||
162 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 | ||
163 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 | ||
164 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 | ||
165 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 | ||
166 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 | ||
167 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 | ||
168 | #define SDHCI_CTRL_TUNED_CLK 0x0080 | ||
169 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 | ||
150 | 170 | ||
151 | #define SDHCI_CAPABILITIES 0x40 | 171 | #define SDHCI_CAPABILITIES 0x40 |
152 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F | 172 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
@@ -167,9 +187,30 @@ | |||
167 | #define SDHCI_CAN_VDD_180 0x04000000 | 187 | #define SDHCI_CAN_VDD_180 0x04000000 |
168 | #define SDHCI_CAN_64BIT 0x10000000 | 188 | #define SDHCI_CAN_64BIT 0x10000000 |
169 | 189 | ||
190 | #define SDHCI_SUPPORT_SDR50 0x00000001 | ||
191 | #define SDHCI_SUPPORT_SDR104 0x00000002 | ||
192 | #define SDHCI_SUPPORT_DDR50 0x00000004 | ||
193 | #define SDHCI_DRIVER_TYPE_A 0x00000010 | ||
194 | #define SDHCI_DRIVER_TYPE_C 0x00000020 | ||
195 | #define SDHCI_DRIVER_TYPE_D 0x00000040 | ||
196 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 | ||
197 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 | ||
198 | #define SDHCI_USE_SDR50_TUNING 0x00002000 | ||
199 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 | ||
200 | #define SDHCI_RETUNING_MODE_SHIFT 14 | ||
201 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 | ||
202 | #define SDHCI_CLOCK_MUL_SHIFT 16 | ||
203 | |||
170 | #define SDHCI_CAPABILITIES_1 0x44 | 204 | #define SDHCI_CAPABILITIES_1 0x44 |
171 | 205 | ||
172 | #define SDHCI_MAX_CURRENT 0x48 | 206 | #define SDHCI_MAX_CURRENT 0x48 |
207 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF | ||
208 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 | ||
209 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 | ||
210 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 | ||
211 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 | ||
212 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 | ||
213 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 | ||
173 | 214 | ||
174 | /* 4C-4F reserved for more max current */ | 215 | /* 4C-4F reserved for more max current */ |
175 | 216 | ||
@@ -202,6 +243,12 @@ | |||
202 | #define SDHCI_MAX_DIV_SPEC_200 256 | 243 | #define SDHCI_MAX_DIV_SPEC_200 256 |
203 | #define SDHCI_MAX_DIV_SPEC_300 2046 | 244 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
204 | 245 | ||
246 | /* | ||
247 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. | ||
248 | */ | ||
249 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) | ||
250 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) | ||
251 | |||
205 | struct sdhci_ops { | 252 | struct sdhci_ops { |
206 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS | 253 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
207 | u32 (*read_l)(struct sdhci_host *host, int reg); | 254 | u32 (*read_l)(struct sdhci_host *host, int reg); |
@@ -223,6 +270,10 @@ struct sdhci_ops { | |||
223 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, | 270 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
224 | u8 power_mode); | 271 | u8 power_mode); |
225 | unsigned int (*get_ro)(struct sdhci_host *host); | 272 | unsigned int (*get_ro)(struct sdhci_host *host); |
273 | void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); | ||
274 | void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); | ||
275 | int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); | ||
276 | |||
226 | }; | 277 | }; |
227 | 278 | ||
228 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS | 279 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |