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path: root/drivers/mmc/host/rtsx_pci_sdmmc.c
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Diffstat (limited to 'drivers/mmc/host/rtsx_pci_sdmmc.c')
-rw-r--r--drivers/mmc/host/rtsx_pci_sdmmc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
index 0b9ded13a3ae..0d519649b575 100644
--- a/drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -236,6 +236,9 @@ static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
236 case MMC_RSP_R1: 236 case MMC_RSP_R1:
237 rsp_type = SD_RSP_TYPE_R1; 237 rsp_type = SD_RSP_TYPE_R1;
238 break; 238 break;
239 case MMC_RSP_R1 & ~MMC_RSP_CRC:
240 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
241 break;
239 case MMC_RSP_R1B: 242 case MMC_RSP_R1B:
240 rsp_type = SD_RSP_TYPE_R1b; 243 rsp_type = SD_RSP_TYPE_R1b;
241 break; 244 break;
@@ -816,6 +819,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
816 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
817 break; 820 break;
818 821
822 case MMC_TIMING_MMC_DDR52:
819 case MMC_TIMING_UHS_DDR50: 823 case MMC_TIMING_UHS_DDR50:
820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 824 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
821 0x0C | SD_ASYNC_FIFO_NOT_RST, 825 0x0C | SD_ASYNC_FIFO_NOT_RST,
@@ -896,6 +900,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
896 host->vpclk = true; 900 host->vpclk = true;
897 host->double_clk = false; 901 host->double_clk = false;
898 break; 902 break;
903 case MMC_TIMING_MMC_DDR52:
899 case MMC_TIMING_UHS_DDR50: 904 case MMC_TIMING_UHS_DDR50:
900 case MMC_TIMING_UHS_SDR25: 905 case MMC_TIMING_UHS_SDR25:
901 host->ssc_depth = RTSX_SSC_DEPTH_1M; 906 host->ssc_depth = RTSX_SSC_DEPTH_1M;