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path: root/drivers/mmc/host/pxamci.c
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Diffstat (limited to 'drivers/mmc/host/pxamci.c')
-rw-r--r--drivers/mmc/host/pxamci.c616
1 files changed, 616 insertions, 0 deletions
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
new file mode 100644
index 000000000000..a98ff98fa567
--- /dev/null
+++ b/drivers/mmc/host/pxamci.c
@@ -0,0 +1,616 @@
1/*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/mmc/host.h>
27
28#include <asm/dma.h>
29#include <asm/io.h>
30#include <asm/scatterlist.h>
31#include <asm/sizes.h>
32
33#include <asm/arch/pxa-regs.h>
34#include <asm/arch/mmc.h>
35
36#include "pxamci.h"
37
38#define DRIVER_NAME "pxa2xx-mci"
39
40#define NR_SG 1
41
42struct pxamci_host {
43 struct mmc_host *mmc;
44 spinlock_t lock;
45 struct resource *res;
46 void __iomem *base;
47 int irq;
48 int dma;
49 unsigned int clkrt;
50 unsigned int cmdat;
51 unsigned int imask;
52 unsigned int power_mode;
53 struct pxamci_platform_data *pdata;
54
55 struct mmc_request *mrq;
56 struct mmc_command *cmd;
57 struct mmc_data *data;
58
59 dma_addr_t sg_dma;
60 struct pxa_dma_desc *sg_cpu;
61 unsigned int dma_len;
62
63 unsigned int dma_dir;
64};
65
66static void pxamci_stop_clock(struct pxamci_host *host)
67{
68 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
69 unsigned long timeout = 10000;
70 unsigned int v;
71
72 writel(STOP_CLOCK, host->base + MMC_STRPCL);
73
74 do {
75 v = readl(host->base + MMC_STAT);
76 if (!(v & STAT_CLK_EN))
77 break;
78 udelay(1);
79 } while (timeout--);
80
81 if (v & STAT_CLK_EN)
82 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
83 }
84}
85
86static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
87{
88 unsigned long flags;
89
90 spin_lock_irqsave(&host->lock, flags);
91 host->imask &= ~mask;
92 writel(host->imask, host->base + MMC_I_MASK);
93 spin_unlock_irqrestore(&host->lock, flags);
94}
95
96static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&host->lock, flags);
101 host->imask |= mask;
102 writel(host->imask, host->base + MMC_I_MASK);
103 spin_unlock_irqrestore(&host->lock, flags);
104}
105
106static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
107{
108 unsigned int nob = data->blocks;
109 unsigned long long clks;
110 unsigned int timeout;
111 u32 dcmd;
112 int i;
113
114 host->data = data;
115
116 if (data->flags & MMC_DATA_STREAM)
117 nob = 0xffff;
118
119 writel(nob, host->base + MMC_NOB);
120 writel(data->blksz, host->base + MMC_BLKLEN);
121
122 clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
123 do_div(clks, 1000000000UL);
124 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
125 writel((timeout + 255) / 256, host->base + MMC_RDTO);
126
127 if (data->flags & MMC_DATA_READ) {
128 host->dma_dir = DMA_FROM_DEVICE;
129 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
130 DRCMRTXMMC = 0;
131 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
132 } else {
133 host->dma_dir = DMA_TO_DEVICE;
134 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
135 DRCMRRXMMC = 0;
136 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
137 }
138
139 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
140
141 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
142 host->dma_dir);
143
144 for (i = 0; i < host->dma_len; i++) {
145 if (data->flags & MMC_DATA_READ) {
146 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
147 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
148 } else {
149 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
150 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
151 }
152 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
153 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
154 sizeof(struct pxa_dma_desc);
155 }
156 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
157 wmb();
158
159 DDADR(host->dma) = host->sg_dma;
160 DCSR(host->dma) = DCSR_RUN;
161}
162
163static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
164{
165 WARN_ON(host->cmd != NULL);
166 host->cmd = cmd;
167
168 if (cmd->flags & MMC_RSP_BUSY)
169 cmdat |= CMDAT_BUSY;
170
171#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
172 switch (RSP_TYPE(mmc_resp_type(cmd))) {
173 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
174 cmdat |= CMDAT_RESP_SHORT;
175 break;
176 case RSP_TYPE(MMC_RSP_R3):
177 cmdat |= CMDAT_RESP_R3;
178 break;
179 case RSP_TYPE(MMC_RSP_R2):
180 cmdat |= CMDAT_RESP_R2;
181 break;
182 default:
183 break;
184 }
185
186 writel(cmd->opcode, host->base + MMC_CMD);
187 writel(cmd->arg >> 16, host->base + MMC_ARGH);
188 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
189 writel(cmdat, host->base + MMC_CMDAT);
190 writel(host->clkrt, host->base + MMC_CLKRT);
191
192 writel(START_CLOCK, host->base + MMC_STRPCL);
193
194 pxamci_enable_irq(host, END_CMD_RES);
195}
196
197static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
198{
199 host->mrq = NULL;
200 host->cmd = NULL;
201 host->data = NULL;
202 mmc_request_done(host->mmc, mrq);
203}
204
205static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
206{
207 struct mmc_command *cmd = host->cmd;
208 int i;
209 u32 v;
210
211 if (!cmd)
212 return 0;
213
214 host->cmd = NULL;
215
216 /*
217 * Did I mention this is Sick. We always need to
218 * discard the upper 8 bits of the first 16-bit word.
219 */
220 v = readl(host->base + MMC_RES) & 0xffff;
221 for (i = 0; i < 4; i++) {
222 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
223 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
224 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
225 v = w2;
226 }
227
228 if (stat & STAT_TIME_OUT_RESPONSE) {
229 cmd->error = MMC_ERR_TIMEOUT;
230 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
231#ifdef CONFIG_PXA27x
232 /*
233 * workaround for erratum #42:
234 * Intel PXA27x Family Processor Specification Update Rev 001
235 */
236 if (cmd->opcode == MMC_ALL_SEND_CID ||
237 cmd->opcode == MMC_SEND_CSD ||
238 cmd->opcode == MMC_SEND_CID) {
239 /* a bogus CRC error can appear if the msb of
240 the 15 byte response is a one */
241 if ((cmd->resp[0] & 0x80000000) == 0)
242 cmd->error = MMC_ERR_BADCRC;
243 } else {
244 pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
245 }
246#else
247 cmd->error = MMC_ERR_BADCRC;
248#endif
249 }
250
251 pxamci_disable_irq(host, END_CMD_RES);
252 if (host->data && cmd->error == MMC_ERR_NONE) {
253 pxamci_enable_irq(host, DATA_TRAN_DONE);
254 } else {
255 pxamci_finish_request(host, host->mrq);
256 }
257
258 return 1;
259}
260
261static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
262{
263 struct mmc_data *data = host->data;
264
265 if (!data)
266 return 0;
267
268 DCSR(host->dma) = 0;
269 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
270 host->dma_dir);
271
272 if (stat & STAT_READ_TIME_OUT)
273 data->error = MMC_ERR_TIMEOUT;
274 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
275 data->error = MMC_ERR_BADCRC;
276
277 /*
278 * There appears to be a hardware design bug here. There seems to
279 * be no way to find out how much data was transferred to the card.
280 * This means that if there was an error on any block, we mark all
281 * data blocks as being in error.
282 */
283 if (data->error == MMC_ERR_NONE)
284 data->bytes_xfered = data->blocks * data->blksz;
285 else
286 data->bytes_xfered = 0;
287
288 pxamci_disable_irq(host, DATA_TRAN_DONE);
289
290 host->data = NULL;
291 if (host->mrq->stop) {
292 pxamci_stop_clock(host);
293 pxamci_start_cmd(host, host->mrq->stop, 0);
294 } else {
295 pxamci_finish_request(host, host->mrq);
296 }
297
298 return 1;
299}
300
301static irqreturn_t pxamci_irq(int irq, void *devid)
302{
303 struct pxamci_host *host = devid;
304 unsigned int ireg;
305 int handled = 0;
306
307 ireg = readl(host->base + MMC_I_REG);
308
309 if (ireg) {
310 unsigned stat = readl(host->base + MMC_STAT);
311
312 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
313
314 if (ireg & END_CMD_RES)
315 handled |= pxamci_cmd_done(host, stat);
316 if (ireg & DATA_TRAN_DONE)
317 handled |= pxamci_data_done(host, stat);
318 }
319
320 return IRQ_RETVAL(handled);
321}
322
323static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
324{
325 struct pxamci_host *host = mmc_priv(mmc);
326 unsigned int cmdat;
327
328 WARN_ON(host->mrq != NULL);
329
330 host->mrq = mrq;
331
332 pxamci_stop_clock(host);
333
334 cmdat = host->cmdat;
335 host->cmdat &= ~CMDAT_INIT;
336
337 if (mrq->data) {
338 pxamci_setup_data(host, mrq->data);
339
340 cmdat &= ~CMDAT_BUSY;
341 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
342 if (mrq->data->flags & MMC_DATA_WRITE)
343 cmdat |= CMDAT_WRITE;
344
345 if (mrq->data->flags & MMC_DATA_STREAM)
346 cmdat |= CMDAT_STREAM;
347 }
348
349 pxamci_start_cmd(host, mrq->cmd, cmdat);
350}
351
352static int pxamci_get_ro(struct mmc_host *mmc)
353{
354 struct pxamci_host *host = mmc_priv(mmc);
355
356 if (host->pdata && host->pdata->get_ro)
357 return host->pdata->get_ro(mmc_dev(mmc));
358 /* Host doesn't support read only detection so assume writeable */
359 return 0;
360}
361
362static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
363{
364 struct pxamci_host *host = mmc_priv(mmc);
365
366 if (ios->clock) {
367 unsigned int clk = CLOCKRATE / ios->clock;
368 if (CLOCKRATE / clk > ios->clock)
369 clk <<= 1;
370 host->clkrt = fls(clk) - 1;
371 pxa_set_cken(CKEN12_MMC, 1);
372
373 /*
374 * we write clkrt on the next command
375 */
376 } else {
377 pxamci_stop_clock(host);
378 pxa_set_cken(CKEN12_MMC, 0);
379 }
380
381 if (host->power_mode != ios->power_mode) {
382 host->power_mode = ios->power_mode;
383
384 if (host->pdata && host->pdata->setpower)
385 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
386
387 if (ios->power_mode == MMC_POWER_ON)
388 host->cmdat |= CMDAT_INIT;
389 }
390
391 pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
392 host->clkrt, host->cmdat);
393}
394
395static const struct mmc_host_ops pxamci_ops = {
396 .request = pxamci_request,
397 .get_ro = pxamci_get_ro,
398 .set_ios = pxamci_set_ios,
399};
400
401static void pxamci_dma_irq(int dma, void *devid)
402{
403 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
404 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
405}
406
407static irqreturn_t pxamci_detect_irq(int irq, void *devid)
408{
409 struct pxamci_host *host = mmc_priv(devid);
410
411 mmc_detect_change(devid, host->pdata->detect_delay);
412 return IRQ_HANDLED;
413}
414
415static int pxamci_probe(struct platform_device *pdev)
416{
417 struct mmc_host *mmc;
418 struct pxamci_host *host = NULL;
419 struct resource *r;
420 int ret, irq;
421
422 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 irq = platform_get_irq(pdev, 0);
424 if (!r || irq < 0)
425 return -ENXIO;
426
427 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
428 if (!r)
429 return -EBUSY;
430
431 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
432 if (!mmc) {
433 ret = -ENOMEM;
434 goto out;
435 }
436
437 mmc->ops = &pxamci_ops;
438 mmc->f_min = CLOCKRATE_MIN;
439 mmc->f_max = CLOCKRATE_MAX;
440
441 /*
442 * We can do SG-DMA, but we don't because we never know how much
443 * data we successfully wrote to the card.
444 */
445 mmc->max_phys_segs = NR_SG;
446
447 /*
448 * Our hardware DMA can handle a maximum of one page per SG entry.
449 */
450 mmc->max_seg_size = PAGE_SIZE;
451
452 /*
453 * Block length register is 10 bits.
454 */
455 mmc->max_blk_size = 1023;
456
457 /*
458 * Block count register is 16 bits.
459 */
460 mmc->max_blk_count = 65535;
461
462 host = mmc_priv(mmc);
463 host->mmc = mmc;
464 host->dma = -1;
465 host->pdata = pdev->dev.platform_data;
466 mmc->ocr_avail = host->pdata ?
467 host->pdata->ocr_mask :
468 MMC_VDD_32_33|MMC_VDD_33_34;
469
470 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
471 if (!host->sg_cpu) {
472 ret = -ENOMEM;
473 goto out;
474 }
475
476 spin_lock_init(&host->lock);
477 host->res = r;
478 host->irq = irq;
479 host->imask = MMC_I_MASK_ALL;
480
481 host->base = ioremap(r->start, SZ_4K);
482 if (!host->base) {
483 ret = -ENOMEM;
484 goto out;
485 }
486
487 /*
488 * Ensure that the host controller is shut down, and setup
489 * with our defaults.
490 */
491 pxamci_stop_clock(host);
492 writel(0, host->base + MMC_SPI);
493 writel(64, host->base + MMC_RESTO);
494 writel(host->imask, host->base + MMC_I_MASK);
495
496 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
497 pxamci_dma_irq, host);
498 if (host->dma < 0) {
499 ret = -EBUSY;
500 goto out;
501 }
502
503 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
504 if (ret)
505 goto out;
506
507 platform_set_drvdata(pdev, mmc);
508
509 if (host->pdata && host->pdata->init)
510 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
511
512 mmc_add_host(mmc);
513
514 return 0;
515
516 out:
517 if (host) {
518 if (host->dma >= 0)
519 pxa_free_dma(host->dma);
520 if (host->base)
521 iounmap(host->base);
522 if (host->sg_cpu)
523 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
524 }
525 if (mmc)
526 mmc_free_host(mmc);
527 release_resource(r);
528 return ret;
529}
530
531static int pxamci_remove(struct platform_device *pdev)
532{
533 struct mmc_host *mmc = platform_get_drvdata(pdev);
534
535 platform_set_drvdata(pdev, NULL);
536
537 if (mmc) {
538 struct pxamci_host *host = mmc_priv(mmc);
539
540 if (host->pdata && host->pdata->exit)
541 host->pdata->exit(&pdev->dev, mmc);
542
543 mmc_remove_host(mmc);
544
545 pxamci_stop_clock(host);
546 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
547 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
548 host->base + MMC_I_MASK);
549
550 DRCMRRXMMC = 0;
551 DRCMRTXMMC = 0;
552
553 free_irq(host->irq, host);
554 pxa_free_dma(host->dma);
555 iounmap(host->base);
556 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
557
558 release_resource(host->res);
559
560 mmc_free_host(mmc);
561 }
562 return 0;
563}
564
565#ifdef CONFIG_PM
566static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
567{
568 struct mmc_host *mmc = platform_get_drvdata(dev);
569 int ret = 0;
570
571 if (mmc)
572 ret = mmc_suspend_host(mmc, state);
573
574 return ret;
575}
576
577static int pxamci_resume(struct platform_device *dev)
578{
579 struct mmc_host *mmc = platform_get_drvdata(dev);
580 int ret = 0;
581
582 if (mmc)
583 ret = mmc_resume_host(mmc);
584
585 return ret;
586}
587#else
588#define pxamci_suspend NULL
589#define pxamci_resume NULL
590#endif
591
592static struct platform_driver pxamci_driver = {
593 .probe = pxamci_probe,
594 .remove = pxamci_remove,
595 .suspend = pxamci_suspend,
596 .resume = pxamci_resume,
597 .driver = {
598 .name = DRIVER_NAME,
599 },
600};
601
602static int __init pxamci_init(void)
603{
604 return platform_driver_register(&pxamci_driver);
605}
606
607static void __exit pxamci_exit(void)
608{
609 platform_driver_unregister(&pxamci_driver);
610}
611
612module_init(pxamci_init);
613module_exit(pxamci_exit);
614
615MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
616MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-07 18:51:02 -0500