1 files changed, 27 insertions, 16 deletions

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 4526d2791f29..4693e62145a6 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -364,6 +364,7 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 {
         struct regulator *reg;
         int ret = 0;
+        int ocr_value = 0;
 
         switch (host->id) {
         case OMAP_MMC1_DEVID:
@@ -396,6 +397,17 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
                 }
         } else {
                 host->vcc = reg;
+                ocr_value = mmc_regulator_get_ocrmask(reg);
+                if (!mmc_slot(host).ocr_mask) {
+                        mmc_slot(host).ocr_mask = ocr_value;
+                } else {
+                        if (!(mmc_slot(host).ocr_mask & ocr_value)) {
+                                pr_err("MMC%d ocrmask %x is not supported\n",
+                                        host->id, mmc_slot(host).ocr_mask);
+                                mmc_slot(host).ocr_mask = 0;
+                                return -EINVAL;
+                        }
+                }
                 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
 
                 /* Allow an aux regulator */
@@ -982,6 +994,17 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
         OMAP_HSMMC_WRITE(host->base, SYSCTL,
                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 
+        /*
+         * OMAP4 ES2 and greater has an updated reset logic.
+         * Monitor a 0->1 transition first
+         */
+        if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
+                while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
+                                        && (i++ < limit))
+                        cpu_relax();
+        }
+        i = 0;
+
         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
                 (i++ < limit))
                 cpu_relax();
@@ -2003,6 +2026,8 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         if (res == NULL || irq < 0)
                 return -ENXIO;
 
+        res->start += pdata->reg_offset;
+        res->end += pdata->reg_offset;
         res = request_mem_region(res->start, res->end - res->start + 1,
                                                         pdev->name);
         if (res == NULL)
@@ -2116,23 +2141,9 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
 
-        switch (mmc_slot(host).wires) {
-        case 8:
-                mmc->caps |= MMC_CAP_8_BIT_DATA;
-                /* Fall through */
-        case 4:
+        mmc->caps |= mmc_slot(host).caps;
+        if (mmc->caps & MMC_CAP_8_BIT_DATA)
                 mmc->caps |= MMC_CAP_4_BIT_DATA;
-                break;
-        case 1:
-                /* Nothing to crib here */
-        case 0:
-                /* Assuming nothing was given by board, Core use's 1-Bit */
-                break;
-        default:
-                /* Completely unexpected.. Core goes with 1-Bit Width */
-                dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!"
-                        "using 1 instead\n", mmc_slot(host).wires);
-        }
 
         if (mmc_slot(host).nonremovable)
                 mmc->caps |= MMC_CAP_NONREMOVABLE;