diff options
Diffstat (limited to 'drivers/mmc/host/mmci.h')
| -rw-r--r-- | drivers/mmc/host/mmci.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index bb32e21c09db..2164e8c6476c 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h | |||
| @@ -86,6 +86,7 @@ | |||
| 86 | #define MCI_CMDRESPEND (1 << 6) | 86 | #define MCI_CMDRESPEND (1 << 6) |
| 87 | #define MCI_CMDSENT (1 << 7) | 87 | #define MCI_CMDSENT (1 << 7) |
| 88 | #define MCI_DATAEND (1 << 8) | 88 | #define MCI_DATAEND (1 << 8) |
| 89 | #define MCI_STARTBITERR (1 << 9) | ||
| 89 | #define MCI_DATABLOCKEND (1 << 10) | 90 | #define MCI_DATABLOCKEND (1 << 10) |
| 90 | #define MCI_CMDACTIVE (1 << 11) | 91 | #define MCI_CMDACTIVE (1 << 11) |
| 91 | #define MCI_TXACTIVE (1 << 12) | 92 | #define MCI_TXACTIVE (1 << 12) |
| @@ -112,6 +113,7 @@ | |||
| 112 | #define MCI_CMDRESPENDCLR (1 << 6) | 113 | #define MCI_CMDRESPENDCLR (1 << 6) |
| 113 | #define MCI_CMDSENTCLR (1 << 7) | 114 | #define MCI_CMDSENTCLR (1 << 7) |
| 114 | #define MCI_DATAENDCLR (1 << 8) | 115 | #define MCI_DATAENDCLR (1 << 8) |
| 116 | #define MCI_STARTBITERRCLR (1 << 9) | ||
| 115 | #define MCI_DATABLOCKENDCLR (1 << 10) | 117 | #define MCI_DATABLOCKENDCLR (1 << 10) |
| 116 | /* Extended status bits for the ST Micro variants */ | 118 | /* Extended status bits for the ST Micro variants */ |
| 117 | #define MCI_ST_SDIOITC (1 << 22) | 119 | #define MCI_ST_SDIOITC (1 << 22) |
| @@ -127,6 +129,7 @@ | |||
| 127 | #define MCI_CMDRESPENDMASK (1 << 6) | 129 | #define MCI_CMDRESPENDMASK (1 << 6) |
| 128 | #define MCI_CMDSENTMASK (1 << 7) | 130 | #define MCI_CMDSENTMASK (1 << 7) |
| 129 | #define MCI_DATAENDMASK (1 << 8) | 131 | #define MCI_DATAENDMASK (1 << 8) |
| 132 | #define MCI_STARTBITERRMASK (1 << 9) | ||
| 130 | #define MCI_DATABLOCKENDMASK (1 << 10) | 133 | #define MCI_DATABLOCKENDMASK (1 << 10) |
| 131 | #define MCI_CMDACTIVEMASK (1 << 11) | 134 | #define MCI_CMDACTIVEMASK (1 << 11) |
| 132 | #define MCI_TXACTIVEMASK (1 << 12) | 135 | #define MCI_TXACTIVEMASK (1 << 12) |
| @@ -150,7 +153,7 @@ | |||
| 150 | #define MCI_IRQENABLE \ | 153 | #define MCI_IRQENABLE \ |
| 151 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ | 154 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ |
| 152 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ | 155 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ |
| 153 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK) | 156 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) |
| 154 | 157 | ||
| 155 | /* These interrupts are directed to IRQ1 when two IRQ lines are available */ | 158 | /* These interrupts are directed to IRQ1 when two IRQ lines are available */ |
| 156 | #define MCI_IRQ1MASK \ | 159 | #define MCI_IRQ1MASK \ |