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-rw-r--r--drivers/mmc/host/mmc_spi.c1408
1 files changed, 1408 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
new file mode 100644
index 000000000000..f30327bba6f6
--- /dev/null
+++ b/drivers/mmc/host/mmc_spi.c
@@ -0,0 +1,1408 @@
1/*
2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers
3 *
4 * (C) Copyright 2005, Intec Automation,
5 * Mike Lavender (mike@steroidmicros)
6 * (C) Copyright 2006-2007, David Brownell
7 * (C) Copyright 2007, Axis Communications,
8 * Hans-Peter Nilsson (hp@axis.com)
9 * (C) Copyright 2007, ATRON electronic GmbH,
10 * Jan Nikitenko <jan.nikitenko@gmail.com>
11 *
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#include <linux/hrtimer.h>
28#include <linux/delay.h>
29#include <linux/blkdev.h>
30#include <linux/dma-mapping.h>
31#include <linux/crc7.h>
32#include <linux/crc-itu-t.h>
33
34#include <linux/mmc/host.h>
35#include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
36
37#include <linux/spi/spi.h>
38#include <linux/spi/mmc_spi.h>
39
40#include <asm/unaligned.h>
41
42
43/* NOTES:
44 *
45 * - For now, we won't try to interoperate with a real mmc/sd/sdio
46 * controller, although some of them do have hardware support for
47 * SPI protocol. The main reason for such configs would be mmc-ish
48 * cards like DataFlash, which don't support that "native" protocol.
49 *
50 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
51 * switch between driver stacks, and in any case if "native" mode
52 * is available, it will be faster and hence preferable.
53 *
54 * - MMC depends on a different chipselect management policy than the
55 * SPI interface currently supports for shared bus segments: it needs
56 * to issue multiple spi_message requests with the chipselect active,
57 * using the results of one message to decide the next one to issue.
58 *
59 * Pending updates to the programming interface, this driver expects
60 * that it not share the bus with other drivers (precluding conflicts).
61 *
62 * - We tell the controller to keep the chipselect active from the
63 * beginning of an mmc_host_ops.request until the end. So beware
64 * of SPI controller drivers that mis-handle the cs_change flag!
65 *
66 * However, many cards seem OK with chipselect flapping up/down
67 * during that time ... at least on unshared bus segments.
68 */
69
70
71/*
72 * Local protocol constants, internal to data block protocols.
73 */
74
75/* Response tokens used to ack each block written: */
76#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
77#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
78#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
79#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
80
81/* Read and write blocks start with these tokens and end with crc;
82 * on error, read tokens act like a subset of R2_SPI_* values.
83 */
84#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
85#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
86#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
87
88#define MMC_SPI_BLOCKSIZE 512
89
90
91/* These fixed timeouts come from the latest SD specs, which say to ignore
92 * the CSD values. The R1B value is for card erase (e.g. the "I forgot the
93 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
94 * reads which takes nowhere near that long. Older cards may be able to use
95 * shorter timeouts ... but why bother?
96 */
97#define readblock_timeout ktime_set(0, 100 * 1000 * 1000)
98#define writeblock_timeout ktime_set(0, 250 * 1000 * 1000)
99#define r1b_timeout ktime_set(3, 0)
100
101
102/****************************************************************************/
103
104/*
105 * Local Data Structures
106 */
107
108/* "scratch" is per-{command,block} data exchanged with the card */
109struct scratch {
110 u8 status[29];
111 u8 data_token;
112 __be16 crc_val;
113};
114
115struct mmc_spi_host {
116 struct mmc_host *mmc;
117 struct spi_device *spi;
118
119 unsigned char power_mode;
120 u16 powerup_msecs;
121
122 struct mmc_spi_platform_data *pdata;
123
124 /* for bulk data transfers */
125 struct spi_transfer token, t, crc, early_status;
126 struct spi_message m;
127
128 /* for status readback */
129 struct spi_transfer status;
130 struct spi_message readback;
131
132 /* underlying DMA-aware controller, or null */
133 struct device *dma_dev;
134
135 /* buffer used for commands and for message "overhead" */
136 struct scratch *data;
137 dma_addr_t data_dma;
138
139 /* Specs say to write ones most of the time, even when the card
140 * has no need to read its input data; and many cards won't care.
141 * This is our source of those ones.
142 */
143 void *ones;
144 dma_addr_t ones_dma;
145};
146
147
148/****************************************************************************/
149
150/*
151 * MMC-over-SPI protocol glue, used by the MMC stack interface
152 */
153
154static inline int mmc_cs_off(struct mmc_spi_host *host)
155{
156 /* chipselect will always be inactive after setup() */
157 return spi_setup(host->spi);
158}
159
160static int
161mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
162{
163 int status;
164
165 if (len > sizeof(*host->data)) {
166 WARN_ON(1);
167 return -EIO;
168 }
169
170 host->status.len = len;
171
172 if (host->dma_dev)
173 dma_sync_single_for_device(host->dma_dev,
174 host->data_dma, sizeof(*host->data),
175 DMA_FROM_DEVICE);
176
177 status = spi_sync(host->spi, &host->readback);
178 if (status == 0)
179 status = host->readback.status;
180
181 if (host->dma_dev)
182 dma_sync_single_for_cpu(host->dma_dev,
183 host->data_dma, sizeof(*host->data),
184 DMA_FROM_DEVICE);
185
186 return status;
187}
188
189static int
190mmc_spi_skip(struct mmc_spi_host *host, ktime_t timeout, unsigned n, u8 byte)
191{
192 u8 *cp = host->data->status;
193
194 timeout = ktime_add(timeout, ktime_get());
195
196 while (1) {
197 int status;
198 unsigned i;
199
200 status = mmc_spi_readbytes(host, n);
201 if (status < 0)
202 return status;
203
204 for (i = 0; i < n; i++) {
205 if (cp[i] != byte)
206 return cp[i];
207 }
208
209 /* REVISIT investigate msleep() to avoid busy-wait I/O
210 * in at least some cases.
211 */
212 if (ktime_to_ns(ktime_sub(ktime_get(), timeout)) > 0)
213 break;
214 }
215 return -ETIMEDOUT;
216}
217
218static inline int
219mmc_spi_wait_unbusy(struct mmc_spi_host *host, ktime_t timeout)
220{
221 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
222}
223
224static int mmc_spi_readtoken(struct mmc_spi_host *host)
225{
226 return mmc_spi_skip(host, readblock_timeout, 1, 0xff);
227}
228
229
230/*
231 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
232 * hosts return! The low byte holds R1_SPI bits. The next byte may hold
233 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
234 *
235 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
236 * newer cards R7 (IF_COND).
237 */
238
239static char *maptype(struct mmc_command *cmd)
240{
241 switch (mmc_spi_resp_type(cmd)) {
242 case MMC_RSP_SPI_R1: return "R1";
243 case MMC_RSP_SPI_R1B: return "R1B";
244 case MMC_RSP_SPI_R2: return "R2/R5";
245 case MMC_RSP_SPI_R3: return "R3/R4/R7";
246 default: return "?";
247 }
248}
249
250/* return zero, else negative errno after setting cmd->error */
251static int mmc_spi_response_get(struct mmc_spi_host *host,
252 struct mmc_command *cmd, int cs_on)
253{
254 u8 *cp = host->data->status;
255 u8 *end = cp + host->t.len;
256 int value = 0;
257 char tag[32];
258
259 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
260 cmd->opcode, maptype(cmd));
261
262 /* Except for data block reads, the whole response will already
263 * be stored in the scratch buffer. It's somewhere after the
264 * command and the first byte we read after it. We ignore that
265 * first byte. After STOP_TRANSMISSION command it may include
266 * two data bits, but otherwise it's all ones.
267 */
268 cp += 8;
269 while (cp < end && *cp == 0xff)
270 cp++;
271
272 /* Data block reads (R1 response types) may need more data... */
273 if (cp == end) {
274 unsigned i;
275
276 cp = host->data->status;
277
278 /* Card sends N(CR) (== 1..8) bytes of all-ones then one
279 * status byte ... and we already scanned 2 bytes.
280 *
281 * REVISIT block read paths use nasty byte-at-a-time I/O
282 * so it can always DMA directly into the target buffer.
283 * It'd probably be better to memcpy() the first chunk and
284 * avoid extra i/o calls...
285 */
286 for (i = 2; i < 9; i++) {
287 value = mmc_spi_readbytes(host, 1);
288 if (value < 0)
289 goto done;
290 if (*cp != 0xff)
291 goto checkstatus;
292 }
293 value = -ETIMEDOUT;
294 goto done;
295 }
296
297checkstatus:
298 if (*cp & 0x80) {
299 dev_dbg(&host->spi->dev, "%s: INVALID RESPONSE, %02x\n",
300 tag, *cp);
301 value = -EBADR;
302 goto done;
303 }
304
305 cmd->resp[0] = *cp++;
306 cmd->error = 0;
307
308 /* Status byte: the entire seven-bit R1 response. */
309 if (cmd->resp[0] != 0) {
310 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS
311 | R1_SPI_ILLEGAL_COMMAND)
312 & cmd->resp[0])
313 value = -EINVAL;
314 else if (R1_SPI_COM_CRC & cmd->resp[0])
315 value = -EILSEQ;
316 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
317 & cmd->resp[0])
318 value = -EIO;
319 /* else R1_SPI_IDLE, "it's resetting" */
320 }
321
322 switch (mmc_spi_resp_type(cmd)) {
323
324 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
325 * and less-common stuff like various erase operations.
326 */
327 case MMC_RSP_SPI_R1B:
328 /* maybe we read all the busy tokens already */
329 while (cp < end && *cp == 0)
330 cp++;
331 if (cp == end)
332 mmc_spi_wait_unbusy(host, r1b_timeout);
333 break;
334
335 /* SPI R2 == R1 + second status byte; SEND_STATUS
336 * SPI R5 == R1 + data byte; IO_RW_DIRECT
337 */
338 case MMC_RSP_SPI_R2:
339 cmd->resp[0] |= *cp << 8;
340 break;
341
342 /* SPI R3, R4, or R7 == R1 + 4 bytes */
343 case MMC_RSP_SPI_R3:
344 cmd->resp[1] = be32_to_cpu(get_unaligned((u32 *)cp));
345 break;
346
347 /* SPI R1 == just one status byte */
348 case MMC_RSP_SPI_R1:
349 break;
350
351 default:
352 dev_dbg(&host->spi->dev, "bad response type %04x\n",
353 mmc_spi_resp_type(cmd));
354 if (value >= 0)
355 value = -EINVAL;
356 goto done;
357 }
358
359 if (value < 0)
360 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
361 tag, cmd->resp[0], cmd->resp[1]);
362
363 /* disable chipselect on errors and some success cases */
364 if (value >= 0 && cs_on)
365 return value;
366done:
367 if (value < 0)
368 cmd->error = value;
369 mmc_cs_off(host);
370 return value;
371}
372
373/* Issue command and read its response.
374 * Returns zero on success, negative for error.
375 *
376 * On error, caller must cope with mmc core retry mechanism. That
377 * means immediate low-level resubmit, which affects the bus lock...
378 */
379static int
380mmc_spi_command_send(struct mmc_spi_host *host,
381 struct mmc_request *mrq,
382 struct mmc_command *cmd, int cs_on)
383{
384 struct scratch *data = host->data;
385 u8 *cp = data->status;
386 u32 arg = cmd->arg;
387 int status;
388 struct spi_transfer *t;
389
390 /* We can handle most commands (except block reads) in one full
391 * duplex I/O operation before either starting the next transfer
392 * (data block or command) or else deselecting the card.
393 *
394 * First, write 7 bytes:
395 * - an all-ones byte to ensure the card is ready
396 * - opcode byte (plus start and transmission bits)
397 * - four bytes of big-endian argument
398 * - crc7 (plus end bit) ... always computed, it's cheap
399 *
400 * We init the whole buffer to all-ones, which is what we need
401 * to write while we're reading (later) response data.
402 */
403 memset(cp++, 0xff, sizeof(data->status));
404
405 *cp++ = 0x40 | cmd->opcode;
406 *cp++ = (u8)(arg >> 24);
407 *cp++ = (u8)(arg >> 16);
408 *cp++ = (u8)(arg >> 8);
409 *cp++ = (u8)arg;
410 *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01;
411
412 /* Then, read up to 13 bytes (while writing all-ones):
413 * - N(CR) (== 1..8) bytes of all-ones
414 * - status byte (for all response types)
415 * - the rest of the response, either:
416 * + nothing, for R1 or R1B responses
417 * + second status byte, for R2 responses
418 * + four data bytes, for R3 and R7 responses
419 *
420 * Finally, read some more bytes ... in the nice cases we know in
421 * advance how many, and reading 1 more is always OK:
422 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
423 * - N(RC) (== 1..N) bytes of all-ones, before next command
424 * - N(WR) (== 1..N) bytes of all-ones, before data write
425 *
426 * So in those cases one full duplex I/O of at most 21 bytes will
427 * handle the whole command, leaving the card ready to receive a
428 * data block or new command. We do that whenever we can, shaving
429 * CPU and IRQ costs (especially when using DMA or FIFOs).
430 *
431 * There are two other cases, where it's not generally practical
432 * to rely on a single I/O:
433 *
434 * - R1B responses need at least N(EC) bytes of all-zeroes.
435 *
436 * In this case we can *try* to fit it into one I/O, then
437 * maybe read more data later.
438 *
439 * - Data block reads are more troublesome, since a variable
440 * number of padding bytes precede the token and data.
441 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
442 * + N(AC) (== 1..many) bytes of all-ones
443 *
444 * In this case we currently only have minimal speedups here:
445 * when N(CR) == 1 we can avoid I/O in response_get().
446 */
447 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
448 cp += 2; /* min(N(CR)) + status */
449 /* R1 */
450 } else {
451 cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */
452 if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */
453 cp++;
454 else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */
455 cp += 4;
456 else if (cmd->flags & MMC_RSP_BUSY) /* R1B */
457 cp = data->status + sizeof(data->status);
458 /* else: R1 (most commands) */
459 }
460
461 dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n",
462 cmd->opcode, maptype(cmd));
463
464 /* send command, leaving chipselect active */
465 spi_message_init(&host->m);
466
467 t = &host->t;
468 memset(t, 0, sizeof(*t));
469 t->tx_buf = t->rx_buf = data->status;
470 t->tx_dma = t->rx_dma = host->data_dma;
471 t->len = cp - data->status;
472 t->cs_change = 1;
473 spi_message_add_tail(t, &host->m);
474
475 if (host->dma_dev) {
476 host->m.is_dma_mapped = 1;
477 dma_sync_single_for_device(host->dma_dev,
478 host->data_dma, sizeof(*host->data),
479 DMA_BIDIRECTIONAL);
480 }
481 status = spi_sync(host->spi, &host->m);
482 if (status == 0)
483 status = host->m.status;
484
485 if (host->dma_dev)
486 dma_sync_single_for_cpu(host->dma_dev,
487 host->data_dma, sizeof(*host->data),
488 DMA_BIDIRECTIONAL);
489 if (status < 0) {
490 dev_dbg(&host->spi->dev, " ... write returned %d\n", status);
491 cmd->error = status;
492 return status;
493 }
494
495 /* after no-data commands and STOP_TRANSMISSION, chipselect off */
496 return mmc_spi_response_get(host, cmd, cs_on);
497}
498
499/* Build data message with up to four separate transfers. For TX, we
500 * start by writing the data token. And in most cases, we finish with
501 * a status transfer.
502 *
503 * We always provide TX data for data and CRC. The MMC/SD protocol
504 * requires us to write ones; but Linux defaults to writing zeroes;
505 * so we explicitly initialize it to all ones on RX paths.
506 *
507 * We also handle DMA mapping, so the underlying SPI controller does
508 * not need to (re)do it for each message.
509 */
510static void
511mmc_spi_setup_data_message(
512 struct mmc_spi_host *host,
513 int multiple,
514 enum dma_data_direction direction)
515{
516 struct spi_transfer *t;
517 struct scratch *scratch = host->data;
518 dma_addr_t dma = host->data_dma;
519
520 spi_message_init(&host->m);
521 if (dma)
522 host->m.is_dma_mapped = 1;
523
524 /* for reads, readblock() skips 0xff bytes before finding
525 * the token; for writes, this transfer issues that token.
526 */
527 if (direction == DMA_TO_DEVICE) {
528 t = &host->token;
529 memset(t, 0, sizeof(*t));
530 t->len = 1;
531 if (multiple)
532 scratch->data_token = SPI_TOKEN_MULTI_WRITE;
533 else
534 scratch->data_token = SPI_TOKEN_SINGLE;
535 t->tx_buf = &scratch->data_token;
536 if (dma)
537 t->tx_dma = dma + offsetof(struct scratch, data_token);
538 spi_message_add_tail(t, &host->m);
539 }
540
541 /* Body of transfer is buffer, then CRC ...
542 * either TX-only, or RX with TX-ones.
543 */
544 t = &host->t;
545 memset(t, 0, sizeof(*t));
546 t->tx_buf = host->ones;
547 t->tx_dma = host->ones_dma;
548 /* length and actual buffer info are written later */
549 spi_message_add_tail(t, &host->m);
550
551 t = &host->crc;
552 memset(t, 0, sizeof(*t));
553 t->len = 2;
554 if (direction == DMA_TO_DEVICE) {
555 /* the actual CRC may get written later */
556 t->tx_buf = &scratch->crc_val;
557 if (dma)
558 t->tx_dma = dma + offsetof(struct scratch, crc_val);
559 } else {
560 t->tx_buf = host->ones;
561 t->tx_dma = host->ones_dma;
562 t->rx_buf = &scratch->crc_val;
563 if (dma)
564 t->rx_dma = dma + offsetof(struct scratch, crc_val);
565 }
566 spi_message_add_tail(t, &host->m);
567
568 /*
569 * A single block read is followed by N(EC) [0+] all-ones bytes
570 * before deselect ... don't bother.
571 *
572 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
573 * the next block is read, or a STOP_TRANSMISSION is issued. We'll
574 * collect that single byte, so readblock() doesn't need to.
575 *
576 * For a write, the one-byte data response follows immediately, then
577 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
578 * Then single block reads may deselect, and multiblock ones issue
579 * the next token (next data block, or STOP_TRAN). We can try to
580 * minimize I/O ops by using a single read to collect end-of-busy.
581 */
582 if (multiple || direction == DMA_TO_DEVICE) {
583 t = &host->early_status;
584 memset(t, 0, sizeof(*t));
585 t->len = (direction == DMA_TO_DEVICE)
586 ? sizeof(scratch->status)
587 : 1;
588 t->tx_buf = host->ones;
589 t->tx_dma = host->ones_dma;
590 t->rx_buf = scratch->status;
591 if (dma)
592 t->rx_dma = dma + offsetof(struct scratch, status);
593 t->cs_change = 1;
594 spi_message_add_tail(t, &host->m);
595 }
596}
597
598/*
599 * Write one block:
600 * - caller handled preceding N(WR) [1+] all-ones bytes
601 * - data block
602 * + token
603 * + data bytes
604 * + crc16
605 * - an all-ones byte ... card writes a data-response byte
606 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
607 *
608 * Return negative errno, else success.
609 */
610static int
611mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t)
612{
613 struct spi_device *spi = host->spi;
614 int status, i;
615 struct scratch *scratch = host->data;
616
617 if (host->mmc->use_spi_crc)
618 scratch->crc_val = cpu_to_be16(
619 crc_itu_t(0, t->tx_buf, t->len));
620 if (host->dma_dev)
621 dma_sync_single_for_device(host->dma_dev,
622 host->data_dma, sizeof(*scratch),
623 DMA_BIDIRECTIONAL);
624
625 status = spi_sync(spi, &host->m);
626 if (status == 0)
627 status = host->m.status;
628
629 if (status != 0) {
630 dev_dbg(&spi->dev, "write error (%d)\n", status);
631 return status;
632 }
633
634 if (host->dma_dev)
635 dma_sync_single_for_cpu(host->dma_dev,
636 host->data_dma, sizeof(*scratch),
637 DMA_BIDIRECTIONAL);
638
639 /*
640 * Get the transmission data-response reply. It must follow
641 * immediately after the data block we transferred. This reply
642 * doesn't necessarily tell whether the write operation succeeded;
643 * it just says if the transmission was ok and whether *earlier*
644 * writes succeeded; see the standard.
645 */
646 switch (SPI_MMC_RESPONSE_CODE(scratch->status[0])) {
647 case SPI_RESPONSE_ACCEPTED:
648 status = 0;
649 break;
650 case SPI_RESPONSE_CRC_ERR:
651 /* host shall then issue MMC_STOP_TRANSMISSION */
652 status = -EILSEQ;
653 break;
654 case SPI_RESPONSE_WRITE_ERR:
655 /* host shall then issue MMC_STOP_TRANSMISSION,
656 * and should MMC_SEND_STATUS to sort it out
657 */
658 status = -EIO;
659 break;
660 default:
661 status = -EPROTO;
662 break;
663 }
664 if (status != 0) {
665 dev_dbg(&spi->dev, "write error %02x (%d)\n",
666 scratch->status[0], status);
667 return status;
668 }
669
670 t->tx_buf += t->len;
671 if (host->dma_dev)
672 t->tx_dma += t->len;
673
674 /* Return when not busy. If we didn't collect that status yet,
675 * we'll need some more I/O.
676 */
677 for (i = 1; i < sizeof(scratch->status); i++) {
678 if (scratch->status[i] != 0)
679 return 0;
680 }
681 return mmc_spi_wait_unbusy(host, writeblock_timeout);
682}
683
684/*
685 * Read one block:
686 * - skip leading all-ones bytes ... either
687 * + N(AC) [1..f(clock,CSD)] usually, else
688 * + N(CX) [0..8] when reading CSD or CID
689 * - data block
690 * + token ... if error token, no data or crc
691 * + data bytes
692 * + crc16
693 *
694 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
695 * before dropping chipselect.
696 *
697 * For multiblock reads, caller either reads the next block or issues a
698 * STOP_TRANSMISSION command.
699 */
700static int
701mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t)
702{
703 struct spi_device *spi = host->spi;
704 int status;
705 struct scratch *scratch = host->data;
706
707 /* At least one SD card sends an all-zeroes byte when N(CX)
708 * applies, before the all-ones bytes ... just cope with that.
709 */
710 status = mmc_spi_readbytes(host, 1);
711 if (status < 0)
712 return status;
713 status = scratch->status[0];
714 if (status == 0xff || status == 0)
715 status = mmc_spi_readtoken(host);
716
717 if (status == SPI_TOKEN_SINGLE) {
718 if (host->dma_dev) {
719 dma_sync_single_for_device(host->dma_dev,
720 host->data_dma, sizeof(*scratch),
721 DMA_BIDIRECTIONAL);
722 dma_sync_single_for_device(host->dma_dev,
723 t->rx_dma, t->len,
724 DMA_FROM_DEVICE);
725 }
726
727 status = spi_sync(spi, &host->m);
728 if (status == 0)
729 status = host->m.status;
730
731 if (host->dma_dev) {
732 dma_sync_single_for_cpu(host->dma_dev,
733 host->data_dma, sizeof(*scratch),
734 DMA_BIDIRECTIONAL);
735 dma_sync_single_for_cpu(host->dma_dev,
736 t->rx_dma, t->len,
737 DMA_FROM_DEVICE);
738 }
739
740 } else {
741 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
742
743 /* we've read extra garbage, timed out, etc */
744 if (status < 0)
745 return status;
746
747 /* low four bits are an R2 subset, fifth seems to be
748 * vendor specific ... map them all to generic error..
749 */
750 return -EIO;
751 }
752
753 if (host->mmc->use_spi_crc) {
754 u16 crc = crc_itu_t(0, t->rx_buf, t->len);
755
756 be16_to_cpus(&scratch->crc_val);
757 if (scratch->crc_val != crc) {
758 dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, "
759 "computed=0x%04x len=%d\n",
760 scratch->crc_val, crc, t->len);
761 return -EILSEQ;
762 }
763 }
764
765 t->rx_buf += t->len;
766 if (host->dma_dev)
767 t->rx_dma += t->len;
768
769 return 0;
770}
771
772/*
773 * An MMC/SD data stage includes one or more blocks, optional CRCs,
774 * and inline handshaking. That handhaking makes it unlike most
775 * other SPI protocol stacks.
776 */
777static void
778mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
779 struct mmc_data *data, u32 blk_size)
780{
781 struct spi_device *spi = host->spi;
782 struct device *dma_dev = host->dma_dev;
783 struct spi_transfer *t;
784 enum dma_data_direction direction;
785 struct scatterlist *sg;
786 unsigned n_sg;
787 int multiple = (data->blocks > 1);
788
789 if (data->flags & MMC_DATA_READ)
790 direction = DMA_FROM_DEVICE;
791 else
792 direction = DMA_TO_DEVICE;
793 mmc_spi_setup_data_message(host, multiple, direction);
794 t = &host->t;
795
796 /* Handle scatterlist segments one at a time, with synch for
797 * each 512-byte block
798 */
799 for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
800 int status = 0;
801 dma_addr_t dma_addr = 0;
802 void *kmap_addr;
803 unsigned length = sg->length;
804 enum dma_data_direction dir = direction;
805
806 /* set up dma mapping for controller drivers that might
807 * use DMA ... though they may fall back to PIO
808 */
809 if (dma_dev) {
810 /* never invalidate whole *shared* pages ... */
811 if ((sg->offset != 0 || length != PAGE_SIZE)
812 && dir == DMA_FROM_DEVICE)
813 dir = DMA_BIDIRECTIONAL;
814
815 dma_addr = dma_map_page(dma_dev, sg->page, 0,
816 PAGE_SIZE, dir);
817 if (direction == DMA_TO_DEVICE)
818 t->tx_dma = dma_addr + sg->offset;
819 else
820 t->rx_dma = dma_addr + sg->offset;
821 }
822
823 /* allow pio too; we don't allow highmem */
824 kmap_addr = kmap(sg->page);
825 if (direction == DMA_TO_DEVICE)
826 t->tx_buf = kmap_addr + sg->offset;
827 else
828 t->rx_buf = kmap_addr + sg->offset;
829
830 /* transfer each block, and update request status */
831 while (length) {
832 t->len = min(length, blk_size);
833
834 dev_dbg(&host->spi->dev,
835 " mmc_spi: %s block, %d bytes\n",
836 (direction == DMA_TO_DEVICE)
837 ? "write"
838 : "read",
839 t->len);
840
841 if (direction == DMA_TO_DEVICE)
842 status = mmc_spi_writeblock(host, t);
843 else
844 status = mmc_spi_readblock(host, t);
845 if (status < 0)
846 break;
847
848 data->bytes_xfered += t->len;
849 length -= t->len;
850
851 if (!multiple)
852 break;
853 }
854
855 /* discard mappings */
856 if (direction == DMA_FROM_DEVICE)
857 flush_kernel_dcache_page(sg->page);
858 kunmap(sg->page);
859 if (dma_dev)
860 dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
861
862 if (status < 0) {
863 data->error = status;
864 dev_dbg(&spi->dev, "%s status %d\n",
865 (direction == DMA_TO_DEVICE)
866 ? "write" : "read",
867 status);
868 break;
869 }
870 }
871
872 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
873 * can be issued before multiblock writes. Unlike its more widely
874 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
875 * that can affect the STOP_TRAN logic. Complete (and current)
876 * MMC specs should sort that out before Linux starts using CMD23.
877 */
878 if (direction == DMA_TO_DEVICE && multiple) {
879 struct scratch *scratch = host->data;
880 int tmp;
881 const unsigned statlen = sizeof(scratch->status);
882
883 dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n");
884
885 /* Tweak the per-block message we set up earlier by morphing
886 * it to hold single buffer with the token followed by some
887 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
888 * "not busy any longer" status, and leave chip selected.
889 */
890 INIT_LIST_HEAD(&host->m.transfers);
891 list_add(&host->early_status.transfer_list,
892 &host->m.transfers);
893
894 memset(scratch->status, 0xff, statlen);
895 scratch->status[0] = SPI_TOKEN_STOP_TRAN;
896
897 host->early_status.tx_buf = host->early_status.rx_buf;
898 host->early_status.tx_dma = host->early_status.rx_dma;
899 host->early_status.len = statlen;
900
901 if (host->dma_dev)
902 dma_sync_single_for_device(host->dma_dev,
903 host->data_dma, sizeof(*scratch),
904 DMA_BIDIRECTIONAL);
905
906 tmp = spi_sync(spi, &host->m);
907 if (tmp == 0)
908 tmp = host->m.status;
909
910 if (host->dma_dev)
911 dma_sync_single_for_cpu(host->dma_dev,
912 host->data_dma, sizeof(*scratch),
913 DMA_BIDIRECTIONAL);
914
915 if (tmp < 0) {
916 if (!data->error)
917 data->error = tmp;
918 return;
919 }
920
921 /* Ideally we collected "not busy" status with one I/O,
922 * avoiding wasteful byte-at-a-time scanning... but more
923 * I/O is often needed.
924 */
925 for (tmp = 2; tmp < statlen; tmp++) {
926 if (scratch->status[tmp] != 0)
927 return;
928 }
929 tmp = mmc_spi_wait_unbusy(host, writeblock_timeout);
930 if (tmp < 0 && !data->error)
931 data->error = tmp;
932 }
933}
934
935/****************************************************************************/
936
937/*
938 * MMC driver implementation -- the interface to the MMC stack
939 */
940
941static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
942{
943 struct mmc_spi_host *host = mmc_priv(mmc);
944 int status = -EINVAL;
945
946#ifdef DEBUG
947 /* MMC core and layered drivers *MUST* issue SPI-aware commands */
948 {
949 struct mmc_command *cmd;
950 int invalid = 0;
951
952 cmd = mrq->cmd;
953 if (!mmc_spi_resp_type(cmd)) {
954 dev_dbg(&host->spi->dev, "bogus command\n");
955 cmd->error = -EINVAL;
956 invalid = 1;
957 }
958
959 cmd = mrq->stop;
960 if (cmd && !mmc_spi_resp_type(cmd)) {
961 dev_dbg(&host->spi->dev, "bogus STOP command\n");
962 cmd->error = -EINVAL;
963 invalid = 1;
964 }
965
966 if (invalid) {
967 dump_stack();
968 mmc_request_done(host->mmc, mrq);
969 return;
970 }
971 }
972#endif
973
974 /* issue command; then optionally data and stop */
975 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
976 if (status == 0 && mrq->data) {
977 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
978 if (mrq->stop)
979 status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
980 else
981 mmc_cs_off(host);
982 }
983
984 mmc_request_done(host->mmc, mrq);
985}
986
987/* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
988 *
989 * NOTE that here we can't know that the card has just been powered up;
990 * not all MMC/SD sockets support power switching.
991 *
992 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
993 * this doesn't seem to do the right thing at all...
994 */
995static void mmc_spi_initsequence(struct mmc_spi_host *host)
996{
997 /* Try to be very sure any previous command has completed;
998 * wait till not-busy, skip debris from any old commands.
999 */
1000 mmc_spi_wait_unbusy(host, r1b_timeout);
1001 mmc_spi_readbytes(host, 10);
1002
1003 /*
1004 * Do a burst with chipselect active-high. We need to do this to
1005 * meet the requirement of 74 clock cycles with both chipselect
1006 * and CMD (MOSI) high before CMD0 ... after the card has been
1007 * powered up to Vdd(min), and so is ready to take commands.
1008 *
1009 * Some cards are particularly needy of this (e.g. Viking "SD256")
1010 * while most others don't seem to care.
1011 *
1012 * Note that this is one of the places MMC/SD plays games with the
1013 * SPI protocol. Another is that when chipselect is released while
1014 * the card returns BUSY status, the clock must issue several cycles
1015 * with chipselect high before the card will stop driving its output.
1016 */
1017 host->spi->mode |= SPI_CS_HIGH;
1018 if (spi_setup(host->spi) != 0) {
1019 /* Just warn; most cards work without it. */
1020 dev_warn(&host->spi->dev,
1021 "can't change chip-select polarity\n");
1022 host->spi->mode &= ~SPI_CS_HIGH;
1023 } else {
1024 mmc_spi_readbytes(host, 18);
1025
1026 host->spi->mode &= ~SPI_CS_HIGH;
1027 if (spi_setup(host->spi) != 0) {
1028 /* Wot, we can't get the same setup we had before? */
1029 dev_err(&host->spi->dev,
1030 "can't restore chip-select polarity\n");
1031 }
1032 }
1033}
1034
1035static char *mmc_powerstring(u8 power_mode)
1036{
1037 switch (power_mode) {
1038 case MMC_POWER_OFF: return "off";
1039 case MMC_POWER_UP: return "up";
1040 case MMC_POWER_ON: return "on";
1041 }
1042 return "?";
1043}
1044
1045static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1046{
1047 struct mmc_spi_host *host = mmc_priv(mmc);
1048
1049 if (host->power_mode != ios->power_mode) {
1050 int canpower;
1051
1052 canpower = host->pdata && host->pdata->setpower;
1053
1054 dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1055 mmc_powerstring(ios->power_mode),
1056 ios->vdd,
1057 canpower ? ", can switch" : "");
1058
1059 /* switch power on/off if possible, accounting for
1060 * max 250msec powerup time if needed.
1061 */
1062 if (canpower) {
1063 switch (ios->power_mode) {
1064 case MMC_POWER_OFF:
1065 case MMC_POWER_UP:
1066 host->pdata->setpower(&host->spi->dev,
1067 ios->vdd);
1068 if (ios->power_mode == MMC_POWER_UP)
1069 msleep(host->powerup_msecs);
1070 }
1071 }
1072
1073 /* See 6.4.1 in the simplified SD card physical spec 2.0 */
1074 if (ios->power_mode == MMC_POWER_ON)
1075 mmc_spi_initsequence(host);
1076
1077 /* If powering down, ground all card inputs to avoid power
1078 * delivery from data lines! On a shared SPI bus, this
1079 * will probably be temporary; 6.4.2 of the simplified SD
1080 * spec says this must last at least 1msec.
1081 *
1082 * - Clock low means CPOL 0, e.g. mode 0
1083 * - MOSI low comes from writing zero
1084 * - Chipselect is usually active low...
1085 */
1086 if (canpower && ios->power_mode == MMC_POWER_OFF) {
1087 int mres;
1088
1089 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1090 mres = spi_setup(host->spi);
1091 if (mres < 0)
1092 dev_dbg(&host->spi->dev,
1093 "switch to SPI mode 0 failed\n");
1094
1095 if (spi_w8r8(host->spi, 0x00) < 0)
1096 dev_dbg(&host->spi->dev,
1097 "put spi signals to low failed\n");
1098
1099 /*
1100 * Now clock should be low due to spi mode 0;
1101 * MOSI should be low because of written 0x00;
1102 * chipselect should be low (it is active low)
1103 * power supply is off, so now MMC is off too!
1104 *
1105 * FIXME no, chipselect can be high since the
1106 * device is inactive and SPI_CS_HIGH is clear...
1107 */
1108 msleep(10);
1109 if (mres == 0) {
1110 host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1111 mres = spi_setup(host->spi);
1112 if (mres < 0)
1113 dev_dbg(&host->spi->dev,
1114 "switch back to SPI mode 3"
1115 " failed\n");
1116 }
1117 }
1118
1119 host->power_mode = ios->power_mode;
1120 }
1121
1122 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1123 int status;
1124
1125 host->spi->max_speed_hz = ios->clock;
1126 status = spi_setup(host->spi);
1127 dev_dbg(&host->spi->dev,
1128 "mmc_spi: clock to %d Hz, %d\n",
1129 host->spi->max_speed_hz, status);
1130 }
1131}
1132
1133static int mmc_spi_get_ro(struct mmc_host *mmc)
1134{
1135 struct mmc_spi_host *host = mmc_priv(mmc);
1136
1137 if (host->pdata && host->pdata->get_ro)
1138 return host->pdata->get_ro(mmc->parent);
1139 /* board doesn't support read only detection; assume writeable */
1140 return 0;
1141}
1142
1143
1144static const struct mmc_host_ops mmc_spi_ops = {
1145 .request = mmc_spi_request,
1146 .set_ios = mmc_spi_set_ios,
1147 .get_ro = mmc_spi_get_ro,
1148};
1149
1150
1151/****************************************************************************/
1152
1153/*
1154 * SPI driver implementation
1155 */
1156
1157static irqreturn_t
1158mmc_spi_detect_irq(int irq, void *mmc)
1159{
1160 struct mmc_spi_host *host = mmc_priv(mmc);
1161 u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1162
1163 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1164 return IRQ_HANDLED;
1165}
1166
1167static int mmc_spi_probe(struct spi_device *spi)
1168{
1169 void *ones;
1170 struct mmc_host *mmc;
1171 struct mmc_spi_host *host;
1172 int status;
1173
1174 /* MMC and SD specs only seem to care that sampling is on the
1175 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
1176 * should be legit. We'll use mode 0 since it seems to be a
1177 * bit less troublesome on some hardware ... unclear why.
1178 */
1179 spi->mode = SPI_MODE_0;
1180 spi->bits_per_word = 8;
1181
1182 status = spi_setup(spi);
1183 if (status < 0) {
1184 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1185 spi->mode, spi->max_speed_hz / 1000,
1186 status);
1187 return status;
1188 }
1189
1190 /* We can use the bus safely iff nobody else will interfere with
1191 * us. That is, either we have the experimental exclusive access
1192 * primitives ... or else there's nobody to share it with.
1193 */
1194 if (spi->master->num_chipselect > 1) {
1195 struct device *parent = spi->dev.parent;
1196
1197 /* If there are multiple devices on this bus, we
1198 * can't proceed.
1199 */
1200 spin_lock(&parent->klist_children.k_lock);
1201 if (parent->klist_children.k_list.next
1202 != parent->klist_children.k_list.prev)
1203 status = -EMLINK;
1204 else
1205 status = 0;
1206 spin_unlock(&parent->klist_children.k_lock);
1207 if (status < 0) {
1208 dev_err(&spi->dev, "can't share SPI bus\n");
1209 return status;
1210 }
1211
1212 /* REVISIT we can't guarantee another device won't
1213 * be added later. It's uncommon though ... for now,
1214 * work as if this is safe.
1215 */
1216 dev_warn(&spi->dev, "ASSUMING unshared SPI bus!\n");
1217 }
1218
1219 /* We need a supply of ones to transmit. This is the only time
1220 * the CPU touches these, so cache coherency isn't a concern.
1221 *
1222 * NOTE if many systems use more than one MMC-over-SPI connector
1223 * it'd save some memory to share this. That's evidently rare.
1224 */
1225 status = -ENOMEM;
1226 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1227 if (!ones)
1228 goto nomem;
1229 memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1230
1231 mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1232 if (!mmc)
1233 goto nomem;
1234
1235 mmc->ops = &mmc_spi_ops;
1236 mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1237
1238 /* As long as we keep track of the number of successfully
1239 * transmitted blocks, we're good for multiwrite.
1240 */
1241 mmc->caps = MMC_CAP_SPI | MMC_CAP_MULTIWRITE;
1242
1243 /* SPI doesn't need the lowspeed device identification thing for
1244 * MMC or SD cards, since it never comes up in open drain mode.
1245 * That's good; some SPI masters can't handle very low speeds!
1246 *
1247 * However, low speed SDIO cards need not handle over 400 KHz;
1248 * that's the only reason not to use a few MHz for f_min (until
1249 * the upper layer reads the target frequency from the CSD).
1250 */
1251 mmc->f_min = 400000;
1252 mmc->f_max = spi->max_speed_hz;
1253
1254 host = mmc_priv(mmc);
1255 host->mmc = mmc;
1256 host->spi = spi;
1257
1258 host->ones = ones;
1259
1260 /* Platform data is used to hook up things like card sensing
1261 * and power switching gpios.
1262 */
1263 host->pdata = spi->dev.platform_data;
1264 if (host->pdata)
1265 mmc->ocr_avail = host->pdata->ocr_mask;
1266 if (!mmc->ocr_avail) {
1267 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1268 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1269 }
1270 if (host->pdata && host->pdata->setpower) {
1271 host->powerup_msecs = host->pdata->powerup_msecs;
1272 if (!host->powerup_msecs || host->powerup_msecs > 250)
1273 host->powerup_msecs = 250;
1274 }
1275
1276 dev_set_drvdata(&spi->dev, mmc);
1277
1278 /* preallocate dma buffers */
1279 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1280 if (!host->data)
1281 goto fail_nobuf1;
1282
1283 if (spi->master->cdev.dev->dma_mask) {
1284 struct device *dev = spi->master->cdev.dev;
1285
1286 host->dma_dev = dev;
1287 host->ones_dma = dma_map_single(dev, ones,
1288 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1289 host->data_dma = dma_map_single(dev, host->data,
1290 sizeof(*host->data), DMA_BIDIRECTIONAL);
1291
1292 /* REVISIT in theory those map operations can fail... */
1293
1294 dma_sync_single_for_cpu(host->dma_dev,
1295 host->data_dma, sizeof(*host->data),
1296 DMA_BIDIRECTIONAL);
1297 }
1298
1299 /* setup message for status/busy readback */
1300 spi_message_init(&host->readback);
1301 host->readback.is_dma_mapped = (host->dma_dev != NULL);
1302
1303 spi_message_add_tail(&host->status, &host->readback);
1304 host->status.tx_buf = host->ones;
1305 host->status.tx_dma = host->ones_dma;
1306 host->status.rx_buf = &host->data->status;
1307 host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1308 host->status.cs_change = 1;
1309
1310 /* register card detect irq */
1311 if (host->pdata && host->pdata->init) {
1312 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1313 if (status != 0)
1314 goto fail_glue_init;
1315 }
1316
1317 status = mmc_add_host(mmc);
1318 if (status != 0)
1319 goto fail_add_host;
1320
1321 dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n",
1322 mmc->class_dev.bus_id,
1323 host->dma_dev ? "" : ", no DMA",
1324 (host->pdata && host->pdata->get_ro)
1325 ? "" : ", no WP",
1326 (host->pdata && host->pdata->setpower)
1327 ? "" : ", no poweroff");
1328 return 0;
1329
1330fail_add_host:
1331 mmc_remove_host (mmc);
1332fail_glue_init:
1333 if (host->dma_dev)
1334 dma_unmap_single(host->dma_dev, host->data_dma,
1335 sizeof(*host->data), DMA_BIDIRECTIONAL);
1336 kfree(host->data);
1337
1338fail_nobuf1:
1339 mmc_free_host(mmc);
1340 dev_set_drvdata(&spi->dev, NULL);
1341
1342nomem:
1343 kfree(ones);
1344 return status;
1345}
1346
1347
1348static int __devexit mmc_spi_remove(struct spi_device *spi)
1349{
1350 struct mmc_host *mmc = dev_get_drvdata(&spi->dev);
1351 struct mmc_spi_host *host;
1352
1353 if (mmc) {
1354 host = mmc_priv(mmc);
1355
1356 /* prevent new mmc_detect_change() calls */
1357 if (host->pdata && host->pdata->exit)
1358 host->pdata->exit(&spi->dev, mmc);
1359
1360 mmc_remove_host(mmc);
1361
1362 if (host->dma_dev) {
1363 dma_unmap_single(host->dma_dev, host->ones_dma,
1364 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1365 dma_unmap_single(host->dma_dev, host->data_dma,
1366 sizeof(*host->data), DMA_BIDIRECTIONAL);
1367 }
1368
1369 kfree(host->data);
1370 kfree(host->ones);
1371
1372 spi->max_speed_hz = mmc->f_max;
1373 mmc_free_host(mmc);
1374 dev_set_drvdata(&spi->dev, NULL);
1375 }
1376 return 0;
1377}
1378
1379
1380static struct spi_driver mmc_spi_driver = {
1381 .driver = {
1382 .name = "mmc_spi",
1383 .bus = &spi_bus_type,
1384 .owner = THIS_MODULE,
1385 },
1386 .probe = mmc_spi_probe,
1387 .remove = __devexit_p(mmc_spi_remove),
1388};
1389
1390
1391static int __init mmc_spi_init(void)
1392{
1393 return spi_register_driver(&mmc_spi_driver);
1394}
1395module_init(mmc_spi_init);
1396
1397
1398static void __exit mmc_spi_exit(void)
1399{
1400 spi_unregister_driver(&mmc_spi_driver);
1401}
1402module_exit(mmc_spi_exit);
1403
1404
1405MODULE_AUTHOR("Mike Lavender, David Brownell, "
1406 "Hans-Peter Nilsson, Jan Nikitenko");
1407MODULE_DESCRIPTION("SPI SD/MMC host driver");
1408MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 11:16:58 -0500