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path: root/drivers/mmc/host/au1xmmc.c
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Diffstat (limited to 'drivers/mmc/host/au1xmmc.c')
-rw-r--r--drivers/mmc/host/au1xmmc.c45
1 files changed, 28 insertions, 17 deletions
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 5d3b9ae64523..dbd0c8a4e98a 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -153,6 +153,7 @@ static inline int has_dbdma(void)
153{ 153{
154 switch (alchemy_get_cputype()) { 154 switch (alchemy_get_cputype()) {
155 case ALCHEMY_CPU_AU1200: 155 case ALCHEMY_CPU_AU1200:
156 case ALCHEMY_CPU_AU1300:
156 return 1; 157 return 1;
157 default: 158 default:
158 return 0; 159 return 0;
@@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
768 769
769 config2 = au_readl(HOST_CONFIG2(host)); 770 config2 = au_readl(HOST_CONFIG2(host));
770 switch (ios->bus_width) { 771 switch (ios->bus_width) {
772 case MMC_BUS_WIDTH_8:
773 config2 |= SD_CONFIG2_BB;
774 break;
771 case MMC_BUS_WIDTH_4: 775 case MMC_BUS_WIDTH_4:
776 config2 &= ~SD_CONFIG2_BB;
772 config2 |= SD_CONFIG2_WB; 777 config2 |= SD_CONFIG2_WB;
773 break; 778 break;
774 case MMC_BUS_WIDTH_1: 779 case MMC_BUS_WIDTH_1:
775 config2 &= ~SD_CONFIG2_WB; 780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
776 break; 781 break;
777 } 782 }
778 au_writel(config2, HOST_CONFIG2(host)); 783 au_writel(config2, HOST_CONFIG2(host));
@@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
943 struct mmc_host *mmc; 948 struct mmc_host *mmc;
944 struct au1xmmc_host *host; 949 struct au1xmmc_host *host;
945 struct resource *r; 950 struct resource *r;
946 int ret; 951 int ret, iflag;
947 952
948 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); 953 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
949 if (!mmc) { 954 if (!mmc) {
@@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
982 dev_err(&pdev->dev, "no IRQ defined\n"); 987 dev_err(&pdev->dev, "no IRQ defined\n");
983 goto out3; 988 goto out3;
984 } 989 }
985
986 host->irq = r->start; 990 host->irq = r->start;
987 /* IRQ is shared among both SD controllers */
988 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
989 DRIVER_NAME, host);
990 if (ret) {
991 dev_err(&pdev->dev, "cannot grab IRQ\n");
992 goto out3;
993 }
994 991
995 mmc->ops = &au1xmmc_ops; 992 mmc->ops = &au1xmmc_ops;
996 993
997 mmc->f_min = 450000; 994 mmc->f_min = 450000;
998 mmc->f_max = 24000000; 995 mmc->f_max = 24000000;
999 996
997 mmc->max_blk_size = 2048;
998 mmc->max_blk_count = 512;
999
1000 mmc->ocr_avail = AU1XMMC_OCR;
1001 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1002 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1003
1004 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
1005
1000 switch (alchemy_get_cputype()) { 1006 switch (alchemy_get_cputype()) {
1001 case ALCHEMY_CPU_AU1100: 1007 case ALCHEMY_CPU_AU1100:
1002 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; 1008 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1003 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1004 break; 1009 break;
1005 case ALCHEMY_CPU_AU1200: 1010 case ALCHEMY_CPU_AU1200:
1006 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; 1011 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1007 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; 1012 break;
1013 case ALCHEMY_CPU_AU1300:
1014 iflag = 0; /* nothing is shared */
1015 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016 mmc->f_max = 52000000;
1017 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1018 mmc->caps |= MMC_CAP_8_BIT_DATA;
1008 break; 1019 break;
1009 } 1020 }
1010 1021
1011 mmc->max_blk_size = 2048; 1022 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1012 mmc->max_blk_count = 512; 1023 if (ret) {
1013 1024 dev_err(&pdev->dev, "cannot grab IRQ\n");
1014 mmc->ocr_avail = AU1XMMC_OCR; 1025 goto out3;
1015 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1026 }
1016 1027
1017 host->status = HOST_S_IDLE; 1028 host->status = HOST_S_IDLE;
1018 1029