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-rw-r--r--drivers/mfd/Kconfig42
-rw-r--r--drivers/mfd/Makefile6
-rw-r--r--drivers/mfd/ab3100-core.c62
-rw-r--r--drivers/mfd/ab3100-otp.c268
-rw-r--r--drivers/mfd/dm355evm_msp.c12
-rw-r--r--drivers/mfd/ezx-pcap.c105
-rw-r--r--drivers/mfd/mc13783-core.c427
-rw-r--r--drivers/mfd/mfd-core.c2
-rw-r--r--drivers/mfd/pcf50633-adc.c32
-rw-r--r--drivers/mfd/pcf50633-core.c5
-rw-r--r--drivers/mfd/twl4030-core.c23
-rw-r--r--drivers/mfd/twl4030-irq.c2
-rw-r--r--drivers/mfd/twl4030-power.c472
-rw-r--r--drivers/mfd/wm831x-core.c1549
-rw-r--r--drivers/mfd/wm831x-irq.c559
-rw-r--r--drivers/mfd/wm831x-otp.c83
-rw-r--r--drivers/mfd/wm8350-core.c27
17 files changed, 3579 insertions, 97 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 491ac0f800d2..570be139f9df 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -108,6 +108,19 @@ config TWL4030_CORE
108 high speed USB OTG transceiver, an audio codec (on most 108 high speed USB OTG transceiver, an audio codec (on most
109 versions) and many other features. 109 versions) and many other features.
110 110
111config TWL4030_POWER
112 bool "Support power resources on TWL4030 family chips"
113 depends on TWL4030_CORE && ARM
114 help
115 Say yes here if you want to use the power resources on the
116 TWL4030 family chips. Most of these resources are regulators,
117 which have a separate driver; some are control signals, such
118 as clock request handshaking.
119
120 This driver uses board-specific data to initialize the resources
121 and load scripts controling which resources are switched off/on
122 or reset when a sleep, wakeup or warm reset event occurs.
123
111config MFD_TMIO 124config MFD_TMIO
112 bool 125 bool
113 default n 126 default n
@@ -157,6 +170,16 @@ config MFD_WM8400
157 the device, additional drivers must be enabled in order to use 170 the device, additional drivers must be enabled in order to use
158 the functionality of the device. 171 the functionality of the device.
159 172
173config MFD_WM831X
174 tristate "Support Wolfson Microelectronics WM831x PMICs"
175 select MFD_CORE
176 depends on I2C
177 help
178 Support for the Wolfson Microelecronics WM831x PMICs. This
179 driver provides common support for accessing the device,
180 additional drivers must be enabled in order to use the
181 functionality of the device.
182
160config MFD_WM8350 183config MFD_WM8350
161 tristate 184 tristate
162 185
@@ -228,6 +251,16 @@ config MFD_PCF50633
228 facilities, and registers devices for the various functions 251 facilities, and registers devices for the various functions
229 so that function-specific drivers can bind to them. 252 so that function-specific drivers can bind to them.
230 253
254config MFD_MC13783
255 tristate "Support Freescale MC13783"
256 depends on SPI_MASTER
257 select MFD_CORE
258 help
259 Support for the Freescale (Atlas) MC13783 PMIC and audio CODEC.
260 This driver provides common support for accessing the device,
261 additional drivers must be enabled in order to use the
262 functionality of the device.
263
231config PCF50633_ADC 264config PCF50633_ADC
232 tristate "Support for NXP PCF50633 ADC" 265 tristate "Support for NXP PCF50633 ADC"
233 depends on MFD_PCF50633 266 depends on MFD_PCF50633
@@ -256,6 +289,15 @@ config AB3100_CORE
256 LEDs, vibrator, system power and temperature, power management 289 LEDs, vibrator, system power and temperature, power management
257 and ALSA sound. 290 and ALSA sound.
258 291
292config AB3100_OTP
293 tristate "ST-Ericsson AB3100 OTP functions"
294 depends on AB3100_CORE
295 default y if AB3100_CORE
296 help
297 Select this to enable the AB3100 Mixed Signal IC OTP (one-time
298 programmable memory) support. This exposes a sysfs file to read
299 out OTP values.
300
259config EZX_PCAP 301config EZX_PCAP
260 bool "PCAP Support" 302 bool "PCAP Support"
261 depends on GENERIC_HARDIRQS && SPI_MASTER 303 depends on GENERIC_HARDIRQS && SPI_MASTER
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6f8a9a1af20b..f3b277b90d40 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
15obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o 15obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
16 16
17obj-$(CONFIG_MFD_WM8400) += wm8400-core.o 17obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
18wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o
19obj-$(CONFIG_MFD_WM831X) += wm831x.o
18wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o 20wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o
19obj-$(CONFIG_MFD_WM8350) += wm8350.o 21obj-$(CONFIG_MFD_WM8350) += wm8350.o
20obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o 22obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
@@ -23,6 +25,9 @@ obj-$(CONFIG_TPS65010) += tps65010.o
23obj-$(CONFIG_MENELAUS) += menelaus.o 25obj-$(CONFIG_MENELAUS) += menelaus.o
24 26
25obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o 27obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
28obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o
29
30obj-$(CONFIG_MFD_MC13783) += mc13783-core.o
26 31
27obj-$(CONFIG_MFD_CORE) += mfd-core.o 32obj-$(CONFIG_MFD_CORE) += mfd-core.o
28 33
@@ -44,3 +49,4 @@ obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o
44obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o 49obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
45obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o 50obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
46obj-$(CONFIG_AB3100_CORE) += ab3100-core.o 51obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
52obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
index 13e7d7bfe85f..c533f86ff5ea 100644
--- a/drivers/mfd/ab3100-core.c
+++ b/drivers/mfd/ab3100-core.c
@@ -14,7 +14,6 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/workqueue.h>
18#include <linux/debugfs.h> 17#include <linux/debugfs.h>
19#include <linux/seq_file.h> 18#include <linux/seq_file.h>
20#include <linux/uaccess.h> 19#include <linux/uaccess.h>
@@ -77,7 +76,7 @@ u8 ab3100_get_chip_type(struct ab3100 *ab3100)
77} 76}
78EXPORT_SYMBOL(ab3100_get_chip_type); 77EXPORT_SYMBOL(ab3100_get_chip_type);
79 78
80int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval) 79int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval)
81{ 80{
82 u8 regandval[2] = {reg, regval}; 81 u8 regandval[2] = {reg, regval};
83 int err; 82 int err;
@@ -107,9 +106,10 @@ int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval)
107 err = 0; 106 err = 0;
108 } 107 }
109 mutex_unlock(&ab3100->access_mutex); 108 mutex_unlock(&ab3100->access_mutex);
110 return 0; 109 return err;
111} 110}
112EXPORT_SYMBOL(ab3100_set_register); 111EXPORT_SYMBOL(ab3100_set_register_interruptible);
112
113 113
114/* 114/*
115 * The test registers exist at an I2C bus address up one 115 * The test registers exist at an I2C bus address up one
@@ -118,7 +118,7 @@ EXPORT_SYMBOL(ab3100_set_register);
118 * anyway. It's currently only used from this file so declare 118 * anyway. It's currently only used from this file so declare
119 * it static and do not export. 119 * it static and do not export.
120 */ 120 */
121static int ab3100_set_test_register(struct ab3100 *ab3100, 121static int ab3100_set_test_register_interruptible(struct ab3100 *ab3100,
122 u8 reg, u8 regval) 122 u8 reg, u8 regval)
123{ 123{
124 u8 regandval[2] = {reg, regval}; 124 u8 regandval[2] = {reg, regval};
@@ -148,7 +148,8 @@ static int ab3100_set_test_register(struct ab3100 *ab3100,
148 return err; 148 return err;
149} 149}
150 150
151int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval) 151
152int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval)
152{ 153{
153 int err; 154 int err;
154 155
@@ -202,9 +203,10 @@ int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval)
202 mutex_unlock(&ab3100->access_mutex); 203 mutex_unlock(&ab3100->access_mutex);
203 return err; 204 return err;
204} 205}
205EXPORT_SYMBOL(ab3100_get_register); 206EXPORT_SYMBOL(ab3100_get_register_interruptible);
206 207
207int ab3100_get_register_page(struct ab3100 *ab3100, 208
209int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
208 u8 first_reg, u8 *regvals, u8 numregs) 210 u8 first_reg, u8 *regvals, u8 numregs)
209{ 211{
210 int err; 212 int err;
@@ -258,9 +260,10 @@ int ab3100_get_register_page(struct ab3100 *ab3100,
258 mutex_unlock(&ab3100->access_mutex); 260 mutex_unlock(&ab3100->access_mutex);
259 return err; 261 return err;
260} 262}
261EXPORT_SYMBOL(ab3100_get_register_page); 263EXPORT_SYMBOL(ab3100_get_register_page_interruptible);
264
262 265
263int ab3100_mask_and_set_register(struct ab3100 *ab3100, 266int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
264 u8 reg, u8 andmask, u8 ormask) 267 u8 reg, u8 andmask, u8 ormask)
265{ 268{
266 u8 regandval[2] = {reg, 0}; 269 u8 regandval[2] = {reg, 0};
@@ -328,7 +331,8 @@ int ab3100_mask_and_set_register(struct ab3100 *ab3100,
328 mutex_unlock(&ab3100->access_mutex); 331 mutex_unlock(&ab3100->access_mutex);
329 return err; 332 return err;
330} 333}
331EXPORT_SYMBOL(ab3100_mask_and_set_register); 334EXPORT_SYMBOL(ab3100_mask_and_set_register_interruptible);
335
332 336
333/* 337/*
334 * Register a simple callback for handling any AB3100 events. 338 * Register a simple callback for handling any AB3100 events.
@@ -371,7 +375,7 @@ static void ab3100_work(struct work_struct *work)
371 u32 fatevent; 375 u32 fatevent;
372 int err; 376 int err;
373 377
374 err = ab3100_get_register_page(ab3100, AB3100_EVENTA1, 378 err = ab3100_get_register_page_interruptible(ab3100, AB3100_EVENTA1,
375 event_regs, 3); 379 event_regs, 3);
376 if (err) 380 if (err)
377 goto err_event_wq; 381 goto err_event_wq;
@@ -417,7 +421,7 @@ static irqreturn_t ab3100_irq_handler(int irq, void *data)
417 * stuff and we will re-enable the interrupts once th 421 * stuff and we will re-enable the interrupts once th
418 * worker has finished. 422 * worker has finished.
419 */ 423 */
420 disable_irq(ab3100->i2c_client->irq); 424 disable_irq_nosync(irq);
421 schedule_work(&ab3100->work); 425 schedule_work(&ab3100->work);
422 return IRQ_HANDLED; 426 return IRQ_HANDLED;
423} 427}
@@ -435,7 +439,7 @@ static int ab3100_registers_print(struct seq_file *s, void *p)
435 seq_printf(s, "AB3100 registers:\n"); 439 seq_printf(s, "AB3100 registers:\n");
436 440
437 for (reg = 0; reg < 0xff; reg++) { 441 for (reg = 0; reg < 0xff; reg++) {
438 ab3100_get_register(ab3100, reg, &value); 442 ab3100_get_register_interruptible(ab3100, reg, &value);
439 seq_printf(s, "[0x%x]: 0x%x\n", reg, value); 443 seq_printf(s, "[0x%x]: 0x%x\n", reg, value);
440 } 444 }
441 return 0; 445 return 0;
@@ -465,14 +469,14 @@ static int ab3100_get_set_reg_open_file(struct inode *inode, struct file *file)
465 return 0; 469 return 0;
466} 470}
467 471
468static int ab3100_get_set_reg(struct file *file, 472static ssize_t ab3100_get_set_reg(struct file *file,
469 const char __user *user_buf, 473 const char __user *user_buf,
470 size_t count, loff_t *ppos) 474 size_t count, loff_t *ppos)
471{ 475{
472 struct ab3100_get_set_reg_priv *priv = file->private_data; 476 struct ab3100_get_set_reg_priv *priv = file->private_data;
473 struct ab3100 *ab3100 = priv->ab3100; 477 struct ab3100 *ab3100 = priv->ab3100;
474 char buf[32]; 478 char buf[32];
475 int buf_size; 479 ssize_t buf_size;
476 int regp; 480 int regp;
477 unsigned long user_reg; 481 unsigned long user_reg;
478 int err; 482 int err;
@@ -515,7 +519,7 @@ static int ab3100_get_set_reg(struct file *file,
515 u8 reg = (u8) user_reg; 519 u8 reg = (u8) user_reg;
516 u8 regvalue; 520 u8 regvalue;
517 521
518 ab3100_get_register(ab3100, reg, &regvalue); 522 ab3100_get_register_interruptible(ab3100, reg, &regvalue);
519 523
520 dev_info(ab3100->dev, 524 dev_info(ab3100->dev,
521 "debug read AB3100 reg[0x%02x]: 0x%02x\n", 525 "debug read AB3100 reg[0x%02x]: 0x%02x\n",
@@ -547,8 +551,8 @@ static int ab3100_get_set_reg(struct file *file,
547 return -EINVAL; 551 return -EINVAL;
548 552
549 value = (u8) user_value; 553 value = (u8) user_value;
550 ab3100_set_register(ab3100, reg, value); 554 ab3100_set_register_interruptible(ab3100, reg, value);
551 ab3100_get_register(ab3100, reg, &regvalue); 555 ab3100_get_register_interruptible(ab3100, reg, &regvalue);
552 556
553 dev_info(ab3100->dev, 557 dev_info(ab3100->dev,
554 "debug write reg[0x%02x] with 0x%02x, " 558 "debug write reg[0x%02x] with 0x%02x, "
@@ -662,7 +666,7 @@ ab3100_init_settings[] = {
662 .setting = 0x01 666 .setting = 0x01
663 }, { 667 }, {
664 .abreg = AB3100_IMRB1, 668 .abreg = AB3100_IMRB1,
665 .setting = 0xFF 669 .setting = 0xBF
666 }, { 670 }, {
667 .abreg = AB3100_IMRB2, 671 .abreg = AB3100_IMRB2,
668 .setting = 0xFF 672 .setting = 0xFF
@@ -696,7 +700,7 @@ static int __init ab3100_setup(struct ab3100 *ab3100)
696 int i; 700 int i;
697 701
698 for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) { 702 for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) {
699 err = ab3100_set_register(ab3100, 703 err = ab3100_set_register_interruptible(ab3100,
700 ab3100_init_settings[i].abreg, 704 ab3100_init_settings[i].abreg,
701 ab3100_init_settings[i].setting); 705 ab3100_init_settings[i].setting);
702 if (err) 706 if (err)
@@ -705,14 +709,14 @@ static int __init ab3100_setup(struct ab3100 *ab3100)
705 709
706 /* 710 /*
707 * Special trick to make the AB3100 use the 32kHz clock (RTC) 711 * Special trick to make the AB3100 use the 32kHz clock (RTC)
708 * bit 3 in test registe 0x02 is a special, undocumented test 712 * bit 3 in test register 0x02 is a special, undocumented test
709 * register bit that only exist in AB3100 P1E 713 * register bit that only exist in AB3100 P1E
710 */ 714 */
711 if (ab3100->chip_id == 0xc4) { 715 if (ab3100->chip_id == 0xc4) {
712 dev_warn(ab3100->dev, 716 dev_warn(ab3100->dev,
713 "AB3100 P1E variant detected, " 717 "AB3100 P1E variant detected, "
714 "forcing chip to 32KHz\n"); 718 "forcing chip to 32KHz\n");
715 err = ab3100_set_test_register(ab3100, 0x02, 0x08); 719 err = ab3100_set_test_register_interruptible(ab3100, 0x02, 0x08);
716 } 720 }
717 721
718 exit_no_setup: 722 exit_no_setup:
@@ -833,6 +837,8 @@ static int __init ab3100_probe(struct i2c_client *client,
833 const struct i2c_device_id *id) 837 const struct i2c_device_id *id)
834{ 838{
835 struct ab3100 *ab3100; 839 struct ab3100 *ab3100;
840 struct ab3100_platform_data *ab3100_plf_data =
841 client->dev.platform_data;
836 int err; 842 int err;
837 int i; 843 int i;
838 844
@@ -852,8 +858,8 @@ static int __init ab3100_probe(struct i2c_client *client,
852 i2c_set_clientdata(client, ab3100); 858 i2c_set_clientdata(client, ab3100);
853 859
854 /* Read chip ID register */ 860 /* Read chip ID register */
855 err = ab3100_get_register(ab3100, AB3100_CID, 861 err = ab3100_get_register_interruptible(ab3100, AB3100_CID,
856 &ab3100->chip_id); 862 &ab3100->chip_id);
857 if (err) { 863 if (err) {
858 dev_err(&client->dev, 864 dev_err(&client->dev,
859 "could not communicate with the AB3100 analog " 865 "could not communicate with the AB3100 analog "
@@ -916,6 +922,8 @@ static int __init ab3100_probe(struct i2c_client *client,
916 for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) { 922 for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) {
917 ab3100_platform_devs[i]->dev.parent = 923 ab3100_platform_devs[i]->dev.parent =
918 &client->dev; 924 &client->dev;
925 ab3100_platform_devs[i]->dev.platform_data =
926 ab3100_plf_data;
919 platform_set_drvdata(ab3100_platform_devs[i], ab3100); 927 platform_set_drvdata(ab3100_platform_devs[i], ab3100);
920 } 928 }
921 929
diff --git a/drivers/mfd/ab3100-otp.c b/drivers/mfd/ab3100-otp.c
new file mode 100644
index 000000000000..0499b2031a2c
--- /dev/null
+++ b/drivers/mfd/ab3100-otp.c
@@ -0,0 +1,268 @@
1/*
2 * drivers/mfd/ab3100_otp.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * Driver to read out OTP from the AB3100 Mixed-signal circuit
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/ab3100.h>
15#include <linux/debugfs.h>
16
17/* The OTP registers */
18#define AB3100_OTP0 0xb0
19#define AB3100_OTP1 0xb1
20#define AB3100_OTP2 0xb2
21#define AB3100_OTP3 0xb3
22#define AB3100_OTP4 0xb4
23#define AB3100_OTP5 0xb5
24#define AB3100_OTP6 0xb6
25#define AB3100_OTP7 0xb7
26#define AB3100_OTPP 0xbf
27
28/**
29 * struct ab3100_otp
30 * @dev containing device
31 * @ab3100 a pointer to the parent ab3100 device struct
32 * @locked whether the OTP is locked, after locking, no more bits
33 * can be changed but before locking it is still possible
34 * to change bits from 1->0.
35 * @freq clocking frequency for the OTP, this frequency is either
36 * 32768Hz or 1MHz/30
37 * @paf product activation flag, indicates whether this is a real
38 * product (paf true) or a lab board etc (paf false)
39 * @imeich if this is set it is possible to override the
40 * IMEI number found in the tac, fac and svn fields with
41 * (secured) software
42 * @cid customer ID
43 * @tac type allocation code of the IMEI
44 * @fac final assembly code of the IMEI
45 * @svn software version number of the IMEI
46 * @debugfs a debugfs file used when dumping to file
47 */
48struct ab3100_otp {
49 struct device *dev;
50 struct ab3100 *ab3100;
51 bool locked;
52 u32 freq;
53 bool paf;
54 bool imeich;
55 u16 cid:14;
56 u32 tac:20;
57 u8 fac;
58 u32 svn:20;
59 struct dentry *debugfs;
60};
61
62static int __init ab3100_otp_read(struct ab3100_otp *otp)
63{
64 struct ab3100 *ab = otp->ab3100;
65 u8 otpval[8];
66 u8 otpp;
67 int err;
68
69 err = ab3100_get_register_interruptible(ab, AB3100_OTPP, &otpp);
70 if (err) {
71 dev_err(otp->dev, "unable to read OTPP register\n");
72 return err;
73 }
74
75 err = ab3100_get_register_page_interruptible(ab, AB3100_OTP0,
76 otpval, 8);
77 if (err) {
78 dev_err(otp->dev, "unable to read OTP register page\n");
79 return err;
80 }
81
82 /* Cache OTP properties, they never change by nature */
83 otp->locked = (otpp & 0x80);
84 otp->freq = (otpp & 0x40) ? 32768 : 34100;
85 otp->paf = (otpval[1] & 0x80);
86 otp->imeich = (otpval[1] & 0x40);
87 otp->cid = ((otpval[1] << 8) | otpval[0]) & 0x3fff;
88 otp->tac = ((otpval[4] & 0x0f) << 16) | (otpval[3] << 8) | otpval[2];
89 otp->fac = ((otpval[5] & 0x0f) << 4) | (otpval[4] >> 4);
90 otp->svn = (otpval[7] << 12) | (otpval[6] << 4) | (otpval[5] >> 4);
91 return 0;
92}
93
94/*
95 * This is a simple debugfs human-readable file that dumps out
96 * the contents of the OTP.
97 */
98#ifdef CONFIG_DEBUGFS
99static int show_otp(struct seq_file *s, void *v)
100{
101 struct ab3100_otp *otp = s->private;
102 int err;
103
104 seq_printf(s, "OTP is %s\n", otp->locked ? "LOCKED" : "UNLOCKED");
105 seq_printf(s, "OTP clock switch startup is %uHz\n", otp->freq);
106 seq_printf(s, "PAF is %s\n", otp->paf ? "SET" : "NOT SET");
107 seq_printf(s, "IMEI is %s\n", otp->imeich ?
108 "CHANGEABLE" : "NOT CHANGEABLE");
109 seq_printf(s, "CID: 0x%04x (decimal: %d)\n", otp->cid, otp->cid);
110 seq_printf(s, "IMEI: %u-%u-%u\n", otp->tac, otp->fac, otp->svn);
111 return 0;
112}
113
114static int ab3100_otp_open(struct inode *inode, struct file *file)
115{
116 return single_open(file, ab3100_otp_show, inode->i_private);
117}
118
119static const struct file_operations ab3100_otp_operations = {
120 .open = ab3100_otp_open,
121 .read = seq_read,
122 .llseek = seq_lseek,
123 .release = single_release,
124};
125
126static int __init ab3100_otp_init_debugfs(struct device *dev,
127 struct ab3100_otp *otp)
128{
129 otp->debugfs = debugfs_create_file("ab3100_otp", S_IFREG | S_IRUGO,
130 NULL, otp,
131 &ab3100_otp_operations);
132 if (!otp->debugfs) {
133 dev_err(dev, "AB3100 debugfs OTP file registration failed!\n");
134 return err;
135 }
136}
137
138static void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp)
139{
140 debugfs_remove_file(otp->debugfs);
141}
142#else
143/* Compile this out if debugfs not selected */
144static inline int __init ab3100_otp_init_debugfs(struct device *dev,
145 struct ab3100_otp *otp)
146{
147 return 0;
148}
149
150static inline void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp)
151{
152}
153#endif
154
155#define SHOW_AB3100_ATTR(name) \
156static ssize_t ab3100_otp_##name##_show(struct device *dev, \
157 struct device_attribute *attr, \
158 char *buf) \
159{\
160 struct ab3100_otp *otp = dev_get_drvdata(dev); \
161 return sprintf(buf, "%u\n", otp->name); \
162}
163
164SHOW_AB3100_ATTR(locked)
165SHOW_AB3100_ATTR(freq)
166SHOW_AB3100_ATTR(paf)
167SHOW_AB3100_ATTR(imeich)
168SHOW_AB3100_ATTR(cid)
169SHOW_AB3100_ATTR(fac)
170SHOW_AB3100_ATTR(tac)
171SHOW_AB3100_ATTR(svn)
172
173static struct device_attribute ab3100_otp_attrs[] = {
174 __ATTR(locked, S_IRUGO, ab3100_otp_locked_show, NULL),
175 __ATTR(freq, S_IRUGO, ab3100_otp_freq_show, NULL),
176 __ATTR(paf, S_IRUGO, ab3100_otp_paf_show, NULL),
177 __ATTR(imeich, S_IRUGO, ab3100_otp_imeich_show, NULL),
178 __ATTR(cid, S_IRUGO, ab3100_otp_cid_show, NULL),
179 __ATTR(fac, S_IRUGO, ab3100_otp_fac_show, NULL),
180 __ATTR(tac, S_IRUGO, ab3100_otp_tac_show, NULL),
181 __ATTR(svn, S_IRUGO, ab3100_otp_svn_show, NULL),
182};
183
184static int __init ab3100_otp_probe(struct platform_device *pdev)
185{
186 struct ab3100_otp *otp;
187 int err = 0;
188 int i;
189
190 otp = kzalloc(sizeof(struct ab3100_otp), GFP_KERNEL);
191 if (!otp) {
192 dev_err(&pdev->dev, "could not allocate AB3100 OTP device\n");
193 return -ENOMEM;
194 }
195 otp->dev = &pdev->dev;
196
197 /* Replace platform data coming in with a local struct */
198 otp->ab3100 = platform_get_drvdata(pdev);
199 platform_set_drvdata(pdev, otp);
200
201 err = ab3100_otp_read(otp);
202 if (err)
203 return err;
204
205 dev_info(&pdev->dev, "AB3100 OTP readout registered\n");
206
207 /* sysfs entries */
208 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++) {
209 err = device_create_file(&pdev->dev,
210 &ab3100_otp_attrs[i]);
211 if (err)
212 goto out_no_sysfs;
213 }
214
215 /* debugfs entries */
216 err = ab3100_otp_init_debugfs(&pdev->dev, otp);
217 if (err)
218 goto out_no_debugfs;
219
220 return 0;
221
222out_no_sysfs:
223 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++)
224 device_remove_file(&pdev->dev,
225 &ab3100_otp_attrs[i]);
226out_no_debugfs:
227 kfree(otp);
228 return err;
229}
230
231static int __exit ab3100_otp_remove(struct platform_device *pdev)
232{
233 struct ab3100_otp *otp = platform_get_drvdata(pdev);
234 int i;
235
236 for (i = 0; i < ARRAY_SIZE(ab3100_otp_attrs); i++)
237 device_remove_file(&pdev->dev,
238 &ab3100_otp_attrs[i]);
239 ab3100_otp_exit_debugfs(otp);
240 kfree(otp);
241 return 0;
242}
243
244static struct platform_driver ab3100_otp_driver = {
245 .driver = {
246 .name = "ab3100-otp",
247 .owner = THIS_MODULE,
248 },
249 .remove = __exit_p(ab3100_otp_remove),
250};
251
252static int __init ab3100_otp_init(void)
253{
254 return platform_driver_probe(&ab3100_otp_driver,
255 ab3100_otp_probe);
256}
257
258static void __exit ab3100_otp_exit(void)
259{
260 platform_driver_unregister(&ab3100_otp_driver);
261}
262
263module_init(ab3100_otp_init);
264module_exit(ab3100_otp_exit);
265
266MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
267MODULE_DESCRIPTION("AB3100 OTP Readout Driver");
268MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c
index 5b6e58a3ba46..3d4a861976ca 100644
--- a/drivers/mfd/dm355evm_msp.c
+++ b/drivers/mfd/dm355evm_msp.c
@@ -107,8 +107,16 @@ static const u8 msp_gpios[] = {
107 MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1), 107 MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1),
108 MSP_GPIO(4, SWITCH1), 108 MSP_GPIO(4, SWITCH1),
109 /* switches on MMC/SD sockets */ 109 /* switches on MMC/SD sockets */
110 MSP_GPIO(1, SDMMC), MSP_GPIO(2, SDMMC), /* mmc0 WP, nCD */ 110 /*
111 MSP_GPIO(3, SDMMC), MSP_GPIO(4, SDMMC), /* mmc1 WP, nCD */ 111 * Note: EVMDM355_ECP_VA4.pdf suggests that Bit 2 and 4 should be
112 * checked for card detection. However on the EVM bit 1 and 3 gives
113 * this status, for 0 and 1 instance respectively. The pdf also
114 * suggests that Bit 1 and 3 should be checked for write protection.
115 * However on the EVM bit 2 and 4 gives this status,for 0 and 1
116 * instance respectively.
117 */
118 MSP_GPIO(2, SDMMC), MSP_GPIO(1, SDMMC), /* mmc0 WP, nCD */
119 MSP_GPIO(4, SDMMC), MSP_GPIO(3, SDMMC), /* mmc1 WP, nCD */
112}; 120};
113 121
114#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3) 122#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3)
diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
index c1de4afa89a6..016be4938e4c 100644
--- a/drivers/mfd/ezx-pcap.c
+++ b/drivers/mfd/ezx-pcap.c
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/mfd/ezx-pcap.h> 18#include <linux/mfd/ezx-pcap.h>
19#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
20 21
21#define PCAP_ADC_MAXQ 8 22#define PCAP_ADC_MAXQ 8
22struct pcap_adc_request { 23struct pcap_adc_request {
@@ -106,11 +107,35 @@ int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
106} 107}
107EXPORT_SYMBOL_GPL(ezx_pcap_read); 108EXPORT_SYMBOL_GPL(ezx_pcap_read);
108 109
110int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
111{
112 int ret;
113 u32 tmp = PCAP_REGISTER_READ_OP_BIT |
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
115
116 mutex_lock(&pcap->io_mutex);
117 ret = ezx_pcap_putget(pcap, &tmp);
118 if (ret)
119 goto out_unlock;
120
121 tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
122 tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
124
125 ret = ezx_pcap_putget(pcap, &tmp);
126out_unlock:
127 mutex_unlock(&pcap->io_mutex);
128
129 return ret;
130}
131EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
132
109/* IRQ */ 133/* IRQ */
110static inline unsigned int irq2pcap(struct pcap_chip *pcap, int irq) 134int irq_to_pcap(struct pcap_chip *pcap, int irq)
111{ 135{
112 return 1 << (irq - pcap->irq_base); 136 return irq - pcap->irq_base;
113} 137}
138EXPORT_SYMBOL_GPL(irq_to_pcap);
114 139
115int pcap_to_irq(struct pcap_chip *pcap, int irq) 140int pcap_to_irq(struct pcap_chip *pcap, int irq)
116{ 141{
@@ -122,7 +147,7 @@ static void pcap_mask_irq(unsigned int irq)
122{ 147{
123 struct pcap_chip *pcap = get_irq_chip_data(irq); 148 struct pcap_chip *pcap = get_irq_chip_data(irq);
124 149
125 pcap->msr |= irq2pcap(pcap, irq); 150 pcap->msr |= 1 << irq_to_pcap(pcap, irq);
126 queue_work(pcap->workqueue, &pcap->msr_work); 151 queue_work(pcap->workqueue, &pcap->msr_work);
127} 152}
128 153
@@ -130,7 +155,7 @@ static void pcap_unmask_irq(unsigned int irq)
130{ 155{
131 struct pcap_chip *pcap = get_irq_chip_data(irq); 156 struct pcap_chip *pcap = get_irq_chip_data(irq);
132 157
133 pcap->msr &= ~irq2pcap(pcap, irq); 158 pcap->msr &= ~(1 << irq_to_pcap(pcap, irq));
134 queue_work(pcap->workqueue, &pcap->msr_work); 159 queue_work(pcap->workqueue, &pcap->msr_work);
135} 160}
136 161
@@ -154,34 +179,38 @@ static void pcap_isr_work(struct work_struct *work)
154 u32 msr, isr, int_sel, service; 179 u32 msr, isr, int_sel, service;
155 int irq; 180 int irq;
156 181
157 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); 182 do {
158 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); 183 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
184 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
159 185
160 /* We cant service/ack irqs that are assigned to port 2 */ 186 /* We cant service/ack irqs that are assigned to port 2 */
161 if (!(pdata->config & PCAP_SECOND_PORT)) { 187 if (!(pdata->config & PCAP_SECOND_PORT)) {
162 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); 188 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
163 isr &= ~int_sel; 189 isr &= ~int_sel;
164 } 190 }
165 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
166 191
167 local_irq_disable(); 192 ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
168 service = isr & ~msr; 193 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
169 194
170 for (irq = pcap->irq_base; service; service >>= 1, irq++) { 195 local_irq_disable();
171 if (service & 1) { 196 service = isr & ~msr;
172 struct irq_desc *desc = irq_to_desc(irq); 197 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
198 if (service & 1) {
199 struct irq_desc *desc = irq_to_desc(irq);
173 200
174 if (WARN(!desc, KERN_WARNING 201 if (WARN(!desc, KERN_WARNING
175 "Invalid PCAP IRQ %d\n", irq)) 202 "Invalid PCAP IRQ %d\n", irq))
176 break; 203 break;
177 204
178 if (desc->status & IRQ_DISABLED) 205 if (desc->status & IRQ_DISABLED)
179 note_interrupt(irq, desc, IRQ_NONE); 206 note_interrupt(irq, desc, IRQ_NONE);
180 else 207 else
181 desc->handle_irq(irq, desc); 208 desc->handle_irq(irq, desc);
209 }
182 } 210 }
183 } 211 local_irq_enable();
184 local_irq_enable(); 212 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
213 } while (gpio_get_value(irq_to_gpio(pcap->spi->irq)));
185} 214}
186 215
187static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc) 216static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -194,6 +223,19 @@ static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
194} 223}
195 224
196/* ADC */ 225/* ADC */
226void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
227{
228 u32 tmp;
229
230 mutex_lock(&pcap->adc_mutex);
231 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
232 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
233 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
234 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
235 mutex_unlock(&pcap->adc_mutex);
236}
237EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
238
197static void pcap_disable_adc(struct pcap_chip *pcap) 239static void pcap_disable_adc(struct pcap_chip *pcap)
198{ 240{
199 u32 tmp; 241 u32 tmp;
@@ -216,15 +258,16 @@ static void pcap_adc_trigger(struct pcap_chip *pcap)
216 mutex_unlock(&pcap->adc_mutex); 258 mutex_unlock(&pcap->adc_mutex);
217 return; 259 return;
218 } 260 }
219 mutex_unlock(&pcap->adc_mutex); 261 /* start conversion on requested bank, save TS_M bits */
220 262 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
221 /* start conversion on requested bank */ 263 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
222 tmp = pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; 264 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
223 265
224 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) 266 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
225 tmp |= PCAP_ADC_AD_SEL1; 267 tmp |= PCAP_ADC_AD_SEL1;
226 268
227 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); 269 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
270 mutex_unlock(&pcap->adc_mutex);
228 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); 271 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
229} 272}
230 273
@@ -499,7 +542,7 @@ static void __exit ezx_pcap_exit(void)
499 spi_unregister_driver(&ezxpcap_driver); 542 spi_unregister_driver(&ezxpcap_driver);
500} 543}
501 544
502module_init(ezx_pcap_init); 545subsys_initcall(ezx_pcap_init);
503module_exit(ezx_pcap_exit); 546module_exit(ezx_pcap_exit);
504 547
505MODULE_LICENSE("GPL"); 548MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c
new file mode 100644
index 000000000000..e354d2912ef1
--- /dev/null
+++ b/drivers/mfd/mc13783-core.c
@@ -0,0 +1,427 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This code is in parts based on wm8350-core.c and pcf50633-core.c
5 *
6 * Initial development of this code was funded by
7 * Phytec Messtechnik GmbH, http://www.phytec.de
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/mfd/mc13783-private.h>
25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/completion.h>
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30#include <linux/spi/spi.h>
31#include <linux/uaccess.h>
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/slab.h>
36#include <linux/irq.h>
37
38#define MC13783_MAX_REG_NUM 0x3f
39#define MC13783_FRAME_MASK 0x00ffffff
40#define MC13783_MAX_REG_NUM 0x3f
41#define MC13783_REG_NUM_SHIFT 0x19
42#define MC13783_WRITE_BIT_SHIFT 31
43
44static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
45{
46 struct spi_transfer t = {
47 .tx_buf = (const void *)buf,
48 .rx_buf = buf,
49 .len = len,
50 .cs_change = 0,
51 .delay_usecs = 0,
52 };
53 struct spi_message m;
54
55 spi_message_init(&m);
56 spi_message_add_tail(&t, &m);
57 if (spi_sync(spi, &m) != 0 || m.status != 0)
58 return -EINVAL;
59 return len - m.actual_length;
60}
61
62static int mc13783_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
63{
64 unsigned int frame = 0;
65 int ret = 0;
66
67 if (reg_num > MC13783_MAX_REG_NUM)
68 return -EINVAL;
69
70 frame |= reg_num << MC13783_REG_NUM_SHIFT;
71
72 ret = spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
73
74 *reg_val = frame & MC13783_FRAME_MASK;
75
76 return ret;
77}
78
79static int mc13783_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
80{
81 unsigned int frame = 0;
82
83 if (reg_num > MC13783_MAX_REG_NUM)
84 return -EINVAL;
85
86 frame |= (1 << MC13783_WRITE_BIT_SHIFT);
87 frame |= reg_num << MC13783_REG_NUM_SHIFT;
88 frame |= reg_val & MC13783_FRAME_MASK;
89
90 return spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
91}
92
93int mc13783_reg_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
94{
95 int ret;
96
97 mutex_lock(&mc13783->io_lock);
98 ret = mc13783_read(mc13783, reg_num, reg_val);
99 mutex_unlock(&mc13783->io_lock);
100
101 return ret;
102}
103EXPORT_SYMBOL_GPL(mc13783_reg_read);
104
105int mc13783_reg_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
106{
107 int ret;
108
109 mutex_lock(&mc13783->io_lock);
110 ret = mc13783_write(mc13783, reg_num, reg_val);
111 mutex_unlock(&mc13783->io_lock);
112
113 return ret;
114}
115EXPORT_SYMBOL_GPL(mc13783_reg_write);
116
117/**
118 * mc13783_set_bits - Bitmask write
119 *
120 * @mc13783: Pointer to mc13783 control structure
121 * @reg: Register to access
122 * @mask: Mask of bits to change
123 * @val: Value to set for masked bits
124 */
125int mc13783_set_bits(struct mc13783 *mc13783, int reg, u32 mask, u32 val)
126{
127 u32 tmp;
128 int ret;
129
130 mutex_lock(&mc13783->io_lock);
131
132 ret = mc13783_read(mc13783, reg, &tmp);
133 tmp = (tmp & ~mask) | val;
134 if (ret == 0)
135 ret = mc13783_write(mc13783, reg, tmp);
136
137 mutex_unlock(&mc13783->io_lock);
138
139 return ret;
140}
141EXPORT_SYMBOL_GPL(mc13783_set_bits);
142
143int mc13783_register_irq(struct mc13783 *mc13783, int irq,
144 void (*handler) (int, void *), void *data)
145{
146 if (irq < 0 || irq > MC13783_NUM_IRQ || !handler)
147 return -EINVAL;
148
149 if (WARN_ON(mc13783->irq_handler[irq].handler))
150 return -EBUSY;
151
152 mutex_lock(&mc13783->io_lock);
153 mc13783->irq_handler[irq].handler = handler;
154 mc13783->irq_handler[irq].data = data;
155 mutex_unlock(&mc13783->io_lock);
156
157 return 0;
158}
159EXPORT_SYMBOL_GPL(mc13783_register_irq);
160
161int mc13783_free_irq(struct mc13783 *mc13783, int irq)
162{
163 if (irq < 0 || irq > MC13783_NUM_IRQ)
164 return -EINVAL;
165
166 mutex_lock(&mc13783->io_lock);
167 mc13783->irq_handler[irq].handler = NULL;
168 mutex_unlock(&mc13783->io_lock);
169
170 return 0;
171}
172EXPORT_SYMBOL_GPL(mc13783_free_irq);
173
174static void mc13783_irq_work(struct work_struct *work)
175{
176 struct mc13783 *mc13783 = container_of(work, struct mc13783, work);
177 int i;
178 unsigned int adc_sts;
179
180 /* check if the adc has finished any completion */
181 mc13783_reg_read(mc13783, MC13783_REG_INTERRUPT_STATUS_0, &adc_sts);
182 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0,
183 adc_sts & MC13783_INT_STAT_ADCDONEI);
184
185 if (adc_sts & MC13783_INT_STAT_ADCDONEI)
186 complete_all(&mc13783->adc_done);
187
188 for (i = 0; i < MC13783_NUM_IRQ; i++)
189 if (mc13783->irq_handler[i].handler)
190 mc13783->irq_handler[i].handler(i,
191 mc13783->irq_handler[i].data);
192 enable_irq(mc13783->irq);
193}
194
195static irqreturn_t mc13783_interrupt(int irq, void *dev_id)
196{
197 struct mc13783 *mc13783 = dev_id;
198
199 disable_irq_nosync(irq);
200
201 schedule_work(&mc13783->work);
202 return IRQ_HANDLED;
203}
204
205/* set adc to ts interrupt mode, which generates touchscreen wakeup interrupt */
206static inline void mc13783_adc_set_ts_irq_mode(struct mc13783 *mc13783)
207{
208 unsigned int reg_adc0, reg_adc1;
209
210 reg_adc0 = MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
211 | MC13783_ADC0_TSMOD0;
212 reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN;
213
214 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
215 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
216}
217
218int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
219 unsigned int channel, unsigned int *sample)
220{
221 unsigned int reg_adc0, reg_adc1;
222 int i;
223
224 mutex_lock(&mc13783->adc_conv_lock);
225
226 /* set up auto incrementing anyway to make quick read */
227 reg_adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
228 /* enable the adc, ignore external triggering and set ASC to trigger
229 * conversion */
230 reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN
231 | MC13783_ADC1_ASC;
232
233 /* setup channel number */
234 if (channel > 7)
235 reg_adc1 |= MC13783_ADC1_ADSEL;
236
237 switch (mode) {
238 case MC13783_ADC_MODE_TS:
239 /* enables touch screen reference mode and set touchscreen mode
240 * to position mode */
241 reg_adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
242 | MC13783_ADC0_TSMOD0 | MC13783_ADC0_TSMOD1;
243 reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
244 break;
245 case MC13783_ADC_MODE_SINGLE_CHAN:
246 reg_adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
247 reg_adc1 |= MC13783_ADC1_RAND;
248 break;
249 case MC13783_ADC_MODE_MULT_CHAN:
250 reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
251 break;
252 default:
253 return -EINVAL;
254 }
255
256 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
257 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
258
259 wait_for_completion_interruptible(&mc13783->adc_done);
260
261 for (i = 0; i < 4; i++)
262 mc13783_reg_read(mc13783, MC13783_REG_ADC_2, &sample[i]);
263
264 if (mc13783->ts_active)
265 mc13783_adc_set_ts_irq_mode(mc13783);
266
267 mutex_unlock(&mc13783->adc_conv_lock);
268
269 return 0;
270}
271EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
272
273void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status)
274{
275 mc13783->ts_active = status;
276}
277EXPORT_SYMBOL_GPL(mc13783_adc_set_ts_status);
278
279static int mc13783_check_revision(struct mc13783 *mc13783)
280{
281 u32 rev_id, rev1, rev2, finid, icid;
282
283 mc13783_read(mc13783, MC13783_REG_REVISION, &rev_id);
284
285 rev1 = (rev_id & 0x018) >> 3;
286 rev2 = (rev_id & 0x007);
287 icid = (rev_id & 0x01C0) >> 6;
288 finid = (rev_id & 0x01E00) >> 9;
289
290 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
291 if ((rev1 == 0) && (rev2 == 2))
292 rev1 = 3;
293
294 if (rev1 == 0 || icid != 2) {
295 dev_err(mc13783->dev, "No MC13783 detected.\n");
296 return -ENODEV;
297 }
298
299 mc13783->revision = ((rev1 * 10) + rev2);
300 dev_info(mc13783->dev, "MC13783 Rev %d.%d FinVer %x detected\n", rev1,
301 rev2, finid);
302
303 return 0;
304}
305
306/*
307 * Register a client device. This is non-fatal since there is no need to
308 * fail the entire device init due to a single platform device failing.
309 */
310static void mc13783_client_dev_register(struct mc13783 *mc13783,
311 const char *name)
312{
313 struct mfd_cell cell = {};
314
315 cell.name = name;
316
317 mfd_add_devices(mc13783->dev, -1, &cell, 1, NULL, 0);
318}
319
320static int __devinit mc13783_probe(struct spi_device *spi)
321{
322 struct mc13783 *mc13783;
323 struct mc13783_platform_data *pdata = spi->dev.platform_data;
324 int ret;
325
326 mc13783 = kzalloc(sizeof(struct mc13783), GFP_KERNEL);
327 if (!mc13783)
328 return -ENOMEM;
329
330 dev_set_drvdata(&spi->dev, mc13783);
331 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
332 spi->bits_per_word = 32;
333 spi_setup(spi);
334
335 mc13783->spi_device = spi;
336 mc13783->dev = &spi->dev;
337 mc13783->irq = spi->irq;
338
339 INIT_WORK(&mc13783->work, mc13783_irq_work);
340 mutex_init(&mc13783->io_lock);
341 mutex_init(&mc13783->adc_conv_lock);
342 init_completion(&mc13783->adc_done);
343
344 if (pdata) {
345 mc13783->flags = pdata->flags;
346 mc13783->regulators = pdata->regulators;
347 mc13783->num_regulators = pdata->num_regulators;
348 }
349
350 if (mc13783_check_revision(mc13783)) {
351 ret = -ENODEV;
352 goto err_out;
353 }
354
355 /* clear and mask all interrupts */
356 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0, 0x00ffffff);
357 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_0, 0x00ffffff);
358 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_1, 0x00ffffff);
359 mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_1, 0x00ffffff);
360
361 /* unmask adcdone interrupts */
362 mc13783_set_bits(mc13783, MC13783_REG_INTERRUPT_MASK_0,
363 MC13783_INT_MASK_ADCDONEM, 0);
364
365 ret = request_irq(mc13783->irq, mc13783_interrupt,
366 IRQF_DISABLED | IRQF_TRIGGER_HIGH, "mc13783",
367 mc13783);
368 if (ret)
369 goto err_out;
370
371 if (mc13783->flags & MC13783_USE_CODEC)
372 mc13783_client_dev_register(mc13783, "mc13783-codec");
373 if (mc13783->flags & MC13783_USE_ADC)
374 mc13783_client_dev_register(mc13783, "mc13783-adc");
375 if (mc13783->flags & MC13783_USE_RTC)
376 mc13783_client_dev_register(mc13783, "mc13783-rtc");
377 if (mc13783->flags & MC13783_USE_REGULATOR)
378 mc13783_client_dev_register(mc13783, "mc13783-regulator");
379 if (mc13783->flags & MC13783_USE_TOUCHSCREEN)
380 mc13783_client_dev_register(mc13783, "mc13783-ts");
381
382 return 0;
383
384err_out:
385 kfree(mc13783);
386 return ret;
387}
388
389static int __devexit mc13783_remove(struct spi_device *spi)
390{
391 struct mc13783 *mc13783;
392
393 mc13783 = dev_get_drvdata(&spi->dev);
394
395 free_irq(mc13783->irq, mc13783);
396
397 mfd_remove_devices(&spi->dev);
398
399 return 0;
400}
401
402static struct spi_driver pmic_driver = {
403 .driver = {
404 .name = "mc13783",
405 .bus = &spi_bus_type,
406 .owner = THIS_MODULE,
407 },
408 .probe = mc13783_probe,
409 .remove = __devexit_p(mc13783_remove),
410};
411
412static int __init pmic_init(void)
413{
414 return spi_register_driver(&pmic_driver);
415}
416subsys_initcall(pmic_init);
417
418static void __exit pmic_exit(void)
419{
420 spi_unregister_driver(&pmic_driver);
421}
422module_exit(pmic_exit);
423
424MODULE_DESCRIPTION("Core/Protocol driver for Freescale MC13783 PMIC");
425MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
426MODULE_LICENSE("GPL");
427
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 54ddf3772e0c..ae15e495e20e 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -25,7 +25,7 @@ static int mfd_add_device(struct device *parent, int id,
25 int ret = -ENOMEM; 25 int ret = -ENOMEM;
26 int r; 26 int r;
27 27
28 pdev = platform_device_alloc(cell->name, id); 28 pdev = platform_device_alloc(cell->name, id + cell->id);
29 if (!pdev) 29 if (!pdev)
30 goto fail_alloc; 30 goto fail_alloc;
31 31
diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c
index c2d05becfa97..3d31e97d6a45 100644
--- a/drivers/mfd/pcf50633-adc.c
+++ b/drivers/mfd/pcf50633-adc.c
@@ -73,15 +73,10 @@ static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
73 struct pcf50633_adc *adc = __to_adc(pcf); 73 struct pcf50633_adc *adc = __to_adc(pcf);
74 int head; 74 int head;
75 75
76 mutex_lock(&adc->queue_mutex);
77
78 head = adc->queue_head; 76 head = adc->queue_head;
79 77
80 if (!adc->queue[head]) { 78 if (!adc->queue[head])
81 mutex_unlock(&adc->queue_mutex);
82 return; 79 return;
83 }
84 mutex_unlock(&adc->queue_mutex);
85 80
86 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); 81 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg);
87} 82}
@@ -99,16 +94,17 @@ adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
99 94
100 if (adc->queue[tail]) { 95 if (adc->queue[tail]) {
101 mutex_unlock(&adc->queue_mutex); 96 mutex_unlock(&adc->queue_mutex);
97 dev_err(pcf->dev, "ADC queue is full, dropping request\n");
102 return -EBUSY; 98 return -EBUSY;
103 } 99 }
104 100
105 adc->queue[tail] = req; 101 adc->queue[tail] = req;
102 if (head == tail)
103 trigger_next_adc_job_if_any(pcf);
106 adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1); 104 adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
107 105
108 mutex_unlock(&adc->queue_mutex); 106 mutex_unlock(&adc->queue_mutex);
109 107
110 trigger_next_adc_job_if_any(pcf);
111
112 return 0; 108 return 0;
113} 109}
114 110
@@ -124,6 +120,7 @@ pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result)
124int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) 120int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
125{ 121{
126 struct pcf50633_adc_request *req; 122 struct pcf50633_adc_request *req;
123 int err;
127 124
128 /* req is freed when the result is ready, in interrupt handler */ 125 /* req is freed when the result is ready, in interrupt handler */
129 req = kzalloc(sizeof(*req), GFP_KERNEL); 126 req = kzalloc(sizeof(*req), GFP_KERNEL);
@@ -136,9 +133,13 @@ int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
136 req->callback_param = req; 133 req->callback_param = req;
137 134
138 init_completion(&req->completion); 135 init_completion(&req->completion);
139 adc_enqueue_request(pcf, req); 136 err = adc_enqueue_request(pcf, req);
137 if (err)
138 return err;
139
140 wait_for_completion(&req->completion); 140 wait_for_completion(&req->completion);
141 141
142 /* FIXME by this time req might be already freed */
142 return req->result; 143 return req->result;
143} 144}
144EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read); 145EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
@@ -159,9 +160,7 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
159 req->callback = callback; 160 req->callback = callback;
160 req->callback_param = callback_param; 161 req->callback_param = callback_param;
161 162
162 adc_enqueue_request(pcf, req); 163 return adc_enqueue_request(pcf, req);
163
164 return 0;
165} 164}
166EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); 165EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
167 166
@@ -184,7 +183,7 @@ static void pcf50633_adc_irq(int irq, void *data)
184 struct pcf50633_adc *adc = data; 183 struct pcf50633_adc *adc = data;
185 struct pcf50633 *pcf = adc->pcf; 184 struct pcf50633 *pcf = adc->pcf;
186 struct pcf50633_adc_request *req; 185 struct pcf50633_adc_request *req;
187 int head; 186 int head, res;
188 187
189 mutex_lock(&adc->queue_mutex); 188 mutex_lock(&adc->queue_mutex);
190 head = adc->queue_head; 189 head = adc->queue_head;
@@ -199,12 +198,13 @@ static void pcf50633_adc_irq(int irq, void *data)
199 adc->queue_head = (head + 1) & 198 adc->queue_head = (head + 1) &
200 (PCF50633_MAX_ADC_FIFO_DEPTH - 1); 199 (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
201 200
201 res = adc_result(pcf);
202 trigger_next_adc_job_if_any(pcf);
203
202 mutex_unlock(&adc->queue_mutex); 204 mutex_unlock(&adc->queue_mutex);
203 205
204 req->callback(pcf, req->callback_param, adc_result(pcf)); 206 req->callback(pcf, req->callback_param, res);
205 kfree(req); 207 kfree(req);
206
207 trigger_next_adc_job_if_any(pcf);
208} 208}
209 209
210static int __devinit pcf50633_adc_probe(struct platform_device *pdev) 210static int __devinit pcf50633_adc_probe(struct platform_device *pdev)
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 8d3c38bf9714..d26d7747175e 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -444,7 +444,7 @@ static irqreturn_t pcf50633_irq(int irq, void *data)
444 444
445 get_device(pcf->dev); 445 get_device(pcf->dev);
446 disable_irq_nosync(pcf->irq); 446 disable_irq_nosync(pcf->irq);
447 schedule_work(&pcf->irq_work); 447 queue_work(pcf->work_queue, &pcf->irq_work);
448 448
449 return IRQ_HANDLED; 449 return IRQ_HANDLED;
450} 450}
@@ -575,6 +575,7 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
575 pcf->dev = &client->dev; 575 pcf->dev = &client->dev;
576 pcf->i2c_client = client; 576 pcf->i2c_client = client;
577 pcf->irq = client->irq; 577 pcf->irq = client->irq;
578 pcf->work_queue = create_singlethread_workqueue("pcf50633");
578 579
579 INIT_WORK(&pcf->irq_work, pcf50633_irq_worker); 580 INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
580 581
@@ -651,6 +652,7 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
651 return 0; 652 return 0;
652 653
653err: 654err:
655 destroy_workqueue(pcf->work_queue);
654 kfree(pcf); 656 kfree(pcf);
655 return ret; 657 return ret;
656} 658}
@@ -661,6 +663,7 @@ static int __devexit pcf50633_remove(struct i2c_client *client)
661 int i; 663 int i;
662 664
663 free_irq(pcf->irq, pcf); 665 free_irq(pcf->irq, pcf);
666 destroy_workqueue(pcf->work_queue);
664 667
665 platform_device_unregister(pcf->input_pdev); 668 platform_device_unregister(pcf->input_pdev);
666 platform_device_unregister(pcf->rtc_pdev); 669 platform_device_unregister(pcf->rtc_pdev);
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
index ca54996ffd0e..e424cf6d8e9e 100644
--- a/drivers/mfd/twl4030-core.c
+++ b/drivers/mfd/twl4030-core.c
@@ -89,6 +89,12 @@
89#define twl_has_madc() false 89#define twl_has_madc() false
90#endif 90#endif
91 91
92#ifdef CONFIG_TWL4030_POWER
93#define twl_has_power() true
94#else
95#define twl_has_power() false
96#endif
97
92#if defined(CONFIG_RTC_DRV_TWL4030) || defined(CONFIG_RTC_DRV_TWL4030_MODULE) 98#if defined(CONFIG_RTC_DRV_TWL4030) || defined(CONFIG_RTC_DRV_TWL4030_MODULE)
93#define twl_has_rtc() true 99#define twl_has_rtc() true
94#else 100#else
@@ -115,6 +121,12 @@
115 121
116#define TWL4030_NUM_SLAVES 4 122#define TWL4030_NUM_SLAVES 4
117 123
124#if defined(CONFIG_INPUT_TWL4030_PWRBUTTON) \
125 || defined(CONFIG_INPUT_TWL4030_PWBUTTON_MODULE)
126#define twl_has_pwrbutton() true
127#else
128#define twl_has_pwrbutton() false
129#endif
118 130
119/* Base Address defns for twl4030_map[] */ 131/* Base Address defns for twl4030_map[] */
120 132
@@ -538,6 +550,13 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
538 return PTR_ERR(child); 550 return PTR_ERR(child);
539 } 551 }
540 552
553 if (twl_has_pwrbutton()) {
554 child = add_child(1, "twl4030_pwrbutton",
555 NULL, 0, true, pdata->irq_base + 8 + 0, 0);
556 if (IS_ERR(child))
557 return PTR_ERR(child);
558 }
559
541 if (twl_has_regulator()) { 560 if (twl_has_regulator()) {
542 /* 561 /*
543 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1); 562 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1);
@@ -788,6 +807,10 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id)
788 /* setup clock framework */ 807 /* setup clock framework */
789 clocks_init(&client->dev); 808 clocks_init(&client->dev);
790 809
810 /* load power event scripts */
811 if (twl_has_power() && pdata->power)
812 twl4030_power_init(pdata->power);
813
791 /* Maybe init the T2 Interrupt subsystem */ 814 /* Maybe init the T2 Interrupt subsystem */
792 if (client->irq 815 if (client->irq
793 && pdata->irq_base 816 && pdata->irq_base
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index 7d430835655f..fb194fe244c1 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -424,7 +424,7 @@ static void twl4030_sih_do_edge(struct work_struct *work)
424 /* see what work we have */ 424 /* see what work we have */
425 spin_lock_irq(&sih_agent_lock); 425 spin_lock_irq(&sih_agent_lock);
426 edge_change = agent->edge_change; 426 edge_change = agent->edge_change;
427 agent->edge_change = 0;; 427 agent->edge_change = 0;
428 sih = edge_change ? agent->sih : NULL; 428 sih = edge_change ? agent->sih : NULL;
429 spin_unlock_irq(&sih_agent_lock); 429 spin_unlock_irq(&sih_agent_lock);
430 if (!sih) 430 if (!sih)
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
new file mode 100644
index 000000000000..d423e0c4176b
--- /dev/null
+++ b/drivers/mfd/twl4030-power.c
@@ -0,0 +1,472 @@
1/*
2 * linux/drivers/i2c/chips/twl4030-power.c
3 *
4 * Handle TWL4030 Power initialization
5 *
6 * Copyright (C) 2008 Nokia Corporation
7 * Copyright (C) 2006 Texas Instruments, Inc
8 *
9 * Written by Kalle Jokiniemi
10 * Peter De Schrijver <peter.de-schrijver@nokia.com>
11 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file "COPYING" in the main directory of this
15 * archive for more details.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <linux/module.h>
28#include <linux/pm.h>
29#include <linux/i2c/twl4030.h>
30#include <linux/platform_device.h>
31
32#include <asm/mach-types.h>
33
34static u8 twl4030_start_script_address = 0x2b;
35
36#define PWR_P1_SW_EVENTS 0x10
37#define PWR_DEVOFF (1<<0)
38
39#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
40#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
41
42/* resource - hfclk */
43#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
44
45/* PM events */
46#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
47#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
48#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
49#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
50#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
51#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
52
53#define LVL_WAKEUP 0x08
54
55#define ENABLE_WARMRESET (1<<4)
56
57#define END_OF_SCRIPT 0x3f
58
59#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
60#define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
61#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
62#define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
63#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
64#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
65
66#define R_PROTECT_KEY 0x0E
67#define R_KEY_1 0xC0
68#define R_KEY_2 0x0C
69
70/* resource configuration registers */
71
72#define DEVGROUP_OFFSET 0
73#define TYPE_OFFSET 1
74
75/* Bit positions */
76#define DEVGROUP_SHIFT 5
77#define DEVGROUP_MASK (7 << DEVGROUP_SHIFT)
78#define TYPE_SHIFT 0
79#define TYPE_MASK (7 << TYPE_SHIFT)
80#define TYPE2_SHIFT 3
81#define TYPE2_MASK (3 << TYPE2_SHIFT)
82
83static u8 res_config_addrs[] = {
84 [RES_VAUX1] = 0x17,
85 [RES_VAUX2] = 0x1b,
86 [RES_VAUX3] = 0x1f,
87 [RES_VAUX4] = 0x23,
88 [RES_VMMC1] = 0x27,
89 [RES_VMMC2] = 0x2b,
90 [RES_VPLL1] = 0x2f,
91 [RES_VPLL2] = 0x33,
92 [RES_VSIM] = 0x37,
93 [RES_VDAC] = 0x3b,
94 [RES_VINTANA1] = 0x3f,
95 [RES_VINTANA2] = 0x43,
96 [RES_VINTDIG] = 0x47,
97 [RES_VIO] = 0x4b,
98 [RES_VDD1] = 0x55,
99 [RES_VDD2] = 0x63,
100 [RES_VUSB_1V5] = 0x71,
101 [RES_VUSB_1V8] = 0x74,
102 [RES_VUSB_3V1] = 0x77,
103 [RES_VUSBCP] = 0x7a,
104 [RES_REGEN] = 0x7f,
105 [RES_NRES_PWRON] = 0x82,
106 [RES_CLKEN] = 0x85,
107 [RES_SYSEN] = 0x88,
108 [RES_HFCLKOUT] = 0x8b,
109 [RES_32KCLKOUT] = 0x8e,
110 [RES_RESET] = 0x91,
111 [RES_Main_Ref] = 0x94,
112};
113
114static int __init twl4030_write_script_byte(u8 address, u8 byte)
115{
116 int err;
117
118 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
119 R_MEMORY_ADDRESS);
120 if (err)
121 goto out;
122 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
123 R_MEMORY_DATA);
124out:
125 return err;
126}
127
128static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
129 u8 delay, u8 next)
130{
131 int err;
132
133 address *= 4;
134 err = twl4030_write_script_byte(address++, pmb_message >> 8);
135 if (err)
136 goto out;
137 err = twl4030_write_script_byte(address++, pmb_message & 0xff);
138 if (err)
139 goto out;
140 err = twl4030_write_script_byte(address++, delay);
141 if (err)
142 goto out;
143 err = twl4030_write_script_byte(address++, next);
144out:
145 return err;
146}
147
148static int __init twl4030_write_script(u8 address, struct twl4030_ins *script,
149 int len)
150{
151 int err;
152
153 for (; len; len--, address++, script++) {
154 if (len == 1) {
155 err = twl4030_write_script_ins(address,
156 script->pmb_message,
157 script->delay,
158 END_OF_SCRIPT);
159 if (err)
160 break;
161 } else {
162 err = twl4030_write_script_ins(address,
163 script->pmb_message,
164 script->delay,
165 address + 1);
166 if (err)
167 break;
168 }
169 }
170 return err;
171}
172
173static int __init twl4030_config_wakeup3_sequence(u8 address)
174{
175 int err;
176 u8 data;
177
178 /* Set SLEEP to ACTIVE SEQ address for P3 */
179 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
180 R_SEQ_ADD_S2A3);
181 if (err)
182 goto out;
183
184 /* P3 LVL_WAKEUP should be on LEVEL */
185 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
186 R_P3_SW_EVENTS);
187 if (err)
188 goto out;
189 data |= LVL_WAKEUP;
190 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
191 R_P3_SW_EVENTS);
192out:
193 if (err)
194 pr_err("TWL4030 wakeup sequence for P3 config error\n");
195 return err;
196}
197
198static int __init twl4030_config_wakeup12_sequence(u8 address)
199{
200 int err = 0;
201 u8 data;
202
203 /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
204 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
205 R_SEQ_ADD_S2A12);
206 if (err)
207 goto out;
208
209 /* P1/P2 LVL_WAKEUP should be on LEVEL */
210 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
211 R_P1_SW_EVENTS);
212 if (err)
213 goto out;
214
215 data |= LVL_WAKEUP;
216 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
217 R_P1_SW_EVENTS);
218 if (err)
219 goto out;
220
221 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
222 R_P2_SW_EVENTS);
223 if (err)
224 goto out;
225
226 data |= LVL_WAKEUP;
227 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
228 R_P2_SW_EVENTS);
229 if (err)
230 goto out;
231
232 if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
233 /* Disabling AC charger effect on sleep-active transitions */
234 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
235 R_CFG_P1_TRANSITION);
236 if (err)
237 goto out;
238 data &= ~(1<<1);
239 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
240 R_CFG_P1_TRANSITION);
241 if (err)
242 goto out;
243 }
244
245out:
246 if (err)
247 pr_err("TWL4030 wakeup sequence for P1 and P2" \
248 "config error\n");
249 return err;
250}
251
252static int __init twl4030_config_sleep_sequence(u8 address)
253{
254 int err;
255
256 /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
257 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
258 R_SEQ_ADD_A2S);
259
260 if (err)
261 pr_err("TWL4030 sleep sequence config error\n");
262
263 return err;
264}
265
266static int __init twl4030_config_warmreset_sequence(u8 address)
267{
268 int err;
269 u8 rd_data;
270
271 /* Set WARM RESET SEQ address for P1 */
272 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
273 R_SEQ_ADD_WARM);
274 if (err)
275 goto out;
276
277 /* P1/P2/P3 enable WARMRESET */
278 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
279 R_P1_SW_EVENTS);
280 if (err)
281 goto out;
282
283 rd_data |= ENABLE_WARMRESET;
284 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
285 R_P1_SW_EVENTS);
286 if (err)
287 goto out;
288
289 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
290 R_P2_SW_EVENTS);
291 if (err)
292 goto out;
293
294 rd_data |= ENABLE_WARMRESET;
295 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
296 R_P2_SW_EVENTS);
297 if (err)
298 goto out;
299
300 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
301 R_P3_SW_EVENTS);
302 if (err)
303 goto out;
304
305 rd_data |= ENABLE_WARMRESET;
306 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
307 R_P3_SW_EVENTS);
308out:
309 if (err)
310 pr_err("TWL4030 warmreset seq config error\n");
311 return err;
312}
313
314static int __init twl4030_configure_resource(struct twl4030_resconfig *rconfig)
315{
316 int rconfig_addr;
317 int err;
318 u8 type;
319 u8 grp;
320
321 if (rconfig->resource > TOTAL_RESOURCES) {
322 pr_err("TWL4030 Resource %d does not exist\n",
323 rconfig->resource);
324 return -EINVAL;
325 }
326
327 rconfig_addr = res_config_addrs[rconfig->resource];
328
329 /* Set resource group */
330 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &grp,
331 rconfig_addr + DEVGROUP_OFFSET);
332 if (err) {
333 pr_err("TWL4030 Resource %d group could not be read\n",
334 rconfig->resource);
335 return err;
336 }
337
338 if (rconfig->devgroup >= 0) {
339 grp &= ~DEVGROUP_MASK;
340 grp |= rconfig->devgroup << DEVGROUP_SHIFT;
341 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
342 grp, rconfig_addr + DEVGROUP_OFFSET);
343 if (err < 0) {
344 pr_err("TWL4030 failed to program devgroup\n");
345 return err;
346 }
347 }
348
349 /* Set resource types */
350 err = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &type,
351 rconfig_addr + TYPE_OFFSET);
352 if (err < 0) {
353 pr_err("TWL4030 Resource %d type could not be read\n",
354 rconfig->resource);
355 return err;
356 }
357
358 if (rconfig->type >= 0) {
359 type &= ~TYPE_MASK;
360 type |= rconfig->type << TYPE_SHIFT;
361 }
362
363 if (rconfig->type2 >= 0) {
364 type &= ~TYPE2_MASK;
365 type |= rconfig->type2 << TYPE2_SHIFT;
366 }
367
368 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
369 type, rconfig_addr + TYPE_OFFSET);
370 if (err < 0) {
371 pr_err("TWL4030 failed to program resource type\n");
372 return err;
373 }
374
375 return 0;
376}
377
378static int __init load_twl4030_script(struct twl4030_script *tscript,
379 u8 address)
380{
381 int err;
382 static int order;
383
384 /* Make sure the script isn't going beyond last valid address (0x3f) */
385 if ((address + tscript->size) > END_OF_SCRIPT) {
386 pr_err("TWL4030 scripts too big error\n");
387 return -EINVAL;
388 }
389
390 err = twl4030_write_script(address, tscript->script, tscript->size);
391 if (err)
392 goto out;
393
394 if (tscript->flags & TWL4030_WRST_SCRIPT) {
395 err = twl4030_config_warmreset_sequence(address);
396 if (err)
397 goto out;
398 }
399 if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
400 err = twl4030_config_wakeup12_sequence(address);
401 if (err)
402 goto out;
403 order = 1;
404 }
405 if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
406 err = twl4030_config_wakeup3_sequence(address);
407 if (err)
408 goto out;
409 }
410 if (tscript->flags & TWL4030_SLEEP_SCRIPT)
411 if (order)
412 pr_warning("TWL4030: Bad order of scripts (sleep "\
413 "script before wakeup) Leads to boot"\
414 "failure on some boards\n");
415 err = twl4030_config_sleep_sequence(address);
416out:
417 return err;
418}
419
420void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
421{
422 int err = 0;
423 int i;
424 struct twl4030_resconfig *resconfig;
425 u8 address = twl4030_start_script_address;
426
427 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_1,
428 R_PROTECT_KEY);
429 if (err)
430 goto unlock;
431
432 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_2,
433 R_PROTECT_KEY);
434 if (err)
435 goto unlock;
436
437 for (i = 0; i < twl4030_scripts->num; i++) {
438 err = load_twl4030_script(twl4030_scripts->scripts[i], address);
439 if (err)
440 goto load;
441 address += twl4030_scripts->scripts[i]->size;
442 }
443
444 resconfig = twl4030_scripts->resource_config;
445 if (resconfig) {
446 while (resconfig->resource) {
447 err = twl4030_configure_resource(resconfig);
448 if (err)
449 goto resource;
450 resconfig++;
451
452 }
453 }
454
455 err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY);
456 if (err)
457 pr_err("TWL4030 Unable to relock registers\n");
458 return;
459
460unlock:
461 if (err)
462 pr_err("TWL4030 Unable to unlock registers\n");
463 return;
464load:
465 if (err)
466 pr_err("TWL4030 failed to load scripts\n");
467 return;
468resource:
469 if (err)
470 pr_err("TWL4030 failed to configure resource\n");
471 return;
472}
diff --git a/drivers/mfd/wm831x-core.c b/drivers/mfd/wm831x-core.c
new file mode 100644
index 000000000000..49b7885c2702
--- /dev/null
+++ b/drivers/mfd/wm831x-core.c
@@ -0,0 +1,1549 @@
1/*
2 * wm831x-core.c -- Device access for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/bcd.h>
19#include <linux/delay.h>
20#include <linux/mfd/core.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/pdata.h>
24#include <linux/mfd/wm831x/irq.h>
25#include <linux/mfd/wm831x/auxadc.h>
26#include <linux/mfd/wm831x/otp.h>
27#include <linux/mfd/wm831x/regulator.h>
28
29/* Current settings - values are 2*2^(reg_val/4) microamps. These are
30 * exported since they are used by multiple drivers.
31 */
32int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL] = {
33 2,
34 2,
35 3,
36 3,
37 4,
38 5,
39 6,
40 7,
41 8,
42 10,
43 11,
44 13,
45 16,
46 19,
47 23,
48 27,
49 32,
50 38,
51 45,
52 54,
53 64,
54 76,
55 91,
56 108,
57 128,
58 152,
59 181,
60 215,
61 256,
62 304,
63 362,
64 431,
65 512,
66 609,
67 724,
68 861,
69 1024,
70 1218,
71 1448,
72 1722,
73 2048,
74 2435,
75 2896,
76 3444,
77 4096,
78 4871,
79 5793,
80 6889,
81 8192,
82 9742,
83 11585,
84 13777,
85 16384,
86 19484,
87 23170,
88 27554,
89};
90EXPORT_SYMBOL_GPL(wm831x_isinkv_values);
91
92enum wm831x_parent {
93 WM8310 = 0,
94 WM8311 = 1,
95 WM8312 = 2,
96};
97
98static int wm831x_reg_locked(struct wm831x *wm831x, unsigned short reg)
99{
100 if (!wm831x->locked)
101 return 0;
102
103 switch (reg) {
104 case WM831X_WATCHDOG:
105 case WM831X_DC4_CONTROL:
106 case WM831X_ON_PIN_CONTROL:
107 case WM831X_BACKUP_CHARGER_CONTROL:
108 case WM831X_CHARGER_CONTROL_1:
109 case WM831X_CHARGER_CONTROL_2:
110 return 1;
111
112 default:
113 return 0;
114 }
115}
116
117/**
118 * wm831x_reg_unlock: Unlock user keyed registers
119 *
120 * The WM831x has a user key preventing writes to particularly
121 * critical registers. This function locks those registers,
122 * allowing writes to them.
123 */
124void wm831x_reg_lock(struct wm831x *wm831x)
125{
126 int ret;
127
128 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
129 if (ret == 0) {
130 dev_vdbg(wm831x->dev, "Registers locked\n");
131
132 mutex_lock(&wm831x->io_lock);
133 WARN_ON(wm831x->locked);
134 wm831x->locked = 1;
135 mutex_unlock(&wm831x->io_lock);
136 } else {
137 dev_err(wm831x->dev, "Failed to lock registers: %d\n", ret);
138 }
139
140}
141EXPORT_SYMBOL_GPL(wm831x_reg_lock);
142
143/**
144 * wm831x_reg_unlock: Unlock user keyed registers
145 *
146 * The WM831x has a user key preventing writes to particularly
147 * critical registers. This function locks those registers,
148 * preventing spurious writes.
149 */
150int wm831x_reg_unlock(struct wm831x *wm831x)
151{
152 int ret;
153
154 /* 0x9716 is the value required to unlock the registers */
155 ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0x9716);
156 if (ret == 0) {
157 dev_vdbg(wm831x->dev, "Registers unlocked\n");
158
159 mutex_lock(&wm831x->io_lock);
160 WARN_ON(!wm831x->locked);
161 wm831x->locked = 0;
162 mutex_unlock(&wm831x->io_lock);
163 }
164
165 return ret;
166}
167EXPORT_SYMBOL_GPL(wm831x_reg_unlock);
168
169static int wm831x_read(struct wm831x *wm831x, unsigned short reg,
170 int bytes, void *dest)
171{
172 int ret, i;
173 u16 *buf = dest;
174
175 BUG_ON(bytes % 2);
176 BUG_ON(bytes <= 0);
177
178 ret = wm831x->read_dev(wm831x, reg, bytes, dest);
179 if (ret < 0)
180 return ret;
181
182 for (i = 0; i < bytes / 2; i++) {
183 buf[i] = be16_to_cpu(buf[i]);
184
185 dev_vdbg(wm831x->dev, "Read %04x from R%d(0x%x)\n",
186 buf[i], reg + i, reg + i);
187 }
188
189 return 0;
190}
191
192/**
193 * wm831x_reg_read: Read a single WM831x register.
194 *
195 * @wm831x: Device to read from.
196 * @reg: Register to read.
197 */
198int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg)
199{
200 unsigned short val;
201 int ret;
202
203 mutex_lock(&wm831x->io_lock);
204
205 ret = wm831x_read(wm831x, reg, 2, &val);
206
207 mutex_unlock(&wm831x->io_lock);
208
209 if (ret < 0)
210 return ret;
211 else
212 return val;
213}
214EXPORT_SYMBOL_GPL(wm831x_reg_read);
215
216/**
217 * wm831x_bulk_read: Read multiple WM831x registers
218 *
219 * @wm831x: Device to read from
220 * @reg: First register
221 * @count: Number of registers
222 * @buf: Buffer to fill.
223 */
224int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
225 int count, u16 *buf)
226{
227 int ret;
228
229 mutex_lock(&wm831x->io_lock);
230
231 ret = wm831x_read(wm831x, reg, count * 2, buf);
232
233 mutex_unlock(&wm831x->io_lock);
234
235 return ret;
236}
237EXPORT_SYMBOL_GPL(wm831x_bulk_read);
238
239static int wm831x_write(struct wm831x *wm831x, unsigned short reg,
240 int bytes, void *src)
241{
242 u16 *buf = src;
243 int i;
244
245 BUG_ON(bytes % 2);
246 BUG_ON(bytes <= 0);
247
248 for (i = 0; i < bytes / 2; i++) {
249 if (wm831x_reg_locked(wm831x, reg))
250 return -EPERM;
251
252 dev_vdbg(wm831x->dev, "Write %04x to R%d(0x%x)\n",
253 buf[i], reg + i, reg + i);
254
255 buf[i] = cpu_to_be16(buf[i]);
256 }
257
258 return wm831x->write_dev(wm831x, reg, bytes, src);
259}
260
261/**
262 * wm831x_reg_write: Write a single WM831x register.
263 *
264 * @wm831x: Device to write to.
265 * @reg: Register to write to.
266 * @val: Value to write.
267 */
268int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
269 unsigned short val)
270{
271 int ret;
272
273 mutex_lock(&wm831x->io_lock);
274
275 ret = wm831x_write(wm831x, reg, 2, &val);
276
277 mutex_unlock(&wm831x->io_lock);
278
279 return ret;
280}
281EXPORT_SYMBOL_GPL(wm831x_reg_write);
282
283/**
284 * wm831x_set_bits: Set the value of a bitfield in a WM831x register
285 *
286 * @wm831x: Device to write to.
287 * @reg: Register to write to.
288 * @mask: Mask of bits to set.
289 * @val: Value to set (unshifted)
290 */
291int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
292 unsigned short mask, unsigned short val)
293{
294 int ret;
295 u16 r;
296
297 mutex_lock(&wm831x->io_lock);
298
299 ret = wm831x_read(wm831x, reg, 2, &r);
300 if (ret < 0)
301 goto out;
302
303 r &= ~mask;
304 r |= val;
305
306 ret = wm831x_write(wm831x, reg, 2, &r);
307
308out:
309 mutex_unlock(&wm831x->io_lock);
310
311 return ret;
312}
313EXPORT_SYMBOL_GPL(wm831x_set_bits);
314
315/**
316 * wm831x_auxadc_read: Read a value from the WM831x AUXADC
317 *
318 * @wm831x: Device to read from.
319 * @input: AUXADC input to read.
320 */
321int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input)
322{
323 int tries = 10;
324 int ret, src;
325
326 mutex_lock(&wm831x->auxadc_lock);
327
328 ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
329 WM831X_AUX_ENA, WM831X_AUX_ENA);
330 if (ret < 0) {
331 dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n", ret);
332 goto out;
333 }
334
335 /* We force a single source at present */
336 src = input;
337 ret = wm831x_reg_write(wm831x, WM831X_AUXADC_SOURCE,
338 1 << src);
339 if (ret < 0) {
340 dev_err(wm831x->dev, "Failed to set AUXADC source: %d\n", ret);
341 goto out;
342 }
343
344 ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
345 WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA);
346 if (ret < 0) {
347 dev_err(wm831x->dev, "Failed to start AUXADC: %d\n", ret);
348 goto disable;
349 }
350
351 do {
352 msleep(1);
353
354 ret = wm831x_reg_read(wm831x, WM831X_AUXADC_CONTROL);
355 if (ret < 0)
356 ret = WM831X_AUX_CVT_ENA;
357 } while ((ret & WM831X_AUX_CVT_ENA) && --tries);
358
359 if (ret & WM831X_AUX_CVT_ENA) {
360 dev_err(wm831x->dev, "Timed out reading AUXADC\n");
361 ret = -EBUSY;
362 goto disable;
363 }
364
365 ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
366 if (ret < 0) {
367 dev_err(wm831x->dev, "Failed to read AUXADC data: %d\n", ret);
368 } else {
369 src = ((ret & WM831X_AUX_DATA_SRC_MASK)
370 >> WM831X_AUX_DATA_SRC_SHIFT) - 1;
371
372 if (src == 14)
373 src = WM831X_AUX_CAL;
374
375 if (src != input) {
376 dev_err(wm831x->dev, "Data from source %d not %d\n",
377 src, input);
378 ret = -EINVAL;
379 } else {
380 ret &= WM831X_AUX_DATA_MASK;
381 }
382 }
383
384disable:
385 wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, WM831X_AUX_ENA, 0);
386out:
387 mutex_unlock(&wm831x->auxadc_lock);
388 return ret;
389}
390EXPORT_SYMBOL_GPL(wm831x_auxadc_read);
391
392/**
393 * wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC
394 *
395 * @wm831x: Device to read from.
396 * @input: AUXADC input to read.
397 */
398int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input)
399{
400 int ret;
401
402 ret = wm831x_auxadc_read(wm831x, input);
403 if (ret < 0)
404 return ret;
405
406 ret *= 1465;
407
408 return ret;
409}
410EXPORT_SYMBOL_GPL(wm831x_auxadc_read_uv);
411
412static struct resource wm831x_dcdc1_resources[] = {
413 {
414 .start = WM831X_DC1_CONTROL_1,
415 .end = WM831X_DC1_DVS_CONTROL,
416 .flags = IORESOURCE_IO,
417 },
418 {
419 .name = "UV",
420 .start = WM831X_IRQ_UV_DC1,
421 .end = WM831X_IRQ_UV_DC1,
422 .flags = IORESOURCE_IRQ,
423 },
424 {
425 .name = "HC",
426 .start = WM831X_IRQ_HC_DC1,
427 .end = WM831X_IRQ_HC_DC1,
428 .flags = IORESOURCE_IRQ,
429 },
430};
431
432
433static struct resource wm831x_dcdc2_resources[] = {
434 {
435 .start = WM831X_DC2_CONTROL_1,
436 .end = WM831X_DC2_DVS_CONTROL,
437 .flags = IORESOURCE_IO,
438 },
439 {
440 .name = "UV",
441 .start = WM831X_IRQ_UV_DC2,
442 .end = WM831X_IRQ_UV_DC2,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .name = "HC",
447 .start = WM831X_IRQ_HC_DC2,
448 .end = WM831X_IRQ_HC_DC2,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static struct resource wm831x_dcdc3_resources[] = {
454 {
455 .start = WM831X_DC3_CONTROL_1,
456 .end = WM831X_DC3_SLEEP_CONTROL,
457 .flags = IORESOURCE_IO,
458 },
459 {
460 .name = "UV",
461 .start = WM831X_IRQ_UV_DC3,
462 .end = WM831X_IRQ_UV_DC3,
463 .flags = IORESOURCE_IRQ,
464 },
465};
466
467static struct resource wm831x_dcdc4_resources[] = {
468 {
469 .start = WM831X_DC4_CONTROL,
470 .end = WM831X_DC4_SLEEP_CONTROL,
471 .flags = IORESOURCE_IO,
472 },
473 {
474 .name = "UV",
475 .start = WM831X_IRQ_UV_DC4,
476 .end = WM831X_IRQ_UV_DC4,
477 .flags = IORESOURCE_IRQ,
478 },
479};
480
481static struct resource wm831x_gpio_resources[] = {
482 {
483 .start = WM831X_IRQ_GPIO_1,
484 .end = WM831X_IRQ_GPIO_16,
485 .flags = IORESOURCE_IRQ,
486 },
487};
488
489static struct resource wm831x_isink1_resources[] = {
490 {
491 .start = WM831X_CURRENT_SINK_1,
492 .end = WM831X_CURRENT_SINK_1,
493 .flags = IORESOURCE_IO,
494 },
495 {
496 .start = WM831X_IRQ_CS1,
497 .end = WM831X_IRQ_CS1,
498 .flags = IORESOURCE_IRQ,
499 },
500};
501
502static struct resource wm831x_isink2_resources[] = {
503 {
504 .start = WM831X_CURRENT_SINK_2,
505 .end = WM831X_CURRENT_SINK_2,
506 .flags = IORESOURCE_IO,
507 },
508 {
509 .start = WM831X_IRQ_CS2,
510 .end = WM831X_IRQ_CS2,
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct resource wm831x_ldo1_resources[] = {
516 {
517 .start = WM831X_LDO1_CONTROL,
518 .end = WM831X_LDO1_SLEEP_CONTROL,
519 .flags = IORESOURCE_IO,
520 },
521 {
522 .name = "UV",
523 .start = WM831X_IRQ_UV_LDO1,
524 .end = WM831X_IRQ_UV_LDO1,
525 .flags = IORESOURCE_IRQ,
526 },
527};
528
529static struct resource wm831x_ldo2_resources[] = {
530 {
531 .start = WM831X_LDO2_CONTROL,
532 .end = WM831X_LDO2_SLEEP_CONTROL,
533 .flags = IORESOURCE_IO,
534 },
535 {
536 .name = "UV",
537 .start = WM831X_IRQ_UV_LDO2,
538 .end = WM831X_IRQ_UV_LDO2,
539 .flags = IORESOURCE_IRQ,
540 },
541};
542
543static struct resource wm831x_ldo3_resources[] = {
544 {
545 .start = WM831X_LDO3_CONTROL,
546 .end = WM831X_LDO3_SLEEP_CONTROL,
547 .flags = IORESOURCE_IO,
548 },
549 {
550 .name = "UV",
551 .start = WM831X_IRQ_UV_LDO3,
552 .end = WM831X_IRQ_UV_LDO3,
553 .flags = IORESOURCE_IRQ,
554 },
555};
556
557static struct resource wm831x_ldo4_resources[] = {
558 {
559 .start = WM831X_LDO4_CONTROL,
560 .end = WM831X_LDO4_SLEEP_CONTROL,
561 .flags = IORESOURCE_IO,
562 },
563 {
564 .name = "UV",
565 .start = WM831X_IRQ_UV_LDO4,
566 .end = WM831X_IRQ_UV_LDO4,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
571static struct resource wm831x_ldo5_resources[] = {
572 {
573 .start = WM831X_LDO5_CONTROL,
574 .end = WM831X_LDO5_SLEEP_CONTROL,
575 .flags = IORESOURCE_IO,
576 },
577 {
578 .name = "UV",
579 .start = WM831X_IRQ_UV_LDO5,
580 .end = WM831X_IRQ_UV_LDO5,
581 .flags = IORESOURCE_IRQ,
582 },
583};
584
585static struct resource wm831x_ldo6_resources[] = {
586 {
587 .start = WM831X_LDO6_CONTROL,
588 .end = WM831X_LDO6_SLEEP_CONTROL,
589 .flags = IORESOURCE_IO,
590 },
591 {
592 .name = "UV",
593 .start = WM831X_IRQ_UV_LDO6,
594 .end = WM831X_IRQ_UV_LDO6,
595 .flags = IORESOURCE_IRQ,
596 },
597};
598
599static struct resource wm831x_ldo7_resources[] = {
600 {
601 .start = WM831X_LDO7_CONTROL,
602 .end = WM831X_LDO7_SLEEP_CONTROL,
603 .flags = IORESOURCE_IO,
604 },
605 {
606 .name = "UV",
607 .start = WM831X_IRQ_UV_LDO7,
608 .end = WM831X_IRQ_UV_LDO7,
609 .flags = IORESOURCE_IRQ,
610 },
611};
612
613static struct resource wm831x_ldo8_resources[] = {
614 {
615 .start = WM831X_LDO8_CONTROL,
616 .end = WM831X_LDO8_SLEEP_CONTROL,
617 .flags = IORESOURCE_IO,
618 },
619 {
620 .name = "UV",
621 .start = WM831X_IRQ_UV_LDO8,
622 .end = WM831X_IRQ_UV_LDO8,
623 .flags = IORESOURCE_IRQ,
624 },
625};
626
627static struct resource wm831x_ldo9_resources[] = {
628 {
629 .start = WM831X_LDO9_CONTROL,
630 .end = WM831X_LDO9_SLEEP_CONTROL,
631 .flags = IORESOURCE_IO,
632 },
633 {
634 .name = "UV",
635 .start = WM831X_IRQ_UV_LDO9,
636 .end = WM831X_IRQ_UV_LDO9,
637 .flags = IORESOURCE_IRQ,
638 },
639};
640
641static struct resource wm831x_ldo10_resources[] = {
642 {
643 .start = WM831X_LDO10_CONTROL,
644 .end = WM831X_LDO10_SLEEP_CONTROL,
645 .flags = IORESOURCE_IO,
646 },
647 {
648 .name = "UV",
649 .start = WM831X_IRQ_UV_LDO10,
650 .end = WM831X_IRQ_UV_LDO10,
651 .flags = IORESOURCE_IRQ,
652 },
653};
654
655static struct resource wm831x_ldo11_resources[] = {
656 {
657 .start = WM831X_LDO11_ON_CONTROL,
658 .end = WM831X_LDO11_SLEEP_CONTROL,
659 .flags = IORESOURCE_IO,
660 },
661};
662
663static struct resource wm831x_on_resources[] = {
664 {
665 .start = WM831X_IRQ_ON,
666 .end = WM831X_IRQ_ON,
667 .flags = IORESOURCE_IRQ,
668 },
669};
670
671
672static struct resource wm831x_power_resources[] = {
673 {
674 .name = "SYSLO",
675 .start = WM831X_IRQ_PPM_SYSLO,
676 .end = WM831X_IRQ_PPM_SYSLO,
677 .flags = IORESOURCE_IRQ,
678 },
679 {
680 .name = "PWR SRC",
681 .start = WM831X_IRQ_PPM_PWR_SRC,
682 .end = WM831X_IRQ_PPM_PWR_SRC,
683 .flags = IORESOURCE_IRQ,
684 },
685 {
686 .name = "USB CURR",
687 .start = WM831X_IRQ_PPM_USB_CURR,
688 .end = WM831X_IRQ_PPM_USB_CURR,
689 .flags = IORESOURCE_IRQ,
690 },
691 {
692 .name = "BATT HOT",
693 .start = WM831X_IRQ_CHG_BATT_HOT,
694 .end = WM831X_IRQ_CHG_BATT_HOT,
695 .flags = IORESOURCE_IRQ,
696 },
697 {
698 .name = "BATT COLD",
699 .start = WM831X_IRQ_CHG_BATT_COLD,
700 .end = WM831X_IRQ_CHG_BATT_COLD,
701 .flags = IORESOURCE_IRQ,
702 },
703 {
704 .name = "BATT FAIL",
705 .start = WM831X_IRQ_CHG_BATT_FAIL,
706 .end = WM831X_IRQ_CHG_BATT_FAIL,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .name = "OV",
711 .start = WM831X_IRQ_CHG_OV,
712 .end = WM831X_IRQ_CHG_OV,
713 .flags = IORESOURCE_IRQ,
714 },
715 {
716 .name = "END",
717 .start = WM831X_IRQ_CHG_END,
718 .end = WM831X_IRQ_CHG_END,
719 .flags = IORESOURCE_IRQ,
720 },
721 {
722 .name = "TO",
723 .start = WM831X_IRQ_CHG_TO,
724 .end = WM831X_IRQ_CHG_TO,
725 .flags = IORESOURCE_IRQ,
726 },
727 {
728 .name = "MODE",
729 .start = WM831X_IRQ_CHG_MODE,
730 .end = WM831X_IRQ_CHG_MODE,
731 .flags = IORESOURCE_IRQ,
732 },
733 {
734 .name = "START",
735 .start = WM831X_IRQ_CHG_START,
736 .end = WM831X_IRQ_CHG_START,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct resource wm831x_rtc_resources[] = {
742 {
743 .name = "PER",
744 .start = WM831X_IRQ_RTC_PER,
745 .end = WM831X_IRQ_RTC_PER,
746 .flags = IORESOURCE_IRQ,
747 },
748 {
749 .name = "ALM",
750 .start = WM831X_IRQ_RTC_ALM,
751 .end = WM831X_IRQ_RTC_ALM,
752 .flags = IORESOURCE_IRQ,
753 },
754};
755
756static struct resource wm831x_status1_resources[] = {
757 {
758 .start = WM831X_STATUS_LED_1,
759 .end = WM831X_STATUS_LED_1,
760 .flags = IORESOURCE_IO,
761 },
762};
763
764static struct resource wm831x_status2_resources[] = {
765 {
766 .start = WM831X_STATUS_LED_2,
767 .end = WM831X_STATUS_LED_2,
768 .flags = IORESOURCE_IO,
769 },
770};
771
772static struct resource wm831x_touch_resources[] = {
773 {
774 .name = "TCHPD",
775 .start = WM831X_IRQ_TCHPD,
776 .end = WM831X_IRQ_TCHPD,
777 .flags = IORESOURCE_IRQ,
778 },
779 {
780 .name = "TCHDATA",
781 .start = WM831X_IRQ_TCHDATA,
782 .end = WM831X_IRQ_TCHDATA,
783 .flags = IORESOURCE_IRQ,
784 },
785};
786
787static struct resource wm831x_wdt_resources[] = {
788 {
789 .start = WM831X_IRQ_WDOG_TO,
790 .end = WM831X_IRQ_WDOG_TO,
791 .flags = IORESOURCE_IRQ,
792 },
793};
794
795static struct mfd_cell wm8310_devs[] = {
796 {
797 .name = "wm831x-buckv",
798 .id = 1,
799 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
800 .resources = wm831x_dcdc1_resources,
801 },
802 {
803 .name = "wm831x-buckv",
804 .id = 2,
805 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
806 .resources = wm831x_dcdc2_resources,
807 },
808 {
809 .name = "wm831x-buckp",
810 .id = 3,
811 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
812 .resources = wm831x_dcdc3_resources,
813 },
814 {
815 .name = "wm831x-boostp",
816 .id = 4,
817 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
818 .resources = wm831x_dcdc4_resources,
819 },
820 {
821 .name = "wm831x-epe",
822 .id = 1,
823 },
824 {
825 .name = "wm831x-epe",
826 .id = 2,
827 },
828 {
829 .name = "wm831x-gpio",
830 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
831 .resources = wm831x_gpio_resources,
832 },
833 {
834 .name = "wm831x-hwmon",
835 },
836 {
837 .name = "wm831x-isink",
838 .id = 1,
839 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
840 .resources = wm831x_isink1_resources,
841 },
842 {
843 .name = "wm831x-isink",
844 .id = 2,
845 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
846 .resources = wm831x_isink2_resources,
847 },
848 {
849 .name = "wm831x-ldo",
850 .id = 1,
851 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
852 .resources = wm831x_ldo1_resources,
853 },
854 {
855 .name = "wm831x-ldo",
856 .id = 2,
857 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
858 .resources = wm831x_ldo2_resources,
859 },
860 {
861 .name = "wm831x-ldo",
862 .id = 3,
863 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
864 .resources = wm831x_ldo3_resources,
865 },
866 {
867 .name = "wm831x-ldo",
868 .id = 4,
869 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
870 .resources = wm831x_ldo4_resources,
871 },
872 {
873 .name = "wm831x-ldo",
874 .id = 5,
875 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
876 .resources = wm831x_ldo5_resources,
877 },
878 {
879 .name = "wm831x-ldo",
880 .id = 6,
881 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
882 .resources = wm831x_ldo6_resources,
883 },
884 {
885 .name = "wm831x-aldo",
886 .id = 7,
887 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
888 .resources = wm831x_ldo7_resources,
889 },
890 {
891 .name = "wm831x-aldo",
892 .id = 8,
893 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
894 .resources = wm831x_ldo8_resources,
895 },
896 {
897 .name = "wm831x-aldo",
898 .id = 9,
899 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
900 .resources = wm831x_ldo9_resources,
901 },
902 {
903 .name = "wm831x-aldo",
904 .id = 10,
905 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
906 .resources = wm831x_ldo10_resources,
907 },
908 {
909 .name = "wm831x-alive-ldo",
910 .id = 11,
911 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
912 .resources = wm831x_ldo11_resources,
913 },
914 {
915 .name = "wm831x-on",
916 .num_resources = ARRAY_SIZE(wm831x_on_resources),
917 .resources = wm831x_on_resources,
918 },
919 {
920 .name = "wm831x-power",
921 .num_resources = ARRAY_SIZE(wm831x_power_resources),
922 .resources = wm831x_power_resources,
923 },
924 {
925 .name = "wm831x-rtc",
926 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
927 .resources = wm831x_rtc_resources,
928 },
929 {
930 .name = "wm831x-status",
931 .id = 1,
932 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
933 .resources = wm831x_status1_resources,
934 },
935 {
936 .name = "wm831x-status",
937 .id = 2,
938 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
939 .resources = wm831x_status2_resources,
940 },
941 {
942 .name = "wm831x-watchdog",
943 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
944 .resources = wm831x_wdt_resources,
945 },
946};
947
948static struct mfd_cell wm8311_devs[] = {
949 {
950 .name = "wm831x-buckv",
951 .id = 1,
952 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
953 .resources = wm831x_dcdc1_resources,
954 },
955 {
956 .name = "wm831x-buckv",
957 .id = 2,
958 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
959 .resources = wm831x_dcdc2_resources,
960 },
961 {
962 .name = "wm831x-buckp",
963 .id = 3,
964 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
965 .resources = wm831x_dcdc3_resources,
966 },
967 {
968 .name = "wm831x-boostp",
969 .id = 4,
970 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
971 .resources = wm831x_dcdc4_resources,
972 },
973 {
974 .name = "wm831x-epe",
975 .id = 1,
976 },
977 {
978 .name = "wm831x-epe",
979 .id = 2,
980 },
981 {
982 .name = "wm831x-gpio",
983 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
984 .resources = wm831x_gpio_resources,
985 },
986 {
987 .name = "wm831x-hwmon",
988 },
989 {
990 .name = "wm831x-isink",
991 .id = 1,
992 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
993 .resources = wm831x_isink1_resources,
994 },
995 {
996 .name = "wm831x-isink",
997 .id = 2,
998 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
999 .resources = wm831x_isink2_resources,
1000 },
1001 {
1002 .name = "wm831x-ldo",
1003 .id = 1,
1004 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1005 .resources = wm831x_ldo1_resources,
1006 },
1007 {
1008 .name = "wm831x-ldo",
1009 .id = 2,
1010 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1011 .resources = wm831x_ldo2_resources,
1012 },
1013 {
1014 .name = "wm831x-ldo",
1015 .id = 3,
1016 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1017 .resources = wm831x_ldo3_resources,
1018 },
1019 {
1020 .name = "wm831x-ldo",
1021 .id = 4,
1022 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1023 .resources = wm831x_ldo4_resources,
1024 },
1025 {
1026 .name = "wm831x-ldo",
1027 .id = 5,
1028 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1029 .resources = wm831x_ldo5_resources,
1030 },
1031 {
1032 .name = "wm831x-aldo",
1033 .id = 7,
1034 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1035 .resources = wm831x_ldo7_resources,
1036 },
1037 {
1038 .name = "wm831x-alive-ldo",
1039 .id = 11,
1040 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1041 .resources = wm831x_ldo11_resources,
1042 },
1043 {
1044 .name = "wm831x-on",
1045 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1046 .resources = wm831x_on_resources,
1047 },
1048 {
1049 .name = "wm831x-power",
1050 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1051 .resources = wm831x_power_resources,
1052 },
1053 {
1054 .name = "wm831x-rtc",
1055 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
1056 .resources = wm831x_rtc_resources,
1057 },
1058 {
1059 .name = "wm831x-status",
1060 .id = 1,
1061 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1062 .resources = wm831x_status1_resources,
1063 },
1064 {
1065 .name = "wm831x-status",
1066 .id = 2,
1067 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1068 .resources = wm831x_status2_resources,
1069 },
1070 {
1071 .name = "wm831x-touch",
1072 .num_resources = ARRAY_SIZE(wm831x_touch_resources),
1073 .resources = wm831x_touch_resources,
1074 },
1075 {
1076 .name = "wm831x-watchdog",
1077 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1078 .resources = wm831x_wdt_resources,
1079 },
1080};
1081
1082static struct mfd_cell wm8312_devs[] = {
1083 {
1084 .name = "wm831x-buckv",
1085 .id = 1,
1086 .num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
1087 .resources = wm831x_dcdc1_resources,
1088 },
1089 {
1090 .name = "wm831x-buckv",
1091 .id = 2,
1092 .num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
1093 .resources = wm831x_dcdc2_resources,
1094 },
1095 {
1096 .name = "wm831x-buckp",
1097 .id = 3,
1098 .num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
1099 .resources = wm831x_dcdc3_resources,
1100 },
1101 {
1102 .name = "wm831x-boostp",
1103 .id = 4,
1104 .num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
1105 .resources = wm831x_dcdc4_resources,
1106 },
1107 {
1108 .name = "wm831x-epe",
1109 .id = 1,
1110 },
1111 {
1112 .name = "wm831x-epe",
1113 .id = 2,
1114 },
1115 {
1116 .name = "wm831x-gpio",
1117 .num_resources = ARRAY_SIZE(wm831x_gpio_resources),
1118 .resources = wm831x_gpio_resources,
1119 },
1120 {
1121 .name = "wm831x-hwmon",
1122 },
1123 {
1124 .name = "wm831x-isink",
1125 .id = 1,
1126 .num_resources = ARRAY_SIZE(wm831x_isink1_resources),
1127 .resources = wm831x_isink1_resources,
1128 },
1129 {
1130 .name = "wm831x-isink",
1131 .id = 2,
1132 .num_resources = ARRAY_SIZE(wm831x_isink2_resources),
1133 .resources = wm831x_isink2_resources,
1134 },
1135 {
1136 .name = "wm831x-ldo",
1137 .id = 1,
1138 .num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
1139 .resources = wm831x_ldo1_resources,
1140 },
1141 {
1142 .name = "wm831x-ldo",
1143 .id = 2,
1144 .num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
1145 .resources = wm831x_ldo2_resources,
1146 },
1147 {
1148 .name = "wm831x-ldo",
1149 .id = 3,
1150 .num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
1151 .resources = wm831x_ldo3_resources,
1152 },
1153 {
1154 .name = "wm831x-ldo",
1155 .id = 4,
1156 .num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
1157 .resources = wm831x_ldo4_resources,
1158 },
1159 {
1160 .name = "wm831x-ldo",
1161 .id = 5,
1162 .num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
1163 .resources = wm831x_ldo5_resources,
1164 },
1165 {
1166 .name = "wm831x-ldo",
1167 .id = 6,
1168 .num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
1169 .resources = wm831x_ldo6_resources,
1170 },
1171 {
1172 .name = "wm831x-aldo",
1173 .id = 7,
1174 .num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
1175 .resources = wm831x_ldo7_resources,
1176 },
1177 {
1178 .name = "wm831x-aldo",
1179 .id = 8,
1180 .num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
1181 .resources = wm831x_ldo8_resources,
1182 },
1183 {
1184 .name = "wm831x-aldo",
1185 .id = 9,
1186 .num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
1187 .resources = wm831x_ldo9_resources,
1188 },
1189 {
1190 .name = "wm831x-aldo",
1191 .id = 10,
1192 .num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
1193 .resources = wm831x_ldo10_resources,
1194 },
1195 {
1196 .name = "wm831x-alive-ldo",
1197 .id = 11,
1198 .num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
1199 .resources = wm831x_ldo11_resources,
1200 },
1201 {
1202 .name = "wm831x-on",
1203 .num_resources = ARRAY_SIZE(wm831x_on_resources),
1204 .resources = wm831x_on_resources,
1205 },
1206 {
1207 .name = "wm831x-power",
1208 .num_resources = ARRAY_SIZE(wm831x_power_resources),
1209 .resources = wm831x_power_resources,
1210 },
1211 {
1212 .name = "wm831x-rtc",
1213 .num_resources = ARRAY_SIZE(wm831x_rtc_resources),
1214 .resources = wm831x_rtc_resources,
1215 },
1216 {
1217 .name = "wm831x-status",
1218 .id = 1,
1219 .num_resources = ARRAY_SIZE(wm831x_status1_resources),
1220 .resources = wm831x_status1_resources,
1221 },
1222 {
1223 .name = "wm831x-status",
1224 .id = 2,
1225 .num_resources = ARRAY_SIZE(wm831x_status2_resources),
1226 .resources = wm831x_status2_resources,
1227 },
1228 {
1229 .name = "wm831x-touch",
1230 .num_resources = ARRAY_SIZE(wm831x_touch_resources),
1231 .resources = wm831x_touch_resources,
1232 },
1233 {
1234 .name = "wm831x-watchdog",
1235 .num_resources = ARRAY_SIZE(wm831x_wdt_resources),
1236 .resources = wm831x_wdt_resources,
1237 },
1238};
1239
1240static struct mfd_cell backlight_devs[] = {
1241 {
1242 .name = "wm831x-backlight",
1243 },
1244};
1245
1246/*
1247 * Instantiate the generic non-control parts of the device.
1248 */
1249static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq)
1250{
1251 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
1252 int rev;
1253 enum wm831x_parent parent;
1254 int ret;
1255
1256 mutex_init(&wm831x->io_lock);
1257 mutex_init(&wm831x->key_lock);
1258 mutex_init(&wm831x->auxadc_lock);
1259 dev_set_drvdata(wm831x->dev, wm831x);
1260
1261 ret = wm831x_reg_read(wm831x, WM831X_PARENT_ID);
1262 if (ret < 0) {
1263 dev_err(wm831x->dev, "Failed to read parent ID: %d\n", ret);
1264 goto err;
1265 }
1266 if (ret != 0x6204) {
1267 dev_err(wm831x->dev, "Device is not a WM831x: ID %x\n", ret);
1268 ret = -EINVAL;
1269 goto err;
1270 }
1271
1272 ret = wm831x_reg_read(wm831x, WM831X_REVISION);
1273 if (ret < 0) {
1274 dev_err(wm831x->dev, "Failed to read revision: %d\n", ret);
1275 goto err;
1276 }
1277 rev = (ret & WM831X_PARENT_REV_MASK) >> WM831X_PARENT_REV_SHIFT;
1278
1279 ret = wm831x_reg_read(wm831x, WM831X_RESET_ID);
1280 if (ret < 0) {
1281 dev_err(wm831x->dev, "Failed to read device ID: %d\n", ret);
1282 goto err;
1283 }
1284
1285 switch (ret) {
1286 case 0x8310:
1287 parent = WM8310;
1288 switch (rev) {
1289 case 0:
1290 dev_info(wm831x->dev, "WM8310 revision %c\n",
1291 'A' + rev);
1292 break;
1293 }
1294 break;
1295
1296 case 0x8311:
1297 parent = WM8311;
1298 switch (rev) {
1299 case 0:
1300 dev_info(wm831x->dev, "WM8311 revision %c\n",
1301 'A' + rev);
1302 break;
1303 }
1304 break;
1305
1306 case 0x8312:
1307 parent = WM8312;
1308 switch (rev) {
1309 case 0:
1310 dev_info(wm831x->dev, "WM8312 revision %c\n",
1311 'A' + rev);
1312 break;
1313 }
1314 break;
1315
1316 case 0:
1317 /* Some engineering samples do not have the ID set,
1318 * rely on the device being registered correctly.
1319 * This will need revisiting for future devices with
1320 * multiple dies.
1321 */
1322 parent = id;
1323 switch (rev) {
1324 case 0:
1325 dev_info(wm831x->dev, "WM831%d ES revision %c\n",
1326 parent, 'A' + rev);
1327 break;
1328 }
1329 break;
1330
1331 default:
1332 dev_err(wm831x->dev, "Unknown WM831x device %04x\n", ret);
1333 ret = -EINVAL;
1334 goto err;
1335 }
1336
1337 /* This will need revisiting in future but is OK for all
1338 * current parts.
1339 */
1340 if (parent != id)
1341 dev_warn(wm831x->dev, "Device was registered as a WM831%lu\n",
1342 id);
1343
1344 /* Bootstrap the user key */
1345 ret = wm831x_reg_read(wm831x, WM831X_SECURITY_KEY);
1346 if (ret < 0) {
1347 dev_err(wm831x->dev, "Failed to read security key: %d\n", ret);
1348 goto err;
1349 }
1350 if (ret != 0) {
1351 dev_warn(wm831x->dev, "Security key had non-zero value %x\n",
1352 ret);
1353 wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
1354 }
1355 wm831x->locked = 1;
1356
1357 if (pdata && pdata->pre_init) {
1358 ret = pdata->pre_init(wm831x);
1359 if (ret != 0) {
1360 dev_err(wm831x->dev, "pre_init() failed: %d\n", ret);
1361 goto err;
1362 }
1363 }
1364
1365 ret = wm831x_irq_init(wm831x, irq);
1366 if (ret != 0)
1367 goto err;
1368
1369 /* The core device is up, instantiate the subdevices. */
1370 switch (parent) {
1371 case WM8310:
1372 ret = mfd_add_devices(wm831x->dev, -1,
1373 wm8310_devs, ARRAY_SIZE(wm8310_devs),
1374 NULL, 0);
1375 break;
1376
1377 case WM8311:
1378 ret = mfd_add_devices(wm831x->dev, -1,
1379 wm8311_devs, ARRAY_SIZE(wm8311_devs),
1380 NULL, 0);
1381 break;
1382
1383 case WM8312:
1384 ret = mfd_add_devices(wm831x->dev, -1,
1385 wm8312_devs, ARRAY_SIZE(wm8312_devs),
1386 NULL, 0);
1387 break;
1388
1389 default:
1390 /* If this happens the bus probe function is buggy */
1391 BUG();
1392 }
1393
1394 if (ret != 0) {
1395 dev_err(wm831x->dev, "Failed to add children\n");
1396 goto err_irq;
1397 }
1398
1399 if (pdata && pdata->backlight) {
1400 /* Treat errors as non-critical */
1401 ret = mfd_add_devices(wm831x->dev, -1, backlight_devs,
1402 ARRAY_SIZE(backlight_devs), NULL, 0);
1403 if (ret < 0)
1404 dev_err(wm831x->dev, "Failed to add backlight: %d\n",
1405 ret);
1406 }
1407
1408 wm831x_otp_init(wm831x);
1409
1410 if (pdata && pdata->post_init) {
1411 ret = pdata->post_init(wm831x);
1412 if (ret != 0) {
1413 dev_err(wm831x->dev, "post_init() failed: %d\n", ret);
1414 goto err_irq;
1415 }
1416 }
1417
1418 return 0;
1419
1420err_irq:
1421 wm831x_irq_exit(wm831x);
1422err:
1423 mfd_remove_devices(wm831x->dev);
1424 kfree(wm831x);
1425 return ret;
1426}
1427
1428static void wm831x_device_exit(struct wm831x *wm831x)
1429{
1430 wm831x_otp_exit(wm831x);
1431 mfd_remove_devices(wm831x->dev);
1432 wm831x_irq_exit(wm831x);
1433 kfree(wm831x);
1434}
1435
1436static int wm831x_i2c_read_device(struct wm831x *wm831x, unsigned short reg,
1437 int bytes, void *dest)
1438{
1439 struct i2c_client *i2c = wm831x->control_data;
1440 int ret;
1441 u16 r = cpu_to_be16(reg);
1442
1443 ret = i2c_master_send(i2c, (unsigned char *)&r, 2);
1444 if (ret < 0)
1445 return ret;
1446 if (ret != 2)
1447 return -EIO;
1448
1449 ret = i2c_master_recv(i2c, dest, bytes);
1450 if (ret < 0)
1451 return ret;
1452 if (ret != bytes)
1453 return -EIO;
1454 return 0;
1455}
1456
1457/* Currently we allocate the write buffer on the stack; this is OK for
1458 * small writes - if we need to do large writes this will need to be
1459 * revised.
1460 */
1461static int wm831x_i2c_write_device(struct wm831x *wm831x, unsigned short reg,
1462 int bytes, void *src)
1463{
1464 struct i2c_client *i2c = wm831x->control_data;
1465 unsigned char msg[bytes + 2];
1466 int ret;
1467
1468 reg = cpu_to_be16(reg);
1469 memcpy(&msg[0], &reg, 2);
1470 memcpy(&msg[2], src, bytes);
1471
1472 ret = i2c_master_send(i2c, msg, bytes + 2);
1473 if (ret < 0)
1474 return ret;
1475 if (ret < bytes + 2)
1476 return -EIO;
1477
1478 return 0;
1479}
1480
1481static int wm831x_i2c_probe(struct i2c_client *i2c,
1482 const struct i2c_device_id *id)
1483{
1484 struct wm831x *wm831x;
1485
1486 wm831x = kzalloc(sizeof(struct wm831x), GFP_KERNEL);
1487 if (wm831x == NULL) {
1488 kfree(i2c);
1489 return -ENOMEM;
1490 }
1491
1492 i2c_set_clientdata(i2c, wm831x);
1493 wm831x->dev = &i2c->dev;
1494 wm831x->control_data = i2c;
1495 wm831x->read_dev = wm831x_i2c_read_device;
1496 wm831x->write_dev = wm831x_i2c_write_device;
1497
1498 return wm831x_device_init(wm831x, id->driver_data, i2c->irq);
1499}
1500
1501static int wm831x_i2c_remove(struct i2c_client *i2c)
1502{
1503 struct wm831x *wm831x = i2c_get_clientdata(i2c);
1504
1505 wm831x_device_exit(wm831x);
1506
1507 return 0;
1508}
1509
1510static const struct i2c_device_id wm831x_i2c_id[] = {
1511 { "wm8310", WM8310 },
1512 { "wm8311", WM8311 },
1513 { "wm8312", WM8312 },
1514 { }
1515};
1516MODULE_DEVICE_TABLE(i2c, wm831x_i2c_id);
1517
1518
1519static struct i2c_driver wm831x_i2c_driver = {
1520 .driver = {
1521 .name = "wm831x",
1522 .owner = THIS_MODULE,
1523 },
1524 .probe = wm831x_i2c_probe,
1525 .remove = wm831x_i2c_remove,
1526 .id_table = wm831x_i2c_id,
1527};
1528
1529static int __init wm831x_i2c_init(void)
1530{
1531 int ret;
1532
1533 ret = i2c_add_driver(&wm831x_i2c_driver);
1534 if (ret != 0)
1535 pr_err("Failed to register wm831x I2C driver: %d\n", ret);
1536
1537 return ret;
1538}
1539subsys_initcall(wm831x_i2c_init);
1540
1541static void __exit wm831x_i2c_exit(void)
1542{
1543 i2c_del_driver(&wm831x_i2c_driver);
1544}
1545module_exit(wm831x_i2c_exit);
1546
1547MODULE_DESCRIPTION("I2C support for the WM831X AudioPlus PMIC");
1548MODULE_LICENSE("GPL");
1549MODULE_AUTHOR("Mark Brown");
diff --git a/drivers/mfd/wm831x-irq.c b/drivers/mfd/wm831x-irq.c
new file mode 100644
index 000000000000..d3015dfb9134
--- /dev/null
+++ b/drivers/mfd/wm831x-irq.c
@@ -0,0 +1,559 @@
1/*
2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/mfd/core.h>
19#include <linux/interrupt.h>
20
21#include <linux/mfd/wm831x/core.h>
22#include <linux/mfd/wm831x/pdata.h>
23#include <linux/mfd/wm831x/irq.h>
24
25#include <linux/delay.h>
26
27/*
28 * Since generic IRQs don't currently support interrupt controllers on
29 * interrupt driven buses we don't use genirq but instead provide an
30 * interface that looks very much like the standard ones. This leads
31 * to some bodges, including storing interrupt handler information in
32 * the static irq_data table we use to look up the data for individual
33 * interrupts, but hopefully won't last too long.
34 */
35
36struct wm831x_irq_data {
37 int primary;
38 int reg;
39 int mask;
40 irq_handler_t handler;
41 void *handler_data;
42};
43
44static struct wm831x_irq_data wm831x_irqs[] = {
45 [WM831X_IRQ_TEMP_THW] = {
46 .primary = WM831X_TEMP_INT,
47 .reg = 1,
48 .mask = WM831X_TEMP_THW_EINT,
49 },
50 [WM831X_IRQ_GPIO_1] = {
51 .primary = WM831X_GP_INT,
52 .reg = 5,
53 .mask = WM831X_GP1_EINT,
54 },
55 [WM831X_IRQ_GPIO_2] = {
56 .primary = WM831X_GP_INT,
57 .reg = 5,
58 .mask = WM831X_GP2_EINT,
59 },
60 [WM831X_IRQ_GPIO_3] = {
61 .primary = WM831X_GP_INT,
62 .reg = 5,
63 .mask = WM831X_GP3_EINT,
64 },
65 [WM831X_IRQ_GPIO_4] = {
66 .primary = WM831X_GP_INT,
67 .reg = 5,
68 .mask = WM831X_GP4_EINT,
69 },
70 [WM831X_IRQ_GPIO_5] = {
71 .primary = WM831X_GP_INT,
72 .reg = 5,
73 .mask = WM831X_GP5_EINT,
74 },
75 [WM831X_IRQ_GPIO_6] = {
76 .primary = WM831X_GP_INT,
77 .reg = 5,
78 .mask = WM831X_GP6_EINT,
79 },
80 [WM831X_IRQ_GPIO_7] = {
81 .primary = WM831X_GP_INT,
82 .reg = 5,
83 .mask = WM831X_GP7_EINT,
84 },
85 [WM831X_IRQ_GPIO_8] = {
86 .primary = WM831X_GP_INT,
87 .reg = 5,
88 .mask = WM831X_GP8_EINT,
89 },
90 [WM831X_IRQ_GPIO_9] = {
91 .primary = WM831X_GP_INT,
92 .reg = 5,
93 .mask = WM831X_GP9_EINT,
94 },
95 [WM831X_IRQ_GPIO_10] = {
96 .primary = WM831X_GP_INT,
97 .reg = 5,
98 .mask = WM831X_GP10_EINT,
99 },
100 [WM831X_IRQ_GPIO_11] = {
101 .primary = WM831X_GP_INT,
102 .reg = 5,
103 .mask = WM831X_GP11_EINT,
104 },
105 [WM831X_IRQ_GPIO_12] = {
106 .primary = WM831X_GP_INT,
107 .reg = 5,
108 .mask = WM831X_GP12_EINT,
109 },
110 [WM831X_IRQ_GPIO_13] = {
111 .primary = WM831X_GP_INT,
112 .reg = 5,
113 .mask = WM831X_GP13_EINT,
114 },
115 [WM831X_IRQ_GPIO_14] = {
116 .primary = WM831X_GP_INT,
117 .reg = 5,
118 .mask = WM831X_GP14_EINT,
119 },
120 [WM831X_IRQ_GPIO_15] = {
121 .primary = WM831X_GP_INT,
122 .reg = 5,
123 .mask = WM831X_GP15_EINT,
124 },
125 [WM831X_IRQ_GPIO_16] = {
126 .primary = WM831X_GP_INT,
127 .reg = 5,
128 .mask = WM831X_GP16_EINT,
129 },
130 [WM831X_IRQ_ON] = {
131 .primary = WM831X_ON_PIN_INT,
132 .reg = 1,
133 .mask = WM831X_ON_PIN_EINT,
134 },
135 [WM831X_IRQ_PPM_SYSLO] = {
136 .primary = WM831X_PPM_INT,
137 .reg = 1,
138 .mask = WM831X_PPM_SYSLO_EINT,
139 },
140 [WM831X_IRQ_PPM_PWR_SRC] = {
141 .primary = WM831X_PPM_INT,
142 .reg = 1,
143 .mask = WM831X_PPM_PWR_SRC_EINT,
144 },
145 [WM831X_IRQ_PPM_USB_CURR] = {
146 .primary = WM831X_PPM_INT,
147 .reg = 1,
148 .mask = WM831X_PPM_USB_CURR_EINT,
149 },
150 [WM831X_IRQ_WDOG_TO] = {
151 .primary = WM831X_WDOG_INT,
152 .reg = 1,
153 .mask = WM831X_WDOG_TO_EINT,
154 },
155 [WM831X_IRQ_RTC_PER] = {
156 .primary = WM831X_RTC_INT,
157 .reg = 1,
158 .mask = WM831X_RTC_PER_EINT,
159 },
160 [WM831X_IRQ_RTC_ALM] = {
161 .primary = WM831X_RTC_INT,
162 .reg = 1,
163 .mask = WM831X_RTC_ALM_EINT,
164 },
165 [WM831X_IRQ_CHG_BATT_HOT] = {
166 .primary = WM831X_CHG_INT,
167 .reg = 2,
168 .mask = WM831X_CHG_BATT_HOT_EINT,
169 },
170 [WM831X_IRQ_CHG_BATT_COLD] = {
171 .primary = WM831X_CHG_INT,
172 .reg = 2,
173 .mask = WM831X_CHG_BATT_COLD_EINT,
174 },
175 [WM831X_IRQ_CHG_BATT_FAIL] = {
176 .primary = WM831X_CHG_INT,
177 .reg = 2,
178 .mask = WM831X_CHG_BATT_FAIL_EINT,
179 },
180 [WM831X_IRQ_CHG_OV] = {
181 .primary = WM831X_CHG_INT,
182 .reg = 2,
183 .mask = WM831X_CHG_OV_EINT,
184 },
185 [WM831X_IRQ_CHG_END] = {
186 .primary = WM831X_CHG_INT,
187 .reg = 2,
188 .mask = WM831X_CHG_END_EINT,
189 },
190 [WM831X_IRQ_CHG_TO] = {
191 .primary = WM831X_CHG_INT,
192 .reg = 2,
193 .mask = WM831X_CHG_TO_EINT,
194 },
195 [WM831X_IRQ_CHG_MODE] = {
196 .primary = WM831X_CHG_INT,
197 .reg = 2,
198 .mask = WM831X_CHG_MODE_EINT,
199 },
200 [WM831X_IRQ_CHG_START] = {
201 .primary = WM831X_CHG_INT,
202 .reg = 2,
203 .mask = WM831X_CHG_START_EINT,
204 },
205 [WM831X_IRQ_TCHDATA] = {
206 .primary = WM831X_TCHDATA_INT,
207 .reg = 1,
208 .mask = WM831X_TCHDATA_EINT,
209 },
210 [WM831X_IRQ_TCHPD] = {
211 .primary = WM831X_TCHPD_INT,
212 .reg = 1,
213 .mask = WM831X_TCHPD_EINT,
214 },
215 [WM831X_IRQ_AUXADC_DATA] = {
216 .primary = WM831X_AUXADC_INT,
217 .reg = 1,
218 .mask = WM831X_AUXADC_DATA_EINT,
219 },
220 [WM831X_IRQ_AUXADC_DCOMP1] = {
221 .primary = WM831X_AUXADC_INT,
222 .reg = 1,
223 .mask = WM831X_AUXADC_DCOMP1_EINT,
224 },
225 [WM831X_IRQ_AUXADC_DCOMP2] = {
226 .primary = WM831X_AUXADC_INT,
227 .reg = 1,
228 .mask = WM831X_AUXADC_DCOMP2_EINT,
229 },
230 [WM831X_IRQ_AUXADC_DCOMP3] = {
231 .primary = WM831X_AUXADC_INT,
232 .reg = 1,
233 .mask = WM831X_AUXADC_DCOMP3_EINT,
234 },
235 [WM831X_IRQ_AUXADC_DCOMP4] = {
236 .primary = WM831X_AUXADC_INT,
237 .reg = 1,
238 .mask = WM831X_AUXADC_DCOMP4_EINT,
239 },
240 [WM831X_IRQ_CS1] = {
241 .primary = WM831X_CS_INT,
242 .reg = 2,
243 .mask = WM831X_CS1_EINT,
244 },
245 [WM831X_IRQ_CS2] = {
246 .primary = WM831X_CS_INT,
247 .reg = 2,
248 .mask = WM831X_CS2_EINT,
249 },
250 [WM831X_IRQ_HC_DC1] = {
251 .primary = WM831X_HC_INT,
252 .reg = 4,
253 .mask = WM831X_HC_DC1_EINT,
254 },
255 [WM831X_IRQ_HC_DC2] = {
256 .primary = WM831X_HC_INT,
257 .reg = 4,
258 .mask = WM831X_HC_DC2_EINT,
259 },
260 [WM831X_IRQ_UV_LDO1] = {
261 .primary = WM831X_UV_INT,
262 .reg = 3,
263 .mask = WM831X_UV_LDO1_EINT,
264 },
265 [WM831X_IRQ_UV_LDO2] = {
266 .primary = WM831X_UV_INT,
267 .reg = 3,
268 .mask = WM831X_UV_LDO2_EINT,
269 },
270 [WM831X_IRQ_UV_LDO3] = {
271 .primary = WM831X_UV_INT,
272 .reg = 3,
273 .mask = WM831X_UV_LDO3_EINT,
274 },
275 [WM831X_IRQ_UV_LDO4] = {
276 .primary = WM831X_UV_INT,
277 .reg = 3,
278 .mask = WM831X_UV_LDO4_EINT,
279 },
280 [WM831X_IRQ_UV_LDO5] = {
281 .primary = WM831X_UV_INT,
282 .reg = 3,
283 .mask = WM831X_UV_LDO5_EINT,
284 },
285 [WM831X_IRQ_UV_LDO6] = {
286 .primary = WM831X_UV_INT,
287 .reg = 3,
288 .mask = WM831X_UV_LDO6_EINT,
289 },
290 [WM831X_IRQ_UV_LDO7] = {
291 .primary = WM831X_UV_INT,
292 .reg = 3,
293 .mask = WM831X_UV_LDO7_EINT,
294 },
295 [WM831X_IRQ_UV_LDO8] = {
296 .primary = WM831X_UV_INT,
297 .reg = 3,
298 .mask = WM831X_UV_LDO8_EINT,
299 },
300 [WM831X_IRQ_UV_LDO9] = {
301 .primary = WM831X_UV_INT,
302 .reg = 3,
303 .mask = WM831X_UV_LDO9_EINT,
304 },
305 [WM831X_IRQ_UV_LDO10] = {
306 .primary = WM831X_UV_INT,
307 .reg = 3,
308 .mask = WM831X_UV_LDO10_EINT,
309 },
310 [WM831X_IRQ_UV_DC1] = {
311 .primary = WM831X_UV_INT,
312 .reg = 4,
313 .mask = WM831X_UV_DC1_EINT,
314 },
315 [WM831X_IRQ_UV_DC2] = {
316 .primary = WM831X_UV_INT,
317 .reg = 4,
318 .mask = WM831X_UV_DC2_EINT,
319 },
320 [WM831X_IRQ_UV_DC3] = {
321 .primary = WM831X_UV_INT,
322 .reg = 4,
323 .mask = WM831X_UV_DC3_EINT,
324 },
325 [WM831X_IRQ_UV_DC4] = {
326 .primary = WM831X_UV_INT,
327 .reg = 4,
328 .mask = WM831X_UV_DC4_EINT,
329 },
330};
331
332static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
333{
334 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
335}
336
337static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
338{
339 return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
340}
341
342static void __wm831x_enable_irq(struct wm831x *wm831x, int irq)
343{
344 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
345
346 wm831x->irq_masks[irq_data->reg - 1] &= ~irq_data->mask;
347 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
348 wm831x->irq_masks[irq_data->reg - 1]);
349}
350
351void wm831x_enable_irq(struct wm831x *wm831x, int irq)
352{
353 mutex_lock(&wm831x->irq_lock);
354 __wm831x_enable_irq(wm831x, irq);
355 mutex_unlock(&wm831x->irq_lock);
356}
357EXPORT_SYMBOL_GPL(wm831x_enable_irq);
358
359static void __wm831x_disable_irq(struct wm831x *wm831x, int irq)
360{
361 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
362
363 wm831x->irq_masks[irq_data->reg - 1] |= irq_data->mask;
364 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
365 wm831x->irq_masks[irq_data->reg - 1]);
366}
367
368void wm831x_disable_irq(struct wm831x *wm831x, int irq)
369{
370 mutex_lock(&wm831x->irq_lock);
371 __wm831x_disable_irq(wm831x, irq);
372 mutex_unlock(&wm831x->irq_lock);
373}
374EXPORT_SYMBOL_GPL(wm831x_disable_irq);
375
376int wm831x_request_irq(struct wm831x *wm831x,
377 unsigned int irq, irq_handler_t handler,
378 unsigned long flags, const char *name,
379 void *dev)
380{
381 int ret = 0;
382
383 if (irq < 0 || irq >= WM831X_NUM_IRQS)
384 return -EINVAL;
385
386 mutex_lock(&wm831x->irq_lock);
387
388 if (wm831x_irqs[irq].handler) {
389 dev_err(wm831x->dev, "Already have handler for IRQ %d\n", irq);
390 ret = -EINVAL;
391 goto out;
392 }
393
394 wm831x_irqs[irq].handler = handler;
395 wm831x_irqs[irq].handler_data = dev;
396
397 __wm831x_enable_irq(wm831x, irq);
398
399out:
400 mutex_unlock(&wm831x->irq_lock);
401
402 return ret;
403}
404EXPORT_SYMBOL_GPL(wm831x_request_irq);
405
406void wm831x_free_irq(struct wm831x *wm831x, unsigned int irq, void *data)
407{
408 if (irq < 0 || irq >= WM831X_NUM_IRQS)
409 return;
410
411 mutex_lock(&wm831x->irq_lock);
412
413 wm831x_irqs[irq].handler = NULL;
414 wm831x_irqs[irq].handler_data = NULL;
415
416 __wm831x_disable_irq(wm831x, irq);
417
418 mutex_unlock(&wm831x->irq_lock);
419}
420EXPORT_SYMBOL_GPL(wm831x_free_irq);
421
422
423static void wm831x_handle_irq(struct wm831x *wm831x, int irq, int status)
424{
425 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
426
427 if (irq_data->handler) {
428 irq_data->handler(irq, irq_data->handler_data);
429 wm831x_reg_write(wm831x, irq_data_to_status_reg(irq_data),
430 irq_data->mask);
431 } else {
432 dev_err(wm831x->dev, "Unhandled IRQ %d, masking\n", irq);
433 __wm831x_disable_irq(wm831x, irq);
434 }
435}
436
437/* Main interrupt handling occurs in a workqueue since we need
438 * interrupts enabled to interact with the chip. */
439static void wm831x_irq_worker(struct work_struct *work)
440{
441 struct wm831x *wm831x = container_of(work, struct wm831x, irq_work);
442 unsigned int i;
443 int primary;
444 int status_regs[5];
445 int read[5] = { 0 };
446 int *status;
447
448 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
449 if (primary < 0) {
450 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
451 primary);
452 goto out;
453 }
454
455 mutex_lock(&wm831x->irq_lock);
456
457 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
458 int offset = wm831x_irqs[i].reg - 1;
459
460 if (!(primary & wm831x_irqs[i].primary))
461 continue;
462
463 status = &status_regs[offset];
464
465 /* Hopefully there should only be one register to read
466 * each time otherwise we ought to do a block read. */
467 if (!read[offset]) {
468 *status = wm831x_reg_read(wm831x,
469 irq_data_to_status_reg(&wm831x_irqs[i]));
470 if (*status < 0) {
471 dev_err(wm831x->dev,
472 "Failed to read IRQ status: %d\n",
473 *status);
474 goto out_lock;
475 }
476
477 /* Mask out the disabled IRQs */
478 *status &= ~wm831x->irq_masks[offset];
479 read[offset] = 1;
480 }
481
482 if (*status & wm831x_irqs[i].mask)
483 wm831x_handle_irq(wm831x, i, *status);
484 }
485
486out_lock:
487 mutex_unlock(&wm831x->irq_lock);
488out:
489 enable_irq(wm831x->irq);
490}
491
492
493static irqreturn_t wm831x_cpu_irq(int irq, void *data)
494{
495 struct wm831x *wm831x = data;
496
497 /* Shut the interrupt to the CPU up and schedule the actual
498 * handler; we can't check that the IRQ is asserted. */
499 disable_irq_nosync(irq);
500
501 queue_work(wm831x->irq_wq, &wm831x->irq_work);
502
503 return IRQ_HANDLED;
504}
505
506int wm831x_irq_init(struct wm831x *wm831x, int irq)
507{
508 int i, ret;
509
510 if (!irq) {
511 dev_warn(wm831x->dev,
512 "No interrupt specified - functionality limited\n");
513 return 0;
514 }
515
516
517 wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq");
518 if (!wm831x->irq_wq) {
519 dev_err(wm831x->dev, "Failed to allocate IRQ worker\n");
520 return -ESRCH;
521 }
522
523 wm831x->irq = irq;
524 mutex_init(&wm831x->irq_lock);
525 INIT_WORK(&wm831x->irq_work, wm831x_irq_worker);
526
527 /* Mask the individual interrupt sources */
528 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks); i++) {
529 wm831x->irq_masks[i] = 0xffff;
530 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
531 0xffff);
532 }
533
534 /* Enable top level interrupts, we mask at secondary level */
535 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
536
537 /* We're good to go. We set IRQF_SHARED since there's a
538 * chance the driver will interoperate with another driver but
539 * the need to disable the IRQ while handing via I2C/SPI means
540 * that this may break and performance will be impacted. If
541 * this does happen it's a hardware design issue and the only
542 * other alternative would be polling.
543 */
544 ret = request_irq(irq, wm831x_cpu_irq, IRQF_TRIGGER_LOW | IRQF_SHARED,
545 "wm831x", wm831x);
546 if (ret != 0) {
547 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
548 irq, ret);
549 return ret;
550 }
551
552 return 0;
553}
554
555void wm831x_irq_exit(struct wm831x *wm831x)
556{
557 if (wm831x->irq)
558 free_irq(wm831x->irq, wm831x);
559}
diff --git a/drivers/mfd/wm831x-otp.c b/drivers/mfd/wm831x-otp.c
new file mode 100644
index 000000000000..f742745ff354
--- /dev/null
+++ b/drivers/mfd/wm831x-otp.c
@@ -0,0 +1,83 @@
1/*
2 * wm831x-otp.c -- OTP for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/bcd.h>
19#include <linux/delay.h>
20#include <linux/mfd/core.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/otp.h>
24
25/* In bytes */
26#define WM831X_UNIQUE_ID_LEN 16
27
28/* Read the unique ID from the chip into id */
29static int wm831x_unique_id_read(struct wm831x *wm831x, char *id)
30{
31 int i, val;
32
33 for (i = 0; i < WM831X_UNIQUE_ID_LEN / 2; i++) {
34 val = wm831x_reg_read(wm831x, WM831X_UNIQUE_ID_1 + i);
35 if (val < 0)
36 return val;
37
38 id[i * 2] = (val >> 8) & 0xff;
39 id[(i * 2) + 1] = val & 0xff;
40 }
41
42 return 0;
43}
44
45static ssize_t wm831x_unique_id_show(struct device *dev,
46 struct device_attribute *attr, char *buf)
47{
48 struct wm831x *wm831x = dev_get_drvdata(dev);
49 int i, rval;
50 char id[WM831X_UNIQUE_ID_LEN];
51 ssize_t ret = 0;
52
53 rval = wm831x_unique_id_read(wm831x, id);
54 if (rval < 0)
55 return 0;
56
57 for (i = 0; i < WM831X_UNIQUE_ID_LEN; i++)
58 ret += sprintf(&buf[ret], "%02x", buf[i]);
59
60 ret += sprintf(&buf[ret], "\n");
61
62 return ret;
63}
64
65static DEVICE_ATTR(unique_id, 0444, wm831x_unique_id_show, NULL);
66
67int wm831x_otp_init(struct wm831x *wm831x)
68{
69 int ret;
70
71 ret = device_create_file(wm831x->dev, &dev_attr_unique_id);
72 if (ret != 0)
73 dev_err(wm831x->dev, "Unique ID attribute not created: %d\n",
74 ret);
75
76 return ret;
77}
78
79void wm831x_otp_exit(struct wm831x *wm831x)
80{
81 device_remove_file(wm831x->dev, &dev_attr_unique_id);
82}
83
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index fe24079387c5..ba27c9dc1ad3 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -353,15 +353,15 @@ static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
353} 353}
354 354
355/* 355/*
356 * wm8350_irq_worker actually handles the interrupts. Since all 356 * This is a threaded IRQ handler so can access I2C/SPI. Since all
357 * interrupts are clear on read the IRQ line will be reasserted and 357 * interrupts are clear on read the IRQ line will be reasserted and
358 * the physical IRQ will be handled again if another interrupt is 358 * the physical IRQ will be handled again if another interrupt is
359 * asserted while we run - in the normal course of events this is a 359 * asserted while we run - in the normal course of events this is a
360 * rare occurrence so we save I2C/SPI reads. 360 * rare occurrence so we save I2C/SPI reads.
361 */ 361 */
362static void wm8350_irq_worker(struct work_struct *work) 362static irqreturn_t wm8350_irq(int irq, void *data)
363{ 363{
364 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work); 364 struct wm8350 *wm8350 = data;
365 u16 level_one, status1, status2, comp; 365 u16 level_one, status1, status2, comp;
366 366
367 /* TODO: Use block reads to improve performance? */ 367 /* TODO: Use block reads to improve performance? */
@@ -552,16 +552,6 @@ static void wm8350_irq_worker(struct work_struct *work)
552 } 552 }
553 } 553 }
554 554
555 enable_irq(wm8350->chip_irq);
556}
557
558static irqreturn_t wm8350_irq(int irq, void *data)
559{
560 struct wm8350 *wm8350 = data;
561
562 disable_irq_nosync(irq);
563 schedule_work(&wm8350->irq_work);
564
565 return IRQ_HANDLED; 555 return IRQ_HANDLED;
566} 556}
567 557
@@ -1428,9 +1418,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1428 1418
1429 mutex_init(&wm8350->auxadc_mutex); 1419 mutex_init(&wm8350->auxadc_mutex);
1430 mutex_init(&wm8350->irq_mutex); 1420 mutex_init(&wm8350->irq_mutex);
1431 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1432 if (irq) { 1421 if (irq) {
1433 int flags = 0; 1422 int flags = IRQF_ONESHOT;
1434 1423
1435 if (pdata && pdata->irq_high) { 1424 if (pdata && pdata->irq_high) {
1436 flags |= IRQF_TRIGGER_HIGH; 1425 flags |= IRQF_TRIGGER_HIGH;
@@ -1444,8 +1433,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1444 WM8350_IRQ_POL); 1433 WM8350_IRQ_POL);
1445 } 1434 }
1446 1435
1447 ret = request_irq(irq, wm8350_irq, flags, 1436 ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
1448 "wm8350", wm8350); 1437 "wm8350", wm8350);
1449 if (ret != 0) { 1438 if (ret != 0) {
1450 dev_err(wm8350->dev, "Failed to request IRQ: %d\n", 1439 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1451 ret); 1440 ret);
@@ -1472,6 +1461,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1472 &(wm8350->codec.pdev)); 1461 &(wm8350->codec.pdev));
1473 wm8350_client_dev_register(wm8350, "wm8350-gpio", 1462 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1474 &(wm8350->gpio.pdev)); 1463 &(wm8350->gpio.pdev));
1464 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
1465 &(wm8350->hwmon.pdev));
1475 wm8350_client_dev_register(wm8350, "wm8350-power", 1466 wm8350_client_dev_register(wm8350, "wm8350-power",
1476 &(wm8350->power.pdev)); 1467 &(wm8350->power.pdev));
1477 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev)); 1468 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
@@ -1498,11 +1489,11 @@ void wm8350_device_exit(struct wm8350 *wm8350)
1498 platform_device_unregister(wm8350->wdt.pdev); 1489 platform_device_unregister(wm8350->wdt.pdev);
1499 platform_device_unregister(wm8350->rtc.pdev); 1490 platform_device_unregister(wm8350->rtc.pdev);
1500 platform_device_unregister(wm8350->power.pdev); 1491 platform_device_unregister(wm8350->power.pdev);
1492 platform_device_unregister(wm8350->hwmon.pdev);
1501 platform_device_unregister(wm8350->gpio.pdev); 1493 platform_device_unregister(wm8350->gpio.pdev);
1502 platform_device_unregister(wm8350->codec.pdev); 1494 platform_device_unregister(wm8350->codec.pdev);
1503 1495
1504 free_irq(wm8350->chip_irq, wm8350); 1496 free_irq(wm8350->chip_irq, wm8350);
1505 flush_work(&wm8350->irq_work);
1506 kfree(wm8350->reg_cache); 1497 kfree(wm8350->reg_cache);
1507} 1498}
1508EXPORT_SYMBOL_GPL(wm8350_device_exit); 1499EXPORT_SYMBOL_GPL(wm8350_device_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 11:00:43 -0500