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-rw-r--r--drivers/mfd/Kconfig66
-rw-r--r--drivers/mfd/Makefile7
-rw-r--r--drivers/mfd/asic3.c6
-rw-r--r--drivers/mfd/da903x.c16
-rw-r--r--drivers/mfd/dm355evm_msp.c420
-rw-r--r--drivers/mfd/mcp-core.c2
-rw-r--r--drivers/mfd/mcp-sa11x0.c2
-rw-r--r--drivers/mfd/menelaus.c1285
-rw-r--r--drivers/mfd/mfd-core.c1
-rw-r--r--drivers/mfd/tps65010.c1072
-rw-r--r--drivers/mfd/twl4030-core.c472
-rw-r--r--drivers/mfd/twl4030-irq.c30
-rw-r--r--drivers/mfd/ucb1x00-assabet.c2
-rw-r--r--drivers/mfd/ucb1x00-core.c2
-rw-r--r--drivers/mfd/ucb1x00-ts.c2
-rw-r--r--drivers/mfd/wm8350-core.c269
-rw-r--r--drivers/mfd/wm8350-i2c.c4
-rw-r--r--drivers/mfd/wm8350-regmap.c2100
-rw-r--r--drivers/mfd/wm8400-core.c31
19 files changed, 5502 insertions, 287 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 257277394f8c..416f9e7286ba 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -34,6 +34,14 @@ config MFD_ASIC3
34 This driver supports the ASIC3 multifunction chip found on many 34 This driver supports the ASIC3 multifunction chip found on many
35 PDAs (mainly iPAQ and HTC based ones) 35 PDAs (mainly iPAQ and HTC based ones)
36 36
37config MFD_DM355EVM_MSP
38 bool "DaVinci DM355 EVM microcontroller"
39 depends on I2C && MACH_DAVINCI_DM355_EVM
40 help
41 This driver supports the MSP430 microcontroller used on these
42 boards. MSP430 firmware manages resets and power sequencing,
43 inputs from buttons and the IR remote, LEDs, an RTC, and more.
44
37config HTC_EGPIO 45config HTC_EGPIO
38 bool "HTC EGPIO support" 46 bool "HTC EGPIO support"
39 depends on GENERIC_HARDIRQS && GPIOLIB && ARM 47 depends on GENERIC_HARDIRQS && GPIOLIB && ARM
@@ -61,9 +69,32 @@ config UCB1400_CORE
61 To compile this driver as a module, choose M here: the 69 To compile this driver as a module, choose M here: the
62 module will be called ucb1400_core. 70 module will be called ucb1400_core.
63 71
72config TPS65010
73 tristate "TPS6501x Power Management chips"
74 depends on I2C && GPIOLIB
75 default y if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_OSK
76 help
77 If you say yes here you get support for the TPS6501x series of
78 Power Management chips. These include voltage regulators,
79 lithium ion/polymer battery charging, and other features that
80 are often used in portable devices like cell phones and cameras.
81
82 This driver can also be built as a module. If so, the module
83 will be called tps65010.
84
85config MENELAUS
86 bool "Texas Instruments TWL92330/Menelaus PM chip"
87 depends on I2C=y && ARCH_OMAP24XX
88 help
89 If you say yes here you get support for the Texas Instruments
90 TWL92330/Menelaus Power Management chip. This include voltage
91 regulators, Dual slot memory card tranceivers, real-time clock
92 and other features that are often used in portable devices like
93 cell phones and PDAs.
94
64config TWL4030_CORE 95config TWL4030_CORE
65 bool "Texas Instruments TWL4030/TPS659x0 Support" 96 bool "Texas Instruments TWL4030/TPS659x0 Support"
66 depends on I2C=y && GENERIC_HARDIRQS && (ARCH_OMAP2 || ARCH_OMAP3) 97 depends on I2C=y && GENERIC_HARDIRQS
67 help 98 help
68 Say yes here if you have TWL4030 family chip on your board. 99 Say yes here if you have TWL4030 family chip on your board.
69 This core driver provides register access and IRQ handling 100 This core driver provides register access and IRQ handling
@@ -116,6 +147,7 @@ config PMIC_DA903X
116 147
117config MFD_WM8400 148config MFD_WM8400
118 tristate "Support Wolfson Microelectronics WM8400" 149 tristate "Support Wolfson Microelectronics WM8400"
150 select MFD_CORE
119 depends on I2C 151 depends on I2C
120 help 152 help
121 Support for the Wolfson Microelecronics WM8400 PMIC and audio 153 Support for the Wolfson Microelecronics WM8400 PMIC and audio
@@ -142,6 +174,38 @@ config MFD_WM8350_CONFIG_MODE_3
142 bool 174 bool
143 depends on MFD_WM8350 175 depends on MFD_WM8350
144 176
177config MFD_WM8351_CONFIG_MODE_0
178 bool
179 depends on MFD_WM8350
180
181config MFD_WM8351_CONFIG_MODE_1
182 bool
183 depends on MFD_WM8350
184
185config MFD_WM8351_CONFIG_MODE_2
186 bool
187 depends on MFD_WM8350
188
189config MFD_WM8351_CONFIG_MODE_3
190 bool
191 depends on MFD_WM8350
192
193config MFD_WM8352_CONFIG_MODE_0
194 bool
195 depends on MFD_WM8350
196
197config MFD_WM8352_CONFIG_MODE_1
198 bool
199 depends on MFD_WM8350
200
201config MFD_WM8352_CONFIG_MODE_2
202 bool
203 depends on MFD_WM8350
204
205config MFD_WM8352_CONFIG_MODE_3
206 bool
207 depends on MFD_WM8350
208
145config MFD_WM8350_I2C 209config MFD_WM8350_I2C
146 tristate "Support Wolfson Microelectronics WM8350 with I2C" 210 tristate "Support Wolfson Microelectronics WM8350 with I2C"
147 select MFD_WM8350 211 select MFD_WM8350
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9a5ad8af9116..0c9418b36c26 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,8 @@ obj-$(CONFIG_MFD_ASIC3) += asic3.o
8obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o 8obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
9obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o 9obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
10 10
11obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o
12
11obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o 13obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o
12obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o 14obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
13obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o 15obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
@@ -17,6 +19,9 @@ wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o
17obj-$(CONFIG_MFD_WM8350) += wm8350.o 19obj-$(CONFIG_MFD_WM8350) += wm8350.o
18obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o 20obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
19 21
22obj-$(CONFIG_TPS65010) += tps65010.o
23obj-$(CONFIG_MENELAUS) += menelaus.o
24
20obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o 25obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
21 26
22obj-$(CONFIG_MFD_CORE) += mfd-core.o 27obj-$(CONFIG_MFD_CORE) += mfd-core.o
@@ -31,4 +36,4 @@ obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o
31endif 36endif
32obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o 37obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o
33 38
34obj-$(CONFIG_PMIC_DA903X) += da903x.o \ No newline at end of file 39obj-$(CONFIG_PMIC_DA903X) += da903x.o
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index e4c0db4dc7b1..9e485459f63b 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -474,9 +474,9 @@ static __init int asic3_gpio_probe(struct platform_device *pdev,
474 u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; 474 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
475 int i; 475 int i;
476 476
477 memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 477 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
478 memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 478 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
479 memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); 479 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
480 480
481 /* Enable all GPIOs */ 481 /* Enable all GPIOs */
482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); 482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
diff --git a/drivers/mfd/da903x.c b/drivers/mfd/da903x.c
index 0b5bd85dfcec..99f8dcfe3d98 100644
--- a/drivers/mfd/da903x.c
+++ b/drivers/mfd/da903x.c
@@ -151,12 +151,24 @@ int da903x_write(struct device *dev, int reg, uint8_t val)
151} 151}
152EXPORT_SYMBOL_GPL(da903x_write); 152EXPORT_SYMBOL_GPL(da903x_write);
153 153
154int da903x_writes(struct device *dev, int reg, int len, uint8_t *val)
155{
156 return __da903x_writes(to_i2c_client(dev), reg, len, val);
157}
158EXPORT_SYMBOL_GPL(da903x_writes);
159
154int da903x_read(struct device *dev, int reg, uint8_t *val) 160int da903x_read(struct device *dev, int reg, uint8_t *val)
155{ 161{
156 return __da903x_read(to_i2c_client(dev), reg, val); 162 return __da903x_read(to_i2c_client(dev), reg, val);
157} 163}
158EXPORT_SYMBOL_GPL(da903x_read); 164EXPORT_SYMBOL_GPL(da903x_read);
159 165
166int da903x_reads(struct device *dev, int reg, int len, uint8_t *val)
167{
168 return __da903x_reads(to_i2c_client(dev), reg, len, val);
169}
170EXPORT_SYMBOL_GPL(da903x_reads);
171
160int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask) 172int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
161{ 173{
162 struct da903x_chip *chip = dev_get_drvdata(dev); 174 struct da903x_chip *chip = dev_get_drvdata(dev);
@@ -435,13 +447,13 @@ static const struct i2c_device_id da903x_id_table[] = {
435}; 447};
436MODULE_DEVICE_TABLE(i2c, da903x_id_table); 448MODULE_DEVICE_TABLE(i2c, da903x_id_table);
437 449
438static int __devexit __remove_subdev(struct device *dev, void *unused) 450static int __remove_subdev(struct device *dev, void *unused)
439{ 451{
440 platform_device_unregister(to_platform_device(dev)); 452 platform_device_unregister(to_platform_device(dev));
441 return 0; 453 return 0;
442} 454}
443 455
444static int __devexit da903x_remove_subdevs(struct da903x_chip *chip) 456static int da903x_remove_subdevs(struct da903x_chip *chip)
445{ 457{
446 return device_for_each_child(chip->dev, NULL, __remove_subdev); 458 return device_for_each_child(chip->dev, NULL, __remove_subdev);
447} 459}
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c
new file mode 100644
index 000000000000..4214b3f72426
--- /dev/null
+++ b/drivers/mfd/dm355evm_msp.c
@@ -0,0 +1,420 @@
1/*
2 * dm355evm_msp.c - driver for MSP430 firmware on DM355EVM board
3 *
4 * Copyright (C) 2008 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/init.h>
13#include <linux/mutex.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/leds.h>
19#include <linux/i2c.h>
20#include <linux/i2c/dm355evm_msp.h>
21
22
23/*
24 * The DM355 is a DaVinci chip with video support but no C64+ DSP. Its
25 * EVM board has an MSP430 programmed with firmware for various board
26 * support functions. This driver exposes some of them directly, and
27 * supports other drivers (e.g. RTC, input) for more complex access.
28 *
29 * Because this firmware is entirely board-specific, this file embeds
30 * knowledge that would be passed as platform_data in a generic driver.
31 *
32 * This driver was tested with firmware revision A4.
33 */
34
35#if defined(CONFIG_KEYBOARD_DM355EVM) \
36 || defined(CONFIG_KEYBOARD_DM355EVM_MODULE)
37#define msp_has_keyboard() true
38#else
39#define msp_has_keyboard() false
40#endif
41
42#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
43#define msp_has_leds() true
44#else
45#define msp_has_leds() false
46#endif
47
48#if defined(CONFIG_RTC_DRV_DM355EVM) || defined(CONFIG_RTC_DRV_DM355EVM_MODULE)
49#define msp_has_rtc() true
50#else
51#define msp_has_rtc() false
52#endif
53
54#if defined(CONFIG_VIDEO_TVP514X) || defined(CONFIG_VIDEO_TVP514X_MODULE)
55#define msp_has_tvp() true
56#else
57#define msp_has_tvp() false
58#endif
59
60
61/*----------------------------------------------------------------------*/
62
63/* REVISIT for paranoia's sake, retry reads/writes on error */
64
65static struct i2c_client *msp430;
66
67/**
68 * dm355evm_msp_write - Writes a register in dm355evm_msp
69 * @value: the value to be written
70 * @reg: register address
71 *
72 * Returns result of operation - 0 is success, else negative errno
73 */
74int dm355evm_msp_write(u8 value, u8 reg)
75{
76 return i2c_smbus_write_byte_data(msp430, reg, value);
77}
78EXPORT_SYMBOL(dm355evm_msp_write);
79
80/**
81 * dm355evm_msp_read - Reads a register from dm355evm_msp
82 * @reg: register address
83 *
84 * Returns result of operation - value, or negative errno
85 */
86int dm355evm_msp_read(u8 reg)
87{
88 return i2c_smbus_read_byte_data(msp430, reg);
89}
90EXPORT_SYMBOL(dm355evm_msp_read);
91
92/*----------------------------------------------------------------------*/
93
94/*
95 * Many of the msp430 pins are just used as fixed-direction GPIOs.
96 * We could export a few more of them this way, if we wanted.
97 */
98#define MSP_GPIO(bit,reg) ((DM355EVM_MSP_ ## reg) << 3 | (bit))
99
100static const u8 msp_gpios[] = {
101 /* eight leds */
102 MSP_GPIO(0, LED), MSP_GPIO(1, LED),
103 MSP_GPIO(2, LED), MSP_GPIO(3, LED),
104 MSP_GPIO(4, LED), MSP_GPIO(5, LED),
105 MSP_GPIO(6, LED), MSP_GPIO(7, LED),
106 /* SW6 and the NTSC/nPAL jumper */
107 MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1),
108 MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1),
109 MSP_GPIO(4, SWITCH1),
110};
111
112#define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3)
113#define MSP_GPIO_MASK(offset) BIT(msp_gpios[(offset)] & 0x07)
114
115static int msp_gpio_in(struct gpio_chip *chip, unsigned offset)
116{
117 switch (MSP_GPIO_REG(offset)) {
118 case DM355EVM_MSP_SWITCH1:
119 case DM355EVM_MSP_SWITCH2:
120 case DM355EVM_MSP_SDMMC:
121 return 0;
122 default:
123 return -EINVAL;
124 }
125}
126
127static u8 msp_led_cache;
128
129static int msp_gpio_get(struct gpio_chip *chip, unsigned offset)
130{
131 int reg, status;
132
133 reg = MSP_GPIO_REG(offset);
134 status = dm355evm_msp_read(reg);
135 if (status < 0)
136 return status;
137 if (reg == DM355EVM_MSP_LED)
138 msp_led_cache = status;
139 return status & MSP_GPIO_MASK(offset);
140}
141
142static int msp_gpio_out(struct gpio_chip *chip, unsigned offset, int value)
143{
144 int mask, bits;
145
146 /* NOTE: there are some other signals that could be
147 * packaged as output GPIOs, but they aren't as useful
148 * as the LEDs ... so for now we don't.
149 */
150 if (MSP_GPIO_REG(offset) != DM355EVM_MSP_LED)
151 return -EINVAL;
152
153 mask = MSP_GPIO_MASK(offset);
154 bits = msp_led_cache;
155
156 bits &= ~mask;
157 if (value)
158 bits |= mask;
159 msp_led_cache = bits;
160
161 return dm355evm_msp_write(bits, DM355EVM_MSP_LED);
162}
163
164static void msp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
165{
166 msp_gpio_out(chip, offset, value);
167}
168
169static struct gpio_chip dm355evm_msp_gpio = {
170 .label = "dm355evm_msp",
171 .owner = THIS_MODULE,
172 .direction_input = msp_gpio_in,
173 .get = msp_gpio_get,
174 .direction_output = msp_gpio_out,
175 .set = msp_gpio_set,
176 .base = -EINVAL, /* dynamic assignment */
177 .ngpio = ARRAY_SIZE(msp_gpios),
178 .can_sleep = true,
179};
180
181/*----------------------------------------------------------------------*/
182
183static struct device *add_child(struct i2c_client *client, const char *name,
184 void *pdata, unsigned pdata_len,
185 bool can_wakeup, int irq)
186{
187 struct platform_device *pdev;
188 int status;
189
190 pdev = platform_device_alloc(name, -1);
191 if (!pdev) {
192 dev_dbg(&client->dev, "can't alloc dev\n");
193 status = -ENOMEM;
194 goto err;
195 }
196
197 device_init_wakeup(&pdev->dev, can_wakeup);
198 pdev->dev.parent = &client->dev;
199
200 if (pdata) {
201 status = platform_device_add_data(pdev, pdata, pdata_len);
202 if (status < 0) {
203 dev_dbg(&pdev->dev, "can't add platform_data\n");
204 goto err;
205 }
206 }
207
208 if (irq) {
209 struct resource r = {
210 .start = irq,
211 .flags = IORESOURCE_IRQ,
212 };
213
214 status = platform_device_add_resources(pdev, &r, 1);
215 if (status < 0) {
216 dev_dbg(&pdev->dev, "can't add irq\n");
217 goto err;
218 }
219 }
220
221 status = platform_device_add(pdev);
222
223err:
224 if (status < 0) {
225 platform_device_put(pdev);
226 dev_err(&client->dev, "can't add %s dev\n", name);
227 return ERR_PTR(status);
228 }
229 return &pdev->dev;
230}
231
232static int add_children(struct i2c_client *client)
233{
234 static const struct {
235 int offset;
236 char *label;
237 } config_inputs[] = {
238 /* 8 == right after the LEDs */
239 { 8 + 0, "sw6_1", },
240 { 8 + 1, "sw6_2", },
241 { 8 + 2, "sw6_3", },
242 { 8 + 3, "sw6_4", },
243 { 8 + 4, "NTSC/nPAL", },
244 };
245
246 struct device *child;
247 int status;
248 int i;
249
250 /* GPIO-ish stuff */
251 dm355evm_msp_gpio.dev = &client->dev;
252 status = gpiochip_add(&dm355evm_msp_gpio);
253 if (status < 0)
254 return status;
255
256 /* LED output */
257 if (msp_has_leds()) {
258#define GPIO_LED(l) .name = l, .active_low = true
259 static struct gpio_led evm_leds[] = {
260 { GPIO_LED("dm355evm::ds14"),
261 .default_trigger = "heartbeat", },
262 { GPIO_LED("dm355evm::ds15"),
263 .default_trigger = "mmc0", },
264 { GPIO_LED("dm355evm::ds16"),
265 /* could also be a CE-ATA drive */
266 .default_trigger = "mmc1", },
267 { GPIO_LED("dm355evm::ds17"),
268 .default_trigger = "nand-disk", },
269 { GPIO_LED("dm355evm::ds18"), },
270 { GPIO_LED("dm355evm::ds19"), },
271 { GPIO_LED("dm355evm::ds20"), },
272 { GPIO_LED("dm355evm::ds21"), },
273 };
274#undef GPIO_LED
275
276 struct gpio_led_platform_data evm_led_data = {
277 .num_leds = ARRAY_SIZE(evm_leds),
278 .leds = evm_leds,
279 };
280
281 for (i = 0; i < ARRAY_SIZE(evm_leds); i++)
282 evm_leds[i].gpio = i + dm355evm_msp_gpio.base;
283
284 /* NOTE: these are the only fully programmable LEDs
285 * on the board, since GPIO-61/ds22 (and many signals
286 * going to DC7) must be used for AEMIF address lines
287 * unless the top 1 GB of NAND is unused...
288 */
289 child = add_child(client, "leds-gpio",
290 &evm_led_data, sizeof(evm_led_data),
291 false, 0);
292 if (IS_ERR(child))
293 return PTR_ERR(child);
294 }
295
296 /* configuration inputs */
297 for (i = 0; i < ARRAY_SIZE(config_inputs); i++) {
298 int gpio = dm355evm_msp_gpio.base + config_inputs[i].offset;
299
300 gpio_request(gpio, config_inputs[i].label);
301 gpio_direction_input(gpio);
302
303 /* make it easy for userspace to see these */
304 gpio_export(gpio, false);
305 }
306
307 /* RTC is a 32 bit counter, no alarm */
308 if (msp_has_rtc()) {
309 child = add_child(client, "rtc-dm355evm",
310 NULL, 0, false, 0);
311 if (IS_ERR(child))
312 return PTR_ERR(child);
313 }
314
315 /* input from buttons and IR remote (uses the IRQ) */
316 if (msp_has_keyboard()) {
317 child = add_child(client, "dm355evm_keys",
318 NULL, 0, true, client->irq);
319 if (IS_ERR(child))
320 return PTR_ERR(child);
321 }
322
323 return 0;
324}
325
326/*----------------------------------------------------------------------*/
327
328static void dm355evm_command(unsigned command)
329{
330 int status;
331
332 status = dm355evm_msp_write(command, DM355EVM_MSP_COMMAND);
333 if (status < 0)
334 dev_err(&msp430->dev, "command %d failure %d\n",
335 command, status);
336}
337
338static void dm355evm_power_off(void)
339{
340 dm355evm_command(MSP_COMMAND_POWEROFF);
341}
342
343static int dm355evm_msp_remove(struct i2c_client *client)
344{
345 pm_power_off = NULL;
346 msp430 = NULL;
347 return 0;
348}
349
350static int
351dm355evm_msp_probe(struct i2c_client *client, const struct i2c_device_id *id)
352{
353 int status;
354 const char *video = msp_has_tvp() ? "TVP5146" : "imager";
355
356 if (msp430)
357 return -EBUSY;
358 msp430 = client;
359
360 /* display revision status; doubles as sanity check */
361 status = dm355evm_msp_read(DM355EVM_MSP_FIRMREV);
362 if (status < 0)
363 goto fail;
364 dev_info(&client->dev, "firmware v.%02X, %s as video-in\n",
365 status, video);
366
367 /* mux video input: either tvp5146 or some external imager */
368 status = dm355evm_msp_write(msp_has_tvp() ? 0 : MSP_VIDEO_IMAGER,
369 DM355EVM_MSP_VIDEO_IN);
370 if (status < 0)
371 dev_warn(&client->dev, "error %d muxing %s as video-in\n",
372 status, video);
373
374 /* init LED cache, and turn off the LEDs */
375 msp_led_cache = 0xff;
376 dm355evm_msp_write(msp_led_cache, DM355EVM_MSP_LED);
377
378 /* export capabilities we support */
379 status = add_children(client);
380 if (status < 0)
381 goto fail;
382
383 /* PM hookup */
384 pm_power_off = dm355evm_power_off;
385
386 return 0;
387
388fail:
389 /* FIXME remove children ... */
390 dm355evm_msp_remove(client);
391 return status;
392}
393
394static const struct i2c_device_id dm355evm_msp_ids[] = {
395 { "dm355evm_msp", 0 },
396 { /* end of list */ },
397};
398MODULE_DEVICE_TABLE(i2c, dm355evm_msp_ids);
399
400static struct i2c_driver dm355evm_msp_driver = {
401 .driver.name = "dm355evm_msp",
402 .id_table = dm355evm_msp_ids,
403 .probe = dm355evm_msp_probe,
404 .remove = dm355evm_msp_remove,
405};
406
407static int __init dm355evm_msp_init(void)
408{
409 return i2c_add_driver(&dm355evm_msp_driver);
410}
411subsys_initcall(dm355evm_msp_init);
412
413static void __exit dm355evm_msp_exit(void)
414{
415 i2c_del_driver(&dm355evm_msp_driver);
416}
417module_exit(dm355evm_msp_exit);
418
419MODULE_DESCRIPTION("Interface to MSP430 firmware on DM355EVM");
420MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/mcp-core.c b/drivers/mfd/mcp-core.c
index b4ed57e02729..6063dc2b52e8 100644
--- a/drivers/mfd/mcp-core.c
+++ b/drivers/mfd/mcp-core.c
@@ -18,7 +18,7 @@
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/string.h> 19#include <linux/string.h>
20 20
21#include <asm/dma.h> 21#include <mach/dma.h>
22#include <asm/system.h> 22#include <asm/system.h>
23 23
24#include "mcp.h" 24#include "mcp.h"
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index 28380b20bc70..62b32dabf629 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -20,7 +20,7 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22 22
23#include <asm/dma.h> 23#include <mach/dma.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <asm/mach-types.h> 25#include <asm/mach-types.h>
26#include <asm/system.h> 26#include <asm/system.h>
diff --git a/drivers/mfd/menelaus.c b/drivers/mfd/menelaus.c
new file mode 100644
index 000000000000..4b364bae6b3e
--- /dev/null
+++ b/drivers/mfd/menelaus.c
@@ -0,0 +1,1285 @@
1/*
2 * Copyright (C) 2004 Texas Instruments, Inc.
3 *
4 * Some parts based tps65010.c:
5 * Copyright (C) 2004 Texas Instruments and
6 * Copyright (C) 2004-2005 David Brownell
7 *
8 * Some parts based on tlv320aic24.c:
9 * Copyright (C) by Kai Svahn <kai.svahn@nokia.com>
10 *
11 * Changes for interrupt handling and clean-up by
12 * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
13 * Cleanup and generalized support for voltage setting by
14 * Juha Yrjola
15 * Added support for controlling VCORE and regulator sleep states,
16 * Amit Kucheria <amit.kucheria@nokia.com>
17 * Copyright (C) 2005, 2006 Nokia Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 */
33
34#include <linux/module.h>
35#include <linux/i2c.h>
36#include <linux/interrupt.h>
37#include <linux/sched.h>
38#include <linux/mutex.h>
39#include <linux/workqueue.h>
40#include <linux/delay.h>
41#include <linux/rtc.h>
42#include <linux/bcd.h>
43
44#include <asm/mach/irq.h>
45
46#include <mach/gpio.h>
47#include <mach/menelaus.h>
48
49#define DRIVER_NAME "menelaus"
50
51#define MENELAUS_I2C_ADDRESS 0x72
52
53#define MENELAUS_REV 0x01
54#define MENELAUS_VCORE_CTRL1 0x02
55#define MENELAUS_VCORE_CTRL2 0x03
56#define MENELAUS_VCORE_CTRL3 0x04
57#define MENELAUS_VCORE_CTRL4 0x05
58#define MENELAUS_VCORE_CTRL5 0x06
59#define MENELAUS_DCDC_CTRL1 0x07
60#define MENELAUS_DCDC_CTRL2 0x08
61#define MENELAUS_DCDC_CTRL3 0x09
62#define MENELAUS_LDO_CTRL1 0x0A
63#define MENELAUS_LDO_CTRL2 0x0B
64#define MENELAUS_LDO_CTRL3 0x0C
65#define MENELAUS_LDO_CTRL4 0x0D
66#define MENELAUS_LDO_CTRL5 0x0E
67#define MENELAUS_LDO_CTRL6 0x0F
68#define MENELAUS_LDO_CTRL7 0x10
69#define MENELAUS_LDO_CTRL8 0x11
70#define MENELAUS_SLEEP_CTRL1 0x12
71#define MENELAUS_SLEEP_CTRL2 0x13
72#define MENELAUS_DEVICE_OFF 0x14
73#define MENELAUS_OSC_CTRL 0x15
74#define MENELAUS_DETECT_CTRL 0x16
75#define MENELAUS_INT_MASK1 0x17
76#define MENELAUS_INT_MASK2 0x18
77#define MENELAUS_INT_STATUS1 0x19
78#define MENELAUS_INT_STATUS2 0x1A
79#define MENELAUS_INT_ACK1 0x1B
80#define MENELAUS_INT_ACK2 0x1C
81#define MENELAUS_GPIO_CTRL 0x1D
82#define MENELAUS_GPIO_IN 0x1E
83#define MENELAUS_GPIO_OUT 0x1F
84#define MENELAUS_BBSMS 0x20
85#define MENELAUS_RTC_CTRL 0x21
86#define MENELAUS_RTC_UPDATE 0x22
87#define MENELAUS_RTC_SEC 0x23
88#define MENELAUS_RTC_MIN 0x24
89#define MENELAUS_RTC_HR 0x25
90#define MENELAUS_RTC_DAY 0x26
91#define MENELAUS_RTC_MON 0x27
92#define MENELAUS_RTC_YR 0x28
93#define MENELAUS_RTC_WKDAY 0x29
94#define MENELAUS_RTC_AL_SEC 0x2A
95#define MENELAUS_RTC_AL_MIN 0x2B
96#define MENELAUS_RTC_AL_HR 0x2C
97#define MENELAUS_RTC_AL_DAY 0x2D
98#define MENELAUS_RTC_AL_MON 0x2E
99#define MENELAUS_RTC_AL_YR 0x2F
100#define MENELAUS_RTC_COMP_MSB 0x30
101#define MENELAUS_RTC_COMP_LSB 0x31
102#define MENELAUS_S1_PULL_EN 0x32
103#define MENELAUS_S1_PULL_DIR 0x33
104#define MENELAUS_S2_PULL_EN 0x34
105#define MENELAUS_S2_PULL_DIR 0x35
106#define MENELAUS_MCT_CTRL1 0x36
107#define MENELAUS_MCT_CTRL2 0x37
108#define MENELAUS_MCT_CTRL3 0x38
109#define MENELAUS_MCT_PIN_ST 0x39
110#define MENELAUS_DEBOUNCE1 0x3A
111
112#define IH_MENELAUS_IRQS 12
113#define MENELAUS_MMC_S1CD_IRQ 0 /* MMC slot 1 card change */
114#define MENELAUS_MMC_S2CD_IRQ 1 /* MMC slot 2 card change */
115#define MENELAUS_MMC_S1D1_IRQ 2 /* MMC DAT1 low in slot 1 */
116#define MENELAUS_MMC_S2D1_IRQ 3 /* MMC DAT1 low in slot 2 */
117#define MENELAUS_LOWBAT_IRQ 4 /* Low battery */
118#define MENELAUS_HOTDIE_IRQ 5 /* Hot die detect */
119#define MENELAUS_UVLO_IRQ 6 /* UVLO detect */
120#define MENELAUS_TSHUT_IRQ 7 /* Thermal shutdown */
121#define MENELAUS_RTCTMR_IRQ 8 /* RTC timer */
122#define MENELAUS_RTCALM_IRQ 9 /* RTC alarm */
123#define MENELAUS_RTCERR_IRQ 10 /* RTC error */
124#define MENELAUS_PSHBTN_IRQ 11 /* Push button */
125#define MENELAUS_RESERVED12_IRQ 12 /* Reserved */
126#define MENELAUS_RESERVED13_IRQ 13 /* Reserved */
127#define MENELAUS_RESERVED14_IRQ 14 /* Reserved */
128#define MENELAUS_RESERVED15_IRQ 15 /* Reserved */
129
130static void menelaus_work(struct work_struct *_menelaus);
131
132struct menelaus_chip {
133 struct mutex lock;
134 struct i2c_client *client;
135 struct work_struct work;
136#ifdef CONFIG_RTC_DRV_TWL92330
137 struct rtc_device *rtc;
138 u8 rtc_control;
139 unsigned uie:1;
140#endif
141 unsigned vcore_hw_mode:1;
142 u8 mask1, mask2;
143 void (*handlers[16])(struct menelaus_chip *);
144 void (*mmc_callback)(void *data, u8 mask);
145 void *mmc_callback_data;
146};
147
148static struct menelaus_chip *the_menelaus;
149
150static int menelaus_write_reg(int reg, u8 value)
151{
152 int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value);
153
154 if (val < 0) {
155 pr_err(DRIVER_NAME ": write error");
156 return val;
157 }
158
159 return 0;
160}
161
162static int menelaus_read_reg(int reg)
163{
164 int val = i2c_smbus_read_byte_data(the_menelaus->client, reg);
165
166 if (val < 0)
167 pr_err(DRIVER_NAME ": read error");
168
169 return val;
170}
171
172static int menelaus_enable_irq(int irq)
173{
174 if (irq > 7) {
175 irq -= 8;
176 the_menelaus->mask2 &= ~(1 << irq);
177 return menelaus_write_reg(MENELAUS_INT_MASK2,
178 the_menelaus->mask2);
179 } else {
180 the_menelaus->mask1 &= ~(1 << irq);
181 return menelaus_write_reg(MENELAUS_INT_MASK1,
182 the_menelaus->mask1);
183 }
184}
185
186static int menelaus_disable_irq(int irq)
187{
188 if (irq > 7) {
189 irq -= 8;
190 the_menelaus->mask2 |= (1 << irq);
191 return menelaus_write_reg(MENELAUS_INT_MASK2,
192 the_menelaus->mask2);
193 } else {
194 the_menelaus->mask1 |= (1 << irq);
195 return menelaus_write_reg(MENELAUS_INT_MASK1,
196 the_menelaus->mask1);
197 }
198}
199
200static int menelaus_ack_irq(int irq)
201{
202 if (irq > 7)
203 return menelaus_write_reg(MENELAUS_INT_ACK2, 1 << (irq - 8));
204 else
205 return menelaus_write_reg(MENELAUS_INT_ACK1, 1 << irq);
206}
207
208/* Adds a handler for an interrupt. Does not run in interrupt context */
209static int menelaus_add_irq_work(int irq,
210 void (*handler)(struct menelaus_chip *))
211{
212 int ret = 0;
213
214 mutex_lock(&the_menelaus->lock);
215 the_menelaus->handlers[irq] = handler;
216 ret = menelaus_enable_irq(irq);
217 mutex_unlock(&the_menelaus->lock);
218
219 return ret;
220}
221
222/* Removes handler for an interrupt */
223static int menelaus_remove_irq_work(int irq)
224{
225 int ret = 0;
226
227 mutex_lock(&the_menelaus->lock);
228 ret = menelaus_disable_irq(irq);
229 the_menelaus->handlers[irq] = NULL;
230 mutex_unlock(&the_menelaus->lock);
231
232 return ret;
233}
234
235/*
236 * Gets scheduled when a card detect interrupt happens. Note that in some cases
237 * this line is wired to card cover switch rather than the card detect switch
238 * in each slot. In this case the cards are not seen by menelaus.
239 * FIXME: Add handling for D1 too
240 */
241static void menelaus_mmc_cd_work(struct menelaus_chip *menelaus_hw)
242{
243 int reg;
244 unsigned char card_mask = 0;
245
246 reg = menelaus_read_reg(MENELAUS_MCT_PIN_ST);
247 if (reg < 0)
248 return;
249
250 if (!(reg & 0x1))
251 card_mask |= (1 << 0);
252
253 if (!(reg & 0x2))
254 card_mask |= (1 << 1);
255
256 if (menelaus_hw->mmc_callback)
257 menelaus_hw->mmc_callback(menelaus_hw->mmc_callback_data,
258 card_mask);
259}
260
261/*
262 * Toggles the MMC slots between open-drain and push-pull mode.
263 */
264int menelaus_set_mmc_opendrain(int slot, int enable)
265{
266 int ret, val;
267
268 if (slot != 1 && slot != 2)
269 return -EINVAL;
270 mutex_lock(&the_menelaus->lock);
271 ret = menelaus_read_reg(MENELAUS_MCT_CTRL1);
272 if (ret < 0) {
273 mutex_unlock(&the_menelaus->lock);
274 return ret;
275 }
276 val = ret;
277 if (slot == 1) {
278 if (enable)
279 val |= 1 << 2;
280 else
281 val &= ~(1 << 2);
282 } else {
283 if (enable)
284 val |= 1 << 3;
285 else
286 val &= ~(1 << 3);
287 }
288 ret = menelaus_write_reg(MENELAUS_MCT_CTRL1, val);
289 mutex_unlock(&the_menelaus->lock);
290
291 return ret;
292}
293EXPORT_SYMBOL(menelaus_set_mmc_opendrain);
294
295int menelaus_set_slot_sel(int enable)
296{
297 int ret;
298
299 mutex_lock(&the_menelaus->lock);
300 ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
301 if (ret < 0)
302 goto out;
303 ret |= 0x02;
304 if (enable)
305 ret |= 1 << 5;
306 else
307 ret &= ~(1 << 5);
308 ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
309out:
310 mutex_unlock(&the_menelaus->lock);
311 return ret;
312}
313EXPORT_SYMBOL(menelaus_set_slot_sel);
314
315int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_en)
316{
317 int ret, val;
318
319 if (slot != 1 && slot != 2)
320 return -EINVAL;
321 if (power >= 3)
322 return -EINVAL;
323
324 mutex_lock(&the_menelaus->lock);
325
326 ret = menelaus_read_reg(MENELAUS_MCT_CTRL2);
327 if (ret < 0)
328 goto out;
329 val = ret;
330 if (slot == 1) {
331 if (cd_en)
332 val |= (1 << 4) | (1 << 6);
333 else
334 val &= ~((1 << 4) | (1 << 6));
335 } else {
336 if (cd_en)
337 val |= (1 << 5) | (1 << 7);
338 else
339 val &= ~((1 << 5) | (1 << 7));
340 }
341 ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, val);
342 if (ret < 0)
343 goto out;
344
345 ret = menelaus_read_reg(MENELAUS_MCT_CTRL3);
346 if (ret < 0)
347 goto out;
348 val = ret;
349 if (slot == 1) {
350 if (enable)
351 val |= 1 << 0;
352 else
353 val &= ~(1 << 0);
354 } else {
355 int b;
356
357 if (enable)
358 ret |= 1 << 1;
359 else
360 ret &= ~(1 << 1);
361 b = menelaus_read_reg(MENELAUS_MCT_CTRL2);
362 b &= ~0x03;
363 b |= power;
364 ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, b);
365 if (ret < 0)
366 goto out;
367 }
368 /* Disable autonomous shutdown */
369 val &= ~(0x03 << 2);
370 ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val);
371out:
372 mutex_unlock(&the_menelaus->lock);
373 return ret;
374}
375EXPORT_SYMBOL(menelaus_set_mmc_slot);
376
377int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
378 void *data)
379{
380 int ret = 0;
381
382 the_menelaus->mmc_callback_data = data;
383 the_menelaus->mmc_callback = callback;
384 ret = menelaus_add_irq_work(MENELAUS_MMC_S1CD_IRQ,
385 menelaus_mmc_cd_work);
386 if (ret < 0)
387 return ret;
388 ret = menelaus_add_irq_work(MENELAUS_MMC_S2CD_IRQ,
389 menelaus_mmc_cd_work);
390 if (ret < 0)
391 return ret;
392 ret = menelaus_add_irq_work(MENELAUS_MMC_S1D1_IRQ,
393 menelaus_mmc_cd_work);
394 if (ret < 0)
395 return ret;
396 ret = menelaus_add_irq_work(MENELAUS_MMC_S2D1_IRQ,
397 menelaus_mmc_cd_work);
398
399 return ret;
400}
401EXPORT_SYMBOL(menelaus_register_mmc_callback);
402
403void menelaus_unregister_mmc_callback(void)
404{
405 menelaus_remove_irq_work(MENELAUS_MMC_S1CD_IRQ);
406 menelaus_remove_irq_work(MENELAUS_MMC_S2CD_IRQ);
407 menelaus_remove_irq_work(MENELAUS_MMC_S1D1_IRQ);
408 menelaus_remove_irq_work(MENELAUS_MMC_S2D1_IRQ);
409
410 the_menelaus->mmc_callback = NULL;
411 the_menelaus->mmc_callback_data = 0;
412}
413EXPORT_SYMBOL(menelaus_unregister_mmc_callback);
414
415struct menelaus_vtg {
416 const char *name;
417 u8 vtg_reg;
418 u8 vtg_shift;
419 u8 vtg_bits;
420 u8 mode_reg;
421};
422
423struct menelaus_vtg_value {
424 u16 vtg;
425 u16 val;
426};
427
428static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV,
429 int vtg_val, int mode)
430{
431 int val, ret;
432 struct i2c_client *c = the_menelaus->client;
433
434 mutex_lock(&the_menelaus->lock);
435 if (vtg == 0)
436 goto set_voltage;
437
438 ret = menelaus_read_reg(vtg->vtg_reg);
439 if (ret < 0)
440 goto out;
441 val = ret & ~(((1 << vtg->vtg_bits) - 1) << vtg->vtg_shift);
442 val |= vtg_val << vtg->vtg_shift;
443
444 dev_dbg(&c->dev, "Setting voltage '%s'"
445 "to %d mV (reg 0x%02x, val 0x%02x)\n",
446 vtg->name, mV, vtg->vtg_reg, val);
447
448 ret = menelaus_write_reg(vtg->vtg_reg, val);
449 if (ret < 0)
450 goto out;
451set_voltage:
452 ret = menelaus_write_reg(vtg->mode_reg, mode);
453out:
454 mutex_unlock(&the_menelaus->lock);
455 if (ret == 0) {
456 /* Wait for voltage to stabilize */
457 msleep(1);
458 }
459 return ret;
460}
461
462static int menelaus_get_vtg_value(int vtg, const struct menelaus_vtg_value *tbl,
463 int n)
464{
465 int i;
466
467 for (i = 0; i < n; i++, tbl++)
468 if (tbl->vtg == vtg)
469 return tbl->val;
470 return -EINVAL;
471}
472
473/*
474 * Vcore can be programmed in two ways:
475 * SW-controlled: Required voltage is programmed into VCORE_CTRL1
476 * HW-controlled: Required range (roof-floor) is programmed into VCORE_CTRL3
477 * and VCORE_CTRL4
478 *
479 * Call correct 'set' function accordingly
480 */
481
482static const struct menelaus_vtg_value vcore_values[] = {
483 { 1000, 0 },
484 { 1025, 1 },
485 { 1050, 2 },
486 { 1075, 3 },
487 { 1100, 4 },
488 { 1125, 5 },
489 { 1150, 6 },
490 { 1175, 7 },
491 { 1200, 8 },
492 { 1225, 9 },
493 { 1250, 10 },
494 { 1275, 11 },
495 { 1300, 12 },
496 { 1325, 13 },
497 { 1350, 14 },
498 { 1375, 15 },
499 { 1400, 16 },
500 { 1425, 17 },
501 { 1450, 18 },
502};
503
504int menelaus_set_vcore_sw(unsigned int mV)
505{
506 int val, ret;
507 struct i2c_client *c = the_menelaus->client;
508
509 val = menelaus_get_vtg_value(mV, vcore_values,
510 ARRAY_SIZE(vcore_values));
511 if (val < 0)
512 return -EINVAL;
513
514 dev_dbg(&c->dev, "Setting VCORE to %d mV (val 0x%02x)\n", mV, val);
515
516 /* Set SW mode and the voltage in one go. */
517 mutex_lock(&the_menelaus->lock);
518 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val);
519 if (ret == 0)
520 the_menelaus->vcore_hw_mode = 0;
521 mutex_unlock(&the_menelaus->lock);
522 msleep(1);
523
524 return ret;
525}
526
527int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV)
528{
529 int fval, rval, val, ret;
530 struct i2c_client *c = the_menelaus->client;
531
532 rval = menelaus_get_vtg_value(roof_mV, vcore_values,
533 ARRAY_SIZE(vcore_values));
534 if (rval < 0)
535 return -EINVAL;
536 fval = menelaus_get_vtg_value(floor_mV, vcore_values,
537 ARRAY_SIZE(vcore_values));
538 if (fval < 0)
539 return -EINVAL;
540
541 dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n",
542 floor_mV, roof_mV);
543
544 mutex_lock(&the_menelaus->lock);
545 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL3, fval);
546 if (ret < 0)
547 goto out;
548 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL4, rval);
549 if (ret < 0)
550 goto out;
551 if (!the_menelaus->vcore_hw_mode) {
552 val = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
553 /* HW mode, turn OFF byte comparator */
554 val |= ((1 << 7) | (1 << 5));
555 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val);
556 the_menelaus->vcore_hw_mode = 1;
557 }
558 msleep(1);
559out:
560 mutex_unlock(&the_menelaus->lock);
561 return ret;
562}
563
564static const struct menelaus_vtg vmem_vtg = {
565 .name = "VMEM",
566 .vtg_reg = MENELAUS_LDO_CTRL1,
567 .vtg_shift = 0,
568 .vtg_bits = 2,
569 .mode_reg = MENELAUS_LDO_CTRL3,
570};
571
572static const struct menelaus_vtg_value vmem_values[] = {
573 { 1500, 0 },
574 { 1800, 1 },
575 { 1900, 2 },
576 { 2500, 3 },
577};
578
579int menelaus_set_vmem(unsigned int mV)
580{
581 int val;
582
583 if (mV == 0)
584 return menelaus_set_voltage(&vmem_vtg, 0, 0, 0);
585
586 val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values));
587 if (val < 0)
588 return -EINVAL;
589 return menelaus_set_voltage(&vmem_vtg, mV, val, 0x02);
590}
591EXPORT_SYMBOL(menelaus_set_vmem);
592
593static const struct menelaus_vtg vio_vtg = {
594 .name = "VIO",
595 .vtg_reg = MENELAUS_LDO_CTRL1,
596 .vtg_shift = 2,
597 .vtg_bits = 2,
598 .mode_reg = MENELAUS_LDO_CTRL4,
599};
600
601static const struct menelaus_vtg_value vio_values[] = {
602 { 1500, 0 },
603 { 1800, 1 },
604 { 2500, 2 },
605 { 2800, 3 },
606};
607
608int menelaus_set_vio(unsigned int mV)
609{
610 int val;
611
612 if (mV == 0)
613 return menelaus_set_voltage(&vio_vtg, 0, 0, 0);
614
615 val = menelaus_get_vtg_value(mV, vio_values, ARRAY_SIZE(vio_values));
616 if (val < 0)
617 return -EINVAL;
618 return menelaus_set_voltage(&vio_vtg, mV, val, 0x02);
619}
620EXPORT_SYMBOL(menelaus_set_vio);
621
622static const struct menelaus_vtg_value vdcdc_values[] = {
623 { 1500, 0 },
624 { 1800, 1 },
625 { 2000, 2 },
626 { 2200, 3 },
627 { 2400, 4 },
628 { 2800, 5 },
629 { 3000, 6 },
630 { 3300, 7 },
631};
632
633static const struct menelaus_vtg vdcdc2_vtg = {
634 .name = "VDCDC2",
635 .vtg_reg = MENELAUS_DCDC_CTRL1,
636 .vtg_shift = 0,
637 .vtg_bits = 3,
638 .mode_reg = MENELAUS_DCDC_CTRL2,
639};
640
641static const struct menelaus_vtg vdcdc3_vtg = {
642 .name = "VDCDC3",
643 .vtg_reg = MENELAUS_DCDC_CTRL1,
644 .vtg_shift = 3,
645 .vtg_bits = 3,
646 .mode_reg = MENELAUS_DCDC_CTRL3,
647};
648
649int menelaus_set_vdcdc(int dcdc, unsigned int mV)
650{
651 const struct menelaus_vtg *vtg;
652 int val;
653
654 if (dcdc != 2 && dcdc != 3)
655 return -EINVAL;
656 if (dcdc == 2)
657 vtg = &vdcdc2_vtg;
658 else
659 vtg = &vdcdc3_vtg;
660
661 if (mV == 0)
662 return menelaus_set_voltage(vtg, 0, 0, 0);
663
664 val = menelaus_get_vtg_value(mV, vdcdc_values,
665 ARRAY_SIZE(vdcdc_values));
666 if (val < 0)
667 return -EINVAL;
668 return menelaus_set_voltage(vtg, mV, val, 0x03);
669}
670
671static const struct menelaus_vtg_value vmmc_values[] = {
672 { 1850, 0 },
673 { 2800, 1 },
674 { 3000, 2 },
675 { 3100, 3 },
676};
677
678static const struct menelaus_vtg vmmc_vtg = {
679 .name = "VMMC",
680 .vtg_reg = MENELAUS_LDO_CTRL1,
681 .vtg_shift = 6,
682 .vtg_bits = 2,
683 .mode_reg = MENELAUS_LDO_CTRL7,
684};
685
686int menelaus_set_vmmc(unsigned int mV)
687{
688 int val;
689
690 if (mV == 0)
691 return menelaus_set_voltage(&vmmc_vtg, 0, 0, 0);
692
693 val = menelaus_get_vtg_value(mV, vmmc_values, ARRAY_SIZE(vmmc_values));
694 if (val < 0)
695 return -EINVAL;
696 return menelaus_set_voltage(&vmmc_vtg, mV, val, 0x02);
697}
698EXPORT_SYMBOL(menelaus_set_vmmc);
699
700
701static const struct menelaus_vtg_value vaux_values[] = {
702 { 1500, 0 },
703 { 1800, 1 },
704 { 2500, 2 },
705 { 2800, 3 },
706};
707
708static const struct menelaus_vtg vaux_vtg = {
709 .name = "VAUX",
710 .vtg_reg = MENELAUS_LDO_CTRL1,
711 .vtg_shift = 4,
712 .vtg_bits = 2,
713 .mode_reg = MENELAUS_LDO_CTRL6,
714};
715
716int menelaus_set_vaux(unsigned int mV)
717{
718 int val;
719
720 if (mV == 0)
721 return menelaus_set_voltage(&vaux_vtg, 0, 0, 0);
722
723 val = menelaus_get_vtg_value(mV, vaux_values, ARRAY_SIZE(vaux_values));
724 if (val < 0)
725 return -EINVAL;
726 return menelaus_set_voltage(&vaux_vtg, mV, val, 0x02);
727}
728EXPORT_SYMBOL(menelaus_set_vaux);
729
730int menelaus_get_slot_pin_states(void)
731{
732 return menelaus_read_reg(MENELAUS_MCT_PIN_ST);
733}
734EXPORT_SYMBOL(menelaus_get_slot_pin_states);
735
736int menelaus_set_regulator_sleep(int enable, u32 val)
737{
738 int t, ret;
739 struct i2c_client *c = the_menelaus->client;
740
741 mutex_lock(&the_menelaus->lock);
742 ret = menelaus_write_reg(MENELAUS_SLEEP_CTRL2, val);
743 if (ret < 0)
744 goto out;
745
746 dev_dbg(&c->dev, "regulator sleep configuration: %02x\n", val);
747
748 ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
749 if (ret < 0)
750 goto out;
751 t = ((1 << 6) | 0x04);
752 if (enable)
753 ret |= t;
754 else
755 ret &= ~t;
756 ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
757out:
758 mutex_unlock(&the_menelaus->lock);
759 return ret;
760}
761
762/*-----------------------------------------------------------------------*/
763
764/* Handles Menelaus interrupts. Does not run in interrupt context */
765static void menelaus_work(struct work_struct *_menelaus)
766{
767 struct menelaus_chip *menelaus =
768 container_of(_menelaus, struct menelaus_chip, work);
769 void (*handler)(struct menelaus_chip *menelaus);
770
771 while (1) {
772 unsigned isr;
773
774 isr = (menelaus_read_reg(MENELAUS_INT_STATUS2)
775 & ~menelaus->mask2) << 8;
776 isr |= menelaus_read_reg(MENELAUS_INT_STATUS1)
777 & ~menelaus->mask1;
778 if (!isr)
779 break;
780
781 while (isr) {
782 int irq = fls(isr) - 1;
783 isr &= ~(1 << irq);
784
785 mutex_lock(&menelaus->lock);
786 menelaus_disable_irq(irq);
787 menelaus_ack_irq(irq);
788 handler = menelaus->handlers[irq];
789 if (handler)
790 handler(menelaus);
791 menelaus_enable_irq(irq);
792 mutex_unlock(&menelaus->lock);
793 }
794 }
795 enable_irq(menelaus->client->irq);
796}
797
798/*
799 * We cannot use I2C in interrupt context, so we just schedule work.
800 */
801static irqreturn_t menelaus_irq(int irq, void *_menelaus)
802{
803 struct menelaus_chip *menelaus = _menelaus;
804
805 disable_irq_nosync(irq);
806 (void)schedule_work(&menelaus->work);
807
808 return IRQ_HANDLED;
809}
810
811/*-----------------------------------------------------------------------*/
812
813/*
814 * The RTC needs to be set once, then it runs on backup battery power.
815 * It supports alarms, including system wake alarms (from some modes);
816 * and 1/second IRQs if requested.
817 */
818#ifdef CONFIG_RTC_DRV_TWL92330
819
820#define RTC_CTRL_RTC_EN (1 << 0)
821#define RTC_CTRL_AL_EN (1 << 1)
822#define RTC_CTRL_MODE12 (1 << 2)
823#define RTC_CTRL_EVERY_MASK (3 << 3)
824#define RTC_CTRL_EVERY_SEC (0 << 3)
825#define RTC_CTRL_EVERY_MIN (1 << 3)
826#define RTC_CTRL_EVERY_HR (2 << 3)
827#define RTC_CTRL_EVERY_DAY (3 << 3)
828
829#define RTC_UPDATE_EVERY 0x08
830
831#define RTC_HR_PM (1 << 7)
832
833static void menelaus_to_time(char *regs, struct rtc_time *t)
834{
835 t->tm_sec = bcd2bin(regs[0]);
836 t->tm_min = bcd2bin(regs[1]);
837 if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
838 t->tm_hour = bcd2bin(regs[2] & 0x1f) - 1;
839 if (regs[2] & RTC_HR_PM)
840 t->tm_hour += 12;
841 } else
842 t->tm_hour = bcd2bin(regs[2] & 0x3f);
843 t->tm_mday = bcd2bin(regs[3]);
844 t->tm_mon = bcd2bin(regs[4]) - 1;
845 t->tm_year = bcd2bin(regs[5]) + 100;
846}
847
848static int time_to_menelaus(struct rtc_time *t, int regnum)
849{
850 int hour, status;
851
852 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_sec));
853 if (status < 0)
854 goto fail;
855
856 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_min));
857 if (status < 0)
858 goto fail;
859
860 if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
861 hour = t->tm_hour + 1;
862 if (hour > 12)
863 hour = RTC_HR_PM | bin2bcd(hour - 12);
864 else
865 hour = bin2bcd(hour);
866 } else
867 hour = bin2bcd(t->tm_hour);
868 status = menelaus_write_reg(regnum++, hour);
869 if (status < 0)
870 goto fail;
871
872 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mday));
873 if (status < 0)
874 goto fail;
875
876 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mon + 1));
877 if (status < 0)
878 goto fail;
879
880 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_year - 100));
881 if (status < 0)
882 goto fail;
883
884 return 0;
885fail:
886 dev_err(&the_menelaus->client->dev, "rtc write reg %02x, err %d\n",
887 --regnum, status);
888 return status;
889}
890
891static int menelaus_read_time(struct device *dev, struct rtc_time *t)
892{
893 struct i2c_msg msg[2];
894 char regs[7];
895 int status;
896
897 /* block read date and time registers */
898 regs[0] = MENELAUS_RTC_SEC;
899
900 msg[0].addr = MENELAUS_I2C_ADDRESS;
901 msg[0].flags = 0;
902 msg[0].len = 1;
903 msg[0].buf = regs;
904
905 msg[1].addr = MENELAUS_I2C_ADDRESS;
906 msg[1].flags = I2C_M_RD;
907 msg[1].len = sizeof(regs);
908 msg[1].buf = regs;
909
910 status = i2c_transfer(the_menelaus->client->adapter, msg, 2);
911 if (status != 2) {
912 dev_err(dev, "%s error %d\n", "read", status);
913 return -EIO;
914 }
915
916 menelaus_to_time(regs, t);
917 t->tm_wday = bcd2bin(regs[6]);
918
919 return 0;
920}
921
922static int menelaus_set_time(struct device *dev, struct rtc_time *t)
923{
924 int status;
925
926 /* write date and time registers */
927 status = time_to_menelaus(t, MENELAUS_RTC_SEC);
928 if (status < 0)
929 return status;
930 status = menelaus_write_reg(MENELAUS_RTC_WKDAY, bin2bcd(t->tm_wday));
931 if (status < 0) {
932 dev_err(&the_menelaus->client->dev, "rtc write reg %02x "
933 "err %d\n", MENELAUS_RTC_WKDAY, status);
934 return status;
935 }
936
937 /* now commit the write */
938 status = menelaus_write_reg(MENELAUS_RTC_UPDATE, RTC_UPDATE_EVERY);
939 if (status < 0)
940 dev_err(&the_menelaus->client->dev, "rtc commit time, err %d\n",
941 status);
942
943 return 0;
944}
945
946static int menelaus_read_alarm(struct device *dev, struct rtc_wkalrm *w)
947{
948 struct i2c_msg msg[2];
949 char regs[6];
950 int status;
951
952 /* block read alarm registers */
953 regs[0] = MENELAUS_RTC_AL_SEC;
954
955 msg[0].addr = MENELAUS_I2C_ADDRESS;
956 msg[0].flags = 0;
957 msg[0].len = 1;
958 msg[0].buf = regs;
959
960 msg[1].addr = MENELAUS_I2C_ADDRESS;
961 msg[1].flags = I2C_M_RD;
962 msg[1].len = sizeof(regs);
963 msg[1].buf = regs;
964
965 status = i2c_transfer(the_menelaus->client->adapter, msg, 2);
966 if (status != 2) {
967 dev_err(dev, "%s error %d\n", "alarm read", status);
968 return -EIO;
969 }
970
971 menelaus_to_time(regs, &w->time);
972
973 w->enabled = !!(the_menelaus->rtc_control & RTC_CTRL_AL_EN);
974
975 /* NOTE we *could* check if actually pending... */
976 w->pending = 0;
977
978 return 0;
979}
980
981static int menelaus_set_alarm(struct device *dev, struct rtc_wkalrm *w)
982{
983 int status;
984
985 if (the_menelaus->client->irq <= 0 && w->enabled)
986 return -ENODEV;
987
988 /* clear previous alarm enable */
989 if (the_menelaus->rtc_control & RTC_CTRL_AL_EN) {
990 the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
991 status = menelaus_write_reg(MENELAUS_RTC_CTRL,
992 the_menelaus->rtc_control);
993 if (status < 0)
994 return status;
995 }
996
997 /* write alarm registers */
998 status = time_to_menelaus(&w->time, MENELAUS_RTC_AL_SEC);
999 if (status < 0)
1000 return status;
1001
1002 /* enable alarm if requested */
1003 if (w->enabled) {
1004 the_menelaus->rtc_control |= RTC_CTRL_AL_EN;
1005 status = menelaus_write_reg(MENELAUS_RTC_CTRL,
1006 the_menelaus->rtc_control);
1007 }
1008
1009 return status;
1010}
1011
1012#ifdef CONFIG_RTC_INTF_DEV
1013
1014static void menelaus_rtc_update_work(struct menelaus_chip *m)
1015{
1016 /* report 1/sec update */
1017 local_irq_disable();
1018 rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_UF);
1019 local_irq_enable();
1020}
1021
1022static int menelaus_ioctl(struct device *dev, unsigned cmd, unsigned long arg)
1023{
1024 int status;
1025
1026 if (the_menelaus->client->irq <= 0)
1027 return -ENOIOCTLCMD;
1028
1029 switch (cmd) {
1030 /* alarm IRQ */
1031 case RTC_AIE_ON:
1032 if (the_menelaus->rtc_control & RTC_CTRL_AL_EN)
1033 return 0;
1034 the_menelaus->rtc_control |= RTC_CTRL_AL_EN;
1035 break;
1036 case RTC_AIE_OFF:
1037 if (!(the_menelaus->rtc_control & RTC_CTRL_AL_EN))
1038 return 0;
1039 the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
1040 break;
1041 /* 1/second "update" IRQ */
1042 case RTC_UIE_ON:
1043 if (the_menelaus->uie)
1044 return 0;
1045 status = menelaus_remove_irq_work(MENELAUS_RTCTMR_IRQ);
1046 status = menelaus_add_irq_work(MENELAUS_RTCTMR_IRQ,
1047 menelaus_rtc_update_work);
1048 if (status == 0)
1049 the_menelaus->uie = 1;
1050 return status;
1051 case RTC_UIE_OFF:
1052 if (!the_menelaus->uie)
1053 return 0;
1054 status = menelaus_remove_irq_work(MENELAUS_RTCTMR_IRQ);
1055 if (status == 0)
1056 the_menelaus->uie = 0;
1057 return status;
1058 default:
1059 return -ENOIOCTLCMD;
1060 }
1061 return menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
1062}
1063
1064#else
1065#define menelaus_ioctl NULL
1066#endif
1067
1068/* REVISIT no compensation register support ... */
1069
1070static const struct rtc_class_ops menelaus_rtc_ops = {
1071 .ioctl = menelaus_ioctl,
1072 .read_time = menelaus_read_time,
1073 .set_time = menelaus_set_time,
1074 .read_alarm = menelaus_read_alarm,
1075 .set_alarm = menelaus_set_alarm,
1076};
1077
1078static void menelaus_rtc_alarm_work(struct menelaus_chip *m)
1079{
1080 /* report alarm */
1081 local_irq_disable();
1082 rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_AF);
1083 local_irq_enable();
1084
1085 /* then disable it; alarms are oneshot */
1086 the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
1087 menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
1088}
1089
1090static inline void menelaus_rtc_init(struct menelaus_chip *m)
1091{
1092 int alarm = (m->client->irq > 0);
1093
1094 /* assume 32KDETEN pin is pulled high */
1095 if (!(menelaus_read_reg(MENELAUS_OSC_CTRL) & 0x80)) {
1096 dev_dbg(&m->client->dev, "no 32k oscillator\n");
1097 return;
1098 }
1099
1100 /* support RTC alarm; it can issue wakeups */
1101 if (alarm) {
1102 if (menelaus_add_irq_work(MENELAUS_RTCALM_IRQ,
1103 menelaus_rtc_alarm_work) < 0) {
1104 dev_err(&m->client->dev, "can't handle RTC alarm\n");
1105 return;
1106 }
1107 device_init_wakeup(&m->client->dev, 1);
1108 }
1109
1110 /* be sure RTC is enabled; allow 1/sec irqs; leave 12hr mode alone */
1111 m->rtc_control = menelaus_read_reg(MENELAUS_RTC_CTRL);
1112 if (!(m->rtc_control & RTC_CTRL_RTC_EN)
1113 || (m->rtc_control & RTC_CTRL_AL_EN)
1114 || (m->rtc_control & RTC_CTRL_EVERY_MASK)) {
1115 if (!(m->rtc_control & RTC_CTRL_RTC_EN)) {
1116 dev_warn(&m->client->dev, "rtc clock needs setting\n");
1117 m->rtc_control |= RTC_CTRL_RTC_EN;
1118 }
1119 m->rtc_control &= ~RTC_CTRL_EVERY_MASK;
1120 m->rtc_control &= ~RTC_CTRL_AL_EN;
1121 menelaus_write_reg(MENELAUS_RTC_CTRL, m->rtc_control);
1122 }
1123
1124 m->rtc = rtc_device_register(DRIVER_NAME,
1125 &m->client->dev,
1126 &menelaus_rtc_ops, THIS_MODULE);
1127 if (IS_ERR(m->rtc)) {
1128 if (alarm) {
1129 menelaus_remove_irq_work(MENELAUS_RTCALM_IRQ);
1130 device_init_wakeup(&m->client->dev, 0);
1131 }
1132 dev_err(&m->client->dev, "can't register RTC: %d\n",
1133 (int) PTR_ERR(m->rtc));
1134 the_menelaus->rtc = NULL;
1135 }
1136}
1137
1138#else
1139
1140static inline void menelaus_rtc_init(struct menelaus_chip *m)
1141{
1142 /* nothing */
1143}
1144
1145#endif
1146
1147/*-----------------------------------------------------------------------*/
1148
1149static struct i2c_driver menelaus_i2c_driver;
1150
1151static int menelaus_probe(struct i2c_client *client,
1152 const struct i2c_device_id *id)
1153{
1154 struct menelaus_chip *menelaus;
1155 int rev = 0, val;
1156 int err = 0;
1157 struct menelaus_platform_data *menelaus_pdata =
1158 client->dev.platform_data;
1159
1160 if (the_menelaus) {
1161 dev_dbg(&client->dev, "only one %s for now\n",
1162 DRIVER_NAME);
1163 return -ENODEV;
1164 }
1165
1166 menelaus = kzalloc(sizeof *menelaus, GFP_KERNEL);
1167 if (!menelaus)
1168 return -ENOMEM;
1169
1170 i2c_set_clientdata(client, menelaus);
1171
1172 the_menelaus = menelaus;
1173 menelaus->client = client;
1174
1175 /* If a true probe check the device */
1176 rev = menelaus_read_reg(MENELAUS_REV);
1177 if (rev < 0) {
1178 pr_err(DRIVER_NAME ": device not found");
1179 err = -ENODEV;
1180 goto fail1;
1181 }
1182
1183 /* Ack and disable all Menelaus interrupts */
1184 menelaus_write_reg(MENELAUS_INT_ACK1, 0xff);
1185 menelaus_write_reg(MENELAUS_INT_ACK2, 0xff);
1186 menelaus_write_reg(MENELAUS_INT_MASK1, 0xff);
1187 menelaus_write_reg(MENELAUS_INT_MASK2, 0xff);
1188 menelaus->mask1 = 0xff;
1189 menelaus->mask2 = 0xff;
1190
1191 /* Set output buffer strengths */
1192 menelaus_write_reg(MENELAUS_MCT_CTRL1, 0x73);
1193
1194 if (client->irq > 0) {
1195 err = request_irq(client->irq, menelaus_irq, IRQF_DISABLED,
1196 DRIVER_NAME, menelaus);
1197 if (err) {
1198 dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
1199 client->irq, err);
1200 goto fail1;
1201 }
1202 }
1203
1204 mutex_init(&menelaus->lock);
1205 INIT_WORK(&menelaus->work, menelaus_work);
1206
1207 pr_info("Menelaus rev %d.%d\n", rev >> 4, rev & 0x0f);
1208
1209 val = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
1210 if (val < 0)
1211 goto fail2;
1212 if (val & (1 << 7))
1213 menelaus->vcore_hw_mode = 1;
1214 else
1215 menelaus->vcore_hw_mode = 0;
1216
1217 if (menelaus_pdata != NULL && menelaus_pdata->late_init != NULL) {
1218 err = menelaus_pdata->late_init(&client->dev);
1219 if (err < 0)
1220 goto fail2;
1221 }
1222
1223 menelaus_rtc_init(menelaus);
1224
1225 return 0;
1226fail2:
1227 free_irq(client->irq, menelaus);
1228 flush_scheduled_work();
1229fail1:
1230 kfree(menelaus);
1231 return err;
1232}
1233
1234static int __exit menelaus_remove(struct i2c_client *client)
1235{
1236 struct menelaus_chip *menelaus = i2c_get_clientdata(client);
1237
1238 free_irq(client->irq, menelaus);
1239 kfree(menelaus);
1240 i2c_set_clientdata(client, NULL);
1241 the_menelaus = NULL;
1242 return 0;
1243}
1244
1245static const struct i2c_device_id menelaus_id[] = {
1246 { "menelaus", 0 },
1247 { }
1248};
1249MODULE_DEVICE_TABLE(i2c, menelaus_id);
1250
1251static struct i2c_driver menelaus_i2c_driver = {
1252 .driver = {
1253 .name = DRIVER_NAME,
1254 },
1255 .probe = menelaus_probe,
1256 .remove = __exit_p(menelaus_remove),
1257 .id_table = menelaus_id,
1258};
1259
1260static int __init menelaus_init(void)
1261{
1262 int res;
1263
1264 res = i2c_add_driver(&menelaus_i2c_driver);
1265 if (res < 0) {
1266 pr_err(DRIVER_NAME ": driver registration failed\n");
1267 return res;
1268 }
1269
1270 return 0;
1271}
1272
1273static void __exit menelaus_exit(void)
1274{
1275 i2c_del_driver(&menelaus_i2c_driver);
1276
1277 /* FIXME: Shutdown menelaus parts that can be shut down */
1278}
1279
1280MODULE_AUTHOR("Texas Instruments, Inc. (and others)");
1281MODULE_DESCRIPTION("I2C interface for Menelaus.");
1282MODULE_LICENSE("GPL");
1283
1284module_init(menelaus_init);
1285module_exit(menelaus_exit);
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 6c0d1bec4b76..54ddf3772e0c 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -34,6 +34,7 @@ static int mfd_add_device(struct device *parent, int id,
34 goto fail_device; 34 goto fail_device;
35 35
36 pdev->dev.parent = parent; 36 pdev->dev.parent = parent;
37 platform_set_drvdata(pdev, cell->driver_data);
37 38
38 ret = platform_device_add_data(pdev, 39 ret = platform_device_add_data(pdev,
39 cell->platform_data, cell->data_size); 40 cell->platform_data, cell->data_size);
diff --git a/drivers/mfd/tps65010.c b/drivers/mfd/tps65010.c
new file mode 100644
index 000000000000..acf8b9d5f575
--- /dev/null
+++ b/drivers/mfd/tps65010.c
@@ -0,0 +1,1072 @@
1/*
2 * tps65010 - driver for tps6501x power management chips
3 *
4 * Copyright (C) 2004 Texas Instruments
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29#include <linux/workqueue.h>
30#include <linux/debugfs.h>
31#include <linux/seq_file.h>
32#include <linux/mutex.h>
33#include <linux/platform_device.h>
34
35#include <linux/i2c/tps65010.h>
36
37#include <asm/gpio.h>
38
39
40/*-------------------------------------------------------------------------*/
41
42#define DRIVER_VERSION "2 May 2005"
43#define DRIVER_NAME (tps65010_driver.driver.name)
44
45MODULE_DESCRIPTION("TPS6501x Power Management Driver");
46MODULE_LICENSE("GPL");
47
48static struct i2c_driver tps65010_driver;
49
50/*-------------------------------------------------------------------------*/
51
52/* This driver handles a family of multipurpose chips, which incorporate
53 * voltage regulators, lithium ion/polymer battery charging, GPIOs, LEDs,
54 * and other features often needed in portable devices like cell phones
55 * or digital cameras.
56 *
57 * The tps65011 and tps65013 have different voltage settings compared
58 * to tps65010 and tps65012. The tps65013 has a NO_CHG status/irq.
59 * All except tps65010 have "wait" mode, possibly defaulted so that
60 * battery-insert != device-on.
61 *
62 * We could distinguish between some models by checking VDCDC1.UVLO or
63 * other registers, unless they've been changed already after powerup
64 * as part of board setup by a bootloader.
65 */
66enum tps_model {
67 TPS65010,
68 TPS65011,
69 TPS65012,
70 TPS65013,
71};
72
73struct tps65010 {
74 struct i2c_client *client;
75 struct mutex lock;
76 struct delayed_work work;
77 struct dentry *file;
78 unsigned charging:1;
79 unsigned por:1;
80 unsigned model:8;
81 u16 vbus;
82 unsigned long flags;
83#define FLAG_VBUS_CHANGED 0
84#define FLAG_IRQ_ENABLE 1
85
86 /* copies of last register state */
87 u8 chgstatus, regstatus, chgconf;
88 u8 nmask1, nmask2;
89
90 u8 outmask;
91 struct gpio_chip chip;
92 struct platform_device *leds;
93};
94
95#define POWER_POLL_DELAY msecs_to_jiffies(5000)
96
97/*-------------------------------------------------------------------------*/
98
99#if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
100
101static void dbg_chgstat(char *buf, size_t len, u8 chgstatus)
102{
103 snprintf(buf, len, "%02x%s%s%s%s%s%s%s%s\n",
104 chgstatus,
105 (chgstatus & TPS_CHG_USB) ? " USB" : "",
106 (chgstatus & TPS_CHG_AC) ? " AC" : "",
107 (chgstatus & TPS_CHG_THERM) ? " therm" : "",
108 (chgstatus & TPS_CHG_TERM) ? " done" :
109 ((chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
110 ? " (charging)" : ""),
111 (chgstatus & TPS_CHG_TAPER_TMO) ? " taper_tmo" : "",
112 (chgstatus & TPS_CHG_CHG_TMO) ? " charge_tmo" : "",
113 (chgstatus & TPS_CHG_PRECHG_TMO) ? " prechg_tmo" : "",
114 (chgstatus & TPS_CHG_TEMP_ERR) ? " temp_err" : "");
115}
116
117static void dbg_regstat(char *buf, size_t len, u8 regstatus)
118{
119 snprintf(buf, len, "%02x %s%s%s%s%s%s%s%s\n",
120 regstatus,
121 (regstatus & TPS_REG_ONOFF) ? "off" : "(on)",
122 (regstatus & TPS_REG_COVER) ? " uncover" : "",
123 (regstatus & TPS_REG_UVLO) ? " UVLO" : "",
124 (regstatus & TPS_REG_NO_CHG) ? " NO_CHG" : "",
125 (regstatus & TPS_REG_PG_LD02) ? " ld02_bad" : "",
126 (regstatus & TPS_REG_PG_LD01) ? " ld01_bad" : "",
127 (regstatus & TPS_REG_PG_MAIN) ? " main_bad" : "",
128 (regstatus & TPS_REG_PG_CORE) ? " core_bad" : "");
129}
130
131static void dbg_chgconf(int por, char *buf, size_t len, u8 chgconfig)
132{
133 const char *hibit;
134
135 if (por)
136 hibit = (chgconfig & TPS_CHARGE_POR)
137 ? "POR=69ms" : "POR=1sec";
138 else
139 hibit = (chgconfig & TPS65013_AUA) ? "AUA" : "";
140
141 snprintf(buf, len, "%02x %s%s%s AC=%d%% USB=%dmA %sCharge\n",
142 chgconfig, hibit,
143 (chgconfig & TPS_CHARGE_RESET) ? " reset" : "",
144 (chgconfig & TPS_CHARGE_FAST) ? " fast" : "",
145 ({int p; switch ((chgconfig >> 3) & 3) {
146 case 3: p = 100; break;
147 case 2: p = 75; break;
148 case 1: p = 50; break;
149 default: p = 25; break;
150 }; p; }),
151 (chgconfig & TPS_VBUS_CHARGING)
152 ? ((chgconfig & TPS_VBUS_500MA) ? 500 : 100)
153 : 0,
154 (chgconfig & TPS_CHARGE_ENABLE) ? "" : "No");
155}
156
157#endif
158
159#ifdef DEBUG
160
161static void show_chgstatus(const char *label, u8 chgstatus)
162{
163 char buf [100];
164
165 dbg_chgstat(buf, sizeof buf, chgstatus);
166 pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
167}
168
169static void show_regstatus(const char *label, u8 regstatus)
170{
171 char buf [100];
172
173 dbg_regstat(buf, sizeof buf, regstatus);
174 pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
175}
176
177static void show_chgconfig(int por, const char *label, u8 chgconfig)
178{
179 char buf [100];
180
181 dbg_chgconf(por, buf, sizeof buf, chgconfig);
182 pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
183}
184
185#else
186
187static inline void show_chgstatus(const char *label, u8 chgstatus) { }
188static inline void show_regstatus(const char *label, u8 chgstatus) { }
189static inline void show_chgconfig(int por, const char *label, u8 chgconfig) { }
190
191#endif
192
193#ifdef CONFIG_DEBUG_FS
194
195static int dbg_show(struct seq_file *s, void *_)
196{
197 struct tps65010 *tps = s->private;
198 u8 value, v2;
199 unsigned i;
200 char buf[100];
201 const char *chip;
202
203 switch (tps->model) {
204 case TPS65010: chip = "tps65010"; break;
205 case TPS65011: chip = "tps65011"; break;
206 case TPS65012: chip = "tps65012"; break;
207 case TPS65013: chip = "tps65013"; break;
208 default: chip = NULL; break;
209 }
210 seq_printf(s, "driver %s\nversion %s\nchip %s\n\n",
211 DRIVER_NAME, DRIVER_VERSION, chip);
212
213 mutex_lock(&tps->lock);
214
215 /* FIXME how can we tell whether a battery is present?
216 * likely involves a charge gauging chip (like BQ26501).
217 */
218
219 seq_printf(s, "%scharging\n\n", tps->charging ? "" : "(not) ");
220
221
222 /* registers for monitoring battery charging and status; note
223 * that reading chgstat and regstat may ack IRQs...
224 */
225 value = i2c_smbus_read_byte_data(tps->client, TPS_CHGCONFIG);
226 dbg_chgconf(tps->por, buf, sizeof buf, value);
227 seq_printf(s, "chgconfig %s", buf);
228
229 value = i2c_smbus_read_byte_data(tps->client, TPS_CHGSTATUS);
230 dbg_chgstat(buf, sizeof buf, value);
231 seq_printf(s, "chgstat %s", buf);
232 value = i2c_smbus_read_byte_data(tps->client, TPS_MASK1);
233 dbg_chgstat(buf, sizeof buf, value);
234 seq_printf(s, "mask1 %s", buf);
235 /* ignore ackint1 */
236
237 value = i2c_smbus_read_byte_data(tps->client, TPS_REGSTATUS);
238 dbg_regstat(buf, sizeof buf, value);
239 seq_printf(s, "regstat %s", buf);
240 value = i2c_smbus_read_byte_data(tps->client, TPS_MASK2);
241 dbg_regstat(buf, sizeof buf, value);
242 seq_printf(s, "mask2 %s\n", buf);
243 /* ignore ackint2 */
244
245 (void) schedule_delayed_work(&tps->work, POWER_POLL_DELAY);
246
247
248 /* VMAIN voltage, enable lowpower, etc */
249 value = i2c_smbus_read_byte_data(tps->client, TPS_VDCDC1);
250 seq_printf(s, "vdcdc1 %02x\n", value);
251
252 /* VCORE voltage, vibrator on/off */
253 value = i2c_smbus_read_byte_data(tps->client, TPS_VDCDC2);
254 seq_printf(s, "vdcdc2 %02x\n", value);
255
256 /* both LD0s, and their lowpower behavior */
257 value = i2c_smbus_read_byte_data(tps->client, TPS_VREGS1);
258 seq_printf(s, "vregs1 %02x\n\n", value);
259
260
261 /* LEDs and GPIOs */
262 value = i2c_smbus_read_byte_data(tps->client, TPS_LED1_ON);
263 v2 = i2c_smbus_read_byte_data(tps->client, TPS_LED1_PER);
264 seq_printf(s, "led1 %s, on=%02x, per=%02x, %d/%d msec\n",
265 (value & 0x80)
266 ? ((v2 & 0x80) ? "on" : "off")
267 : ((v2 & 0x80) ? "blink" : "(nPG)"),
268 value, v2,
269 (value & 0x7f) * 10, (v2 & 0x7f) * 100);
270
271 value = i2c_smbus_read_byte_data(tps->client, TPS_LED2_ON);
272 v2 = i2c_smbus_read_byte_data(tps->client, TPS_LED2_PER);
273 seq_printf(s, "led2 %s, on=%02x, per=%02x, %d/%d msec\n",
274 (value & 0x80)
275 ? ((v2 & 0x80) ? "on" : "off")
276 : ((v2 & 0x80) ? "blink" : "off"),
277 value, v2,
278 (value & 0x7f) * 10, (v2 & 0x7f) * 100);
279
280 value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO);
281 v2 = i2c_smbus_read_byte_data(tps->client, TPS_MASK3);
282 seq_printf(s, "defgpio %02x mask3 %02x\n", value, v2);
283
284 for (i = 0; i < 4; i++) {
285 if (value & (1 << (4 + i)))
286 seq_printf(s, " gpio%d-out %s\n", i + 1,
287 (value & (1 << i)) ? "low" : "hi ");
288 else
289 seq_printf(s, " gpio%d-in %s %s %s\n", i + 1,
290 (value & (1 << i)) ? "hi " : "low",
291 (v2 & (1 << i)) ? "no-irq" : "irq",
292 (v2 & (1 << (4 + i))) ? "rising" : "falling");
293 }
294
295 mutex_unlock(&tps->lock);
296 return 0;
297}
298
299static int dbg_tps_open(struct inode *inode, struct file *file)
300{
301 return single_open(file, dbg_show, inode->i_private);
302}
303
304static const struct file_operations debug_fops = {
305 .open = dbg_tps_open,
306 .read = seq_read,
307 .llseek = seq_lseek,
308 .release = single_release,
309};
310
311#define DEBUG_FOPS &debug_fops
312
313#else
314#define DEBUG_FOPS NULL
315#endif
316
317/*-------------------------------------------------------------------------*/
318
319/* handle IRQS in a task context, so we can use I2C calls */
320static void tps65010_interrupt(struct tps65010 *tps)
321{
322 u8 tmp = 0, mask, poll;
323
324 /* IRQs won't trigger for certain events, but we can get
325 * others by polling (normally, with external power applied).
326 */
327 poll = 0;
328
329 /* regstatus irqs */
330 if (tps->nmask2) {
331 tmp = i2c_smbus_read_byte_data(tps->client, TPS_REGSTATUS);
332 mask = tmp ^ tps->regstatus;
333 tps->regstatus = tmp;
334 mask &= tps->nmask2;
335 } else
336 mask = 0;
337 if (mask) {
338 tps->regstatus = tmp;
339 /* may need to shut something down ... */
340
341 /* "off" usually means deep sleep */
342 if (tmp & TPS_REG_ONOFF) {
343 pr_info("%s: power off button\n", DRIVER_NAME);
344#if 0
345 /* REVISIT: this might need its own workqueue
346 * plus tweaks including deadlock avoidance ...
347 * also needs to get error handling and probably
348 * an #ifdef CONFIG_HIBERNATION
349 */
350 hibernate();
351#endif
352 poll = 1;
353 }
354 }
355
356 /* chgstatus irqs */
357 if (tps->nmask1) {
358 tmp = i2c_smbus_read_byte_data(tps->client, TPS_CHGSTATUS);
359 mask = tmp ^ tps->chgstatus;
360 tps->chgstatus = tmp;
361 mask &= tps->nmask1;
362 } else
363 mask = 0;
364 if (mask) {
365 unsigned charging = 0;
366
367 show_chgstatus("chg/irq", tmp);
368 if (tmp & (TPS_CHG_USB|TPS_CHG_AC))
369 show_chgconfig(tps->por, "conf", tps->chgconf);
370
371 /* Unless it was turned off or disabled, we charge any
372 * battery whenever there's power available for it
373 * and the charger hasn't been disabled.
374 */
375 if (!(tps->chgstatus & ~(TPS_CHG_USB|TPS_CHG_AC))
376 && (tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
377 && (tps->chgconf & TPS_CHARGE_ENABLE)
378 ) {
379 if (tps->chgstatus & TPS_CHG_USB) {
380 /* VBUS options are readonly until reconnect */
381 if (mask & TPS_CHG_USB)
382 set_bit(FLAG_VBUS_CHANGED, &tps->flags);
383 charging = 1;
384 } else if (tps->chgstatus & TPS_CHG_AC)
385 charging = 1;
386 }
387 if (charging != tps->charging) {
388 tps->charging = charging;
389 pr_info("%s: battery %scharging\n",
390 DRIVER_NAME, charging ? "" :
391 ((tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
392 ? "NOT " : "dis"));
393 }
394 }
395
396 /* always poll to detect (a) power removal, without tps65013
397 * NO_CHG IRQ; or (b) restart of charging after stop.
398 */
399 if ((tps->model != TPS65013 || !tps->charging)
400 && (tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC)))
401 poll = 1;
402 if (poll)
403 (void) schedule_delayed_work(&tps->work, POWER_POLL_DELAY);
404
405 /* also potentially gpio-in rise or fall */
406}
407
408/* handle IRQs and polling using keventd for now */
409static void tps65010_work(struct work_struct *work)
410{
411 struct tps65010 *tps;
412
413 tps = container_of(work, struct tps65010, work.work);
414 mutex_lock(&tps->lock);
415
416 tps65010_interrupt(tps);
417
418 if (test_and_clear_bit(FLAG_VBUS_CHANGED, &tps->flags)) {
419 int status;
420 u8 chgconfig, tmp;
421
422 chgconfig = i2c_smbus_read_byte_data(tps->client,
423 TPS_CHGCONFIG);
424 chgconfig &= ~(TPS_VBUS_500MA | TPS_VBUS_CHARGING);
425 if (tps->vbus == 500)
426 chgconfig |= TPS_VBUS_500MA | TPS_VBUS_CHARGING;
427 else if (tps->vbus >= 100)
428 chgconfig |= TPS_VBUS_CHARGING;
429
430 status = i2c_smbus_write_byte_data(tps->client,
431 TPS_CHGCONFIG, chgconfig);
432
433 /* vbus update fails unless VBUS is connected! */
434 tmp = i2c_smbus_read_byte_data(tps->client, TPS_CHGCONFIG);
435 tps->chgconf = tmp;
436 show_chgconfig(tps->por, "update vbus", tmp);
437 }
438
439 if (test_and_clear_bit(FLAG_IRQ_ENABLE, &tps->flags))
440 enable_irq(tps->client->irq);
441
442 mutex_unlock(&tps->lock);
443}
444
445static irqreturn_t tps65010_irq(int irq, void *_tps)
446{
447 struct tps65010 *tps = _tps;
448
449 disable_irq_nosync(irq);
450 set_bit(FLAG_IRQ_ENABLE, &tps->flags);
451 (void) schedule_work(&tps->work.work);
452 return IRQ_HANDLED;
453}
454
455/*-------------------------------------------------------------------------*/
456
457/* offsets 0..3 == GPIO1..GPIO4
458 * offsets 4..5 == LED1/nPG, LED2 (we set one of the non-BLINK modes)
459 * offset 6 == vibrator motor driver
460 */
461static void
462tps65010_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
463{
464 if (offset < 4)
465 tps65010_set_gpio_out_value(offset + 1, value);
466 else if (offset < 6)
467 tps65010_set_led(offset - 3, value ? ON : OFF);
468 else
469 tps65010_set_vib(value);
470}
471
472static int
473tps65010_output(struct gpio_chip *chip, unsigned offset, int value)
474{
475 /* GPIOs may be input-only */
476 if (offset < 4) {
477 struct tps65010 *tps;
478
479 tps = container_of(chip, struct tps65010, chip);
480 if (!(tps->outmask & (1 << offset)))
481 return -EINVAL;
482 tps65010_set_gpio_out_value(offset + 1, value);
483 } else if (offset < 6)
484 tps65010_set_led(offset - 3, value ? ON : OFF);
485 else
486 tps65010_set_vib(value);
487
488 return 0;
489}
490
491static int tps65010_gpio_get(struct gpio_chip *chip, unsigned offset)
492{
493 int value;
494 struct tps65010 *tps;
495
496 tps = container_of(chip, struct tps65010, chip);
497
498 if (offset < 4) {
499 value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO);
500 if (value < 0)
501 return 0;
502 if (value & (1 << (offset + 4))) /* output */
503 return !(value & (1 << offset));
504 else /* input */
505 return (value & (1 << offset));
506 }
507
508 /* REVISIT we *could* report LED1/nPG and LED2 state ... */
509 return 0;
510}
511
512
513/*-------------------------------------------------------------------------*/
514
515static struct tps65010 *the_tps;
516
517static int __exit tps65010_remove(struct i2c_client *client)
518{
519 struct tps65010 *tps = i2c_get_clientdata(client);
520 struct tps65010_board *board = client->dev.platform_data;
521
522 if (board && board->teardown) {
523 int status = board->teardown(client, board->context);
524 if (status < 0)
525 dev_dbg(&client->dev, "board %s %s err %d\n",
526 "teardown", client->name, status);
527 }
528 if (client->irq > 0)
529 free_irq(client->irq, tps);
530 cancel_delayed_work(&tps->work);
531 flush_scheduled_work();
532 debugfs_remove(tps->file);
533 kfree(tps);
534 i2c_set_clientdata(client, NULL);
535 the_tps = NULL;
536 return 0;
537}
538
539static int tps65010_probe(struct i2c_client *client,
540 const struct i2c_device_id *id)
541{
542 struct tps65010 *tps;
543 int status;
544 struct tps65010_board *board = client->dev.platform_data;
545
546 if (the_tps) {
547 dev_dbg(&client->dev, "only one tps6501x chip allowed\n");
548 return -ENODEV;
549 }
550
551 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
552 return -EINVAL;
553
554 tps = kzalloc(sizeof *tps, GFP_KERNEL);
555 if (!tps)
556 return -ENOMEM;
557
558 mutex_init(&tps->lock);
559 INIT_DELAYED_WORK(&tps->work, tps65010_work);
560 tps->client = client;
561 tps->model = id->driver_data;
562
563 /* the IRQ is active low, but many gpio lines can't support that
564 * so this driver uses falling-edge triggers instead.
565 */
566 if (client->irq > 0) {
567 status = request_irq(client->irq, tps65010_irq,
568 IRQF_SAMPLE_RANDOM | IRQF_TRIGGER_FALLING,
569 DRIVER_NAME, tps);
570 if (status < 0) {
571 dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
572 client->irq, status);
573 goto fail1;
574 }
575 /* annoying race here, ideally we'd have an option
576 * to claim the irq now and enable it later.
577 * FIXME genirq IRQF_NOAUTOEN now solves that ...
578 */
579 disable_irq(client->irq);
580 set_bit(FLAG_IRQ_ENABLE, &tps->flags);
581 } else
582 dev_warn(&client->dev, "IRQ not configured!\n");
583
584
585 switch (tps->model) {
586 case TPS65010:
587 case TPS65012:
588 tps->por = 1;
589 break;
590 /* else CHGCONFIG.POR is replaced by AUA, enabling a WAIT mode */
591 }
592 tps->chgconf = i2c_smbus_read_byte_data(client, TPS_CHGCONFIG);
593 show_chgconfig(tps->por, "conf/init", tps->chgconf);
594
595 show_chgstatus("chg/init",
596 i2c_smbus_read_byte_data(client, TPS_CHGSTATUS));
597 show_regstatus("reg/init",
598 i2c_smbus_read_byte_data(client, TPS_REGSTATUS));
599
600 pr_debug("%s: vdcdc1 0x%02x, vdcdc2 %02x, vregs1 %02x\n", DRIVER_NAME,
601 i2c_smbus_read_byte_data(client, TPS_VDCDC1),
602 i2c_smbus_read_byte_data(client, TPS_VDCDC2),
603 i2c_smbus_read_byte_data(client, TPS_VREGS1));
604 pr_debug("%s: defgpio 0x%02x, mask3 0x%02x\n", DRIVER_NAME,
605 i2c_smbus_read_byte_data(client, TPS_DEFGPIO),
606 i2c_smbus_read_byte_data(client, TPS_MASK3));
607
608 i2c_set_clientdata(client, tps);
609 the_tps = tps;
610
611#if defined(CONFIG_USB_GADGET) && !defined(CONFIG_USB_OTG)
612 /* USB hosts can't draw VBUS. OTG devices could, later
613 * when OTG infrastructure enables it. USB peripherals
614 * could be relying on VBUS while booting, though.
615 */
616 tps->vbus = 100;
617#endif
618
619 /* unmask the "interesting" irqs, then poll once to
620 * kickstart monitoring, initialize shadowed status
621 * registers, and maybe disable VBUS draw.
622 */
623 tps->nmask1 = ~0;
624 (void) i2c_smbus_write_byte_data(client, TPS_MASK1, ~tps->nmask1);
625
626 tps->nmask2 = TPS_REG_ONOFF;
627 if (tps->model == TPS65013)
628 tps->nmask2 |= TPS_REG_NO_CHG;
629 (void) i2c_smbus_write_byte_data(client, TPS_MASK2, ~tps->nmask2);
630
631 (void) i2c_smbus_write_byte_data(client, TPS_MASK3, 0x0f
632 | i2c_smbus_read_byte_data(client, TPS_MASK3));
633
634 tps65010_work(&tps->work.work);
635
636 tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, NULL,
637 tps, DEBUG_FOPS);
638
639 /* optionally register GPIOs */
640 if (board && board->base > 0) {
641 tps->outmask = board->outmask;
642
643 tps->chip.label = client->name;
644 tps->chip.dev = &client->dev;
645 tps->chip.owner = THIS_MODULE;
646
647 tps->chip.set = tps65010_gpio_set;
648 tps->chip.direction_output = tps65010_output;
649
650 /* NOTE: only partial support for inputs; nyet IRQs */
651 tps->chip.get = tps65010_gpio_get;
652
653 tps->chip.base = board->base;
654 tps->chip.ngpio = 7;
655 tps->chip.can_sleep = 1;
656
657 status = gpiochip_add(&tps->chip);
658 if (status < 0)
659 dev_err(&client->dev, "can't add gpiochip, err %d\n",
660 status);
661 else if (board->setup) {
662 status = board->setup(client, board->context);
663 if (status < 0) {
664 dev_dbg(&client->dev,
665 "board %s %s err %d\n",
666 "setup", client->name, status);
667 status = 0;
668 }
669 }
670 }
671
672 return 0;
673fail1:
674 kfree(tps);
675 return status;
676}
677
678static const struct i2c_device_id tps65010_id[] = {
679 { "tps65010", TPS65010 },
680 { "tps65011", TPS65011 },
681 { "tps65012", TPS65012 },
682 { "tps65013", TPS65013 },
683 { "tps65014", TPS65011 }, /* tps65011 charging at 6.5V max */
684 { }
685};
686MODULE_DEVICE_TABLE(i2c, tps65010_id);
687
688static struct i2c_driver tps65010_driver = {
689 .driver = {
690 .name = "tps65010",
691 },
692 .probe = tps65010_probe,
693 .remove = __exit_p(tps65010_remove),
694 .id_table = tps65010_id,
695};
696
697/*-------------------------------------------------------------------------*/
698
699/* Draw from VBUS:
700 * 0 mA -- DON'T DRAW (might supply power instead)
701 * 100 mA -- usb unit load (slowest charge rate)
702 * 500 mA -- usb high power (fast battery charge)
703 */
704int tps65010_set_vbus_draw(unsigned mA)
705{
706 unsigned long flags;
707
708 if (!the_tps)
709 return -ENODEV;
710
711 /* assumes non-SMP */
712 local_irq_save(flags);
713 if (mA >= 500)
714 mA = 500;
715 else if (mA >= 100)
716 mA = 100;
717 else
718 mA = 0;
719 the_tps->vbus = mA;
720 if ((the_tps->chgstatus & TPS_CHG_USB)
721 && test_and_set_bit(
722 FLAG_VBUS_CHANGED, &the_tps->flags)) {
723 /* gadget drivers call this in_irq() */
724 (void) schedule_work(&the_tps->work.work);
725 }
726 local_irq_restore(flags);
727
728 return 0;
729}
730EXPORT_SYMBOL(tps65010_set_vbus_draw);
731
732/*-------------------------------------------------------------------------*/
733/* tps65010_set_gpio_out_value parameter:
734 * gpio: GPIO1, GPIO2, GPIO3 or GPIO4
735 * value: LOW or HIGH
736 */
737int tps65010_set_gpio_out_value(unsigned gpio, unsigned value)
738{
739 int status;
740 unsigned defgpio;
741
742 if (!the_tps)
743 return -ENODEV;
744 if ((gpio < GPIO1) || (gpio > GPIO4))
745 return -EINVAL;
746
747 mutex_lock(&the_tps->lock);
748
749 defgpio = i2c_smbus_read_byte_data(the_tps->client, TPS_DEFGPIO);
750
751 /* Configure GPIO for output */
752 defgpio |= 1 << (gpio + 3);
753
754 /* Writing 1 forces a logic 0 on that GPIO and vice versa */
755 switch (value) {
756 case LOW:
757 defgpio |= 1 << (gpio - 1); /* set GPIO low by writing 1 */
758 break;
759 /* case HIGH: */
760 default:
761 defgpio &= ~(1 << (gpio - 1)); /* set GPIO high by writing 0 */
762 break;
763 }
764
765 status = i2c_smbus_write_byte_data(the_tps->client,
766 TPS_DEFGPIO, defgpio);
767
768 pr_debug("%s: gpio%dout = %s, defgpio 0x%02x\n", DRIVER_NAME,
769 gpio, value ? "high" : "low",
770 i2c_smbus_read_byte_data(the_tps->client, TPS_DEFGPIO));
771
772 mutex_unlock(&the_tps->lock);
773 return status;
774}
775EXPORT_SYMBOL(tps65010_set_gpio_out_value);
776
777/*-------------------------------------------------------------------------*/
778/* tps65010_set_led parameter:
779 * led: LED1 or LED2
780 * mode: ON, OFF or BLINK
781 */
782int tps65010_set_led(unsigned led, unsigned mode)
783{
784 int status;
785 unsigned led_on, led_per, offs;
786
787 if (!the_tps)
788 return -ENODEV;
789
790 if (led == LED1)
791 offs = 0;
792 else {
793 offs = 2;
794 led = LED2;
795 }
796
797 mutex_lock(&the_tps->lock);
798
799 pr_debug("%s: led%i_on 0x%02x\n", DRIVER_NAME, led,
800 i2c_smbus_read_byte_data(the_tps->client,
801 TPS_LED1_ON + offs));
802
803 pr_debug("%s: led%i_per 0x%02x\n", DRIVER_NAME, led,
804 i2c_smbus_read_byte_data(the_tps->client,
805 TPS_LED1_PER + offs));
806
807 switch (mode) {
808 case OFF:
809 led_on = 1 << 7;
810 led_per = 0 << 7;
811 break;
812 case ON:
813 led_on = 1 << 7;
814 led_per = 1 << 7;
815 break;
816 case BLINK:
817 led_on = 0x30 | (0 << 7);
818 led_per = 0x08 | (1 << 7);
819 break;
820 default:
821 printk(KERN_ERR "%s: Wrong mode parameter for set_led()\n",
822 DRIVER_NAME);
823 mutex_unlock(&the_tps->lock);
824 return -EINVAL;
825 }
826
827 status = i2c_smbus_write_byte_data(the_tps->client,
828 TPS_LED1_ON + offs, led_on);
829
830 if (status != 0) {
831 printk(KERN_ERR "%s: Failed to write led%i_on register\n",
832 DRIVER_NAME, led);
833 mutex_unlock(&the_tps->lock);
834 return status;
835 }
836
837 pr_debug("%s: led%i_on 0x%02x\n", DRIVER_NAME, led,
838 i2c_smbus_read_byte_data(the_tps->client, TPS_LED1_ON + offs));
839
840 status = i2c_smbus_write_byte_data(the_tps->client,
841 TPS_LED1_PER + offs, led_per);
842
843 if (status != 0) {
844 printk(KERN_ERR "%s: Failed to write led%i_per register\n",
845 DRIVER_NAME, led);
846 mutex_unlock(&the_tps->lock);
847 return status;
848 }
849
850 pr_debug("%s: led%i_per 0x%02x\n", DRIVER_NAME, led,
851 i2c_smbus_read_byte_data(the_tps->client,
852 TPS_LED1_PER + offs));
853
854 mutex_unlock(&the_tps->lock);
855
856 return status;
857}
858EXPORT_SYMBOL(tps65010_set_led);
859
860/*-------------------------------------------------------------------------*/
861/* tps65010_set_vib parameter:
862 * value: ON or OFF
863 */
864int tps65010_set_vib(unsigned value)
865{
866 int status;
867 unsigned vdcdc2;
868
869 if (!the_tps)
870 return -ENODEV;
871
872 mutex_lock(&the_tps->lock);
873
874 vdcdc2 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC2);
875 vdcdc2 &= ~(1 << 1);
876 if (value)
877 vdcdc2 |= (1 << 1);
878 status = i2c_smbus_write_byte_data(the_tps->client,
879 TPS_VDCDC2, vdcdc2);
880
881 pr_debug("%s: vibrator %s\n", DRIVER_NAME, value ? "on" : "off");
882
883 mutex_unlock(&the_tps->lock);
884 return status;
885}
886EXPORT_SYMBOL(tps65010_set_vib);
887
888/*-------------------------------------------------------------------------*/
889/* tps65010_set_low_pwr parameter:
890 * mode: ON or OFF
891 */
892int tps65010_set_low_pwr(unsigned mode)
893{
894 int status;
895 unsigned vdcdc1;
896
897 if (!the_tps)
898 return -ENODEV;
899
900 mutex_lock(&the_tps->lock);
901
902 pr_debug("%s: %s low_pwr, vdcdc1 0x%02x\n", DRIVER_NAME,
903 mode ? "enable" : "disable",
904 i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
905
906 vdcdc1 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1);
907
908 switch (mode) {
909 case OFF:
910 vdcdc1 &= ~TPS_ENABLE_LP; /* disable ENABLE_LP bit */
911 break;
912 /* case ON: */
913 default:
914 vdcdc1 |= TPS_ENABLE_LP; /* enable ENABLE_LP bit */
915 break;
916 }
917
918 status = i2c_smbus_write_byte_data(the_tps->client,
919 TPS_VDCDC1, vdcdc1);
920
921 if (status != 0)
922 printk(KERN_ERR "%s: Failed to write vdcdc1 register\n",
923 DRIVER_NAME);
924 else
925 pr_debug("%s: vdcdc1 0x%02x\n", DRIVER_NAME,
926 i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
927
928 mutex_unlock(&the_tps->lock);
929
930 return status;
931}
932EXPORT_SYMBOL(tps65010_set_low_pwr);
933
934/*-------------------------------------------------------------------------*/
935/* tps65010_config_vregs1 parameter:
936 * value to be written to VREGS1 register
937 * Note: The complete register is written, set all bits you need
938 */
939int tps65010_config_vregs1(unsigned value)
940{
941 int status;
942
943 if (!the_tps)
944 return -ENODEV;
945
946 mutex_lock(&the_tps->lock);
947
948 pr_debug("%s: vregs1 0x%02x\n", DRIVER_NAME,
949 i2c_smbus_read_byte_data(the_tps->client, TPS_VREGS1));
950
951 status = i2c_smbus_write_byte_data(the_tps->client,
952 TPS_VREGS1, value);
953
954 if (status != 0)
955 printk(KERN_ERR "%s: Failed to write vregs1 register\n",
956 DRIVER_NAME);
957 else
958 pr_debug("%s: vregs1 0x%02x\n", DRIVER_NAME,
959 i2c_smbus_read_byte_data(the_tps->client, TPS_VREGS1));
960
961 mutex_unlock(&the_tps->lock);
962
963 return status;
964}
965EXPORT_SYMBOL(tps65010_config_vregs1);
966
967/*-------------------------------------------------------------------------*/
968/* tps65013_set_low_pwr parameter:
969 * mode: ON or OFF
970 */
971
972/* FIXME: Assumes AC or USB power is present. Setting AUA bit is not
973 required if power supply is through a battery */
974
975int tps65013_set_low_pwr(unsigned mode)
976{
977 int status;
978 unsigned vdcdc1, chgconfig;
979
980 if (!the_tps || the_tps->por)
981 return -ENODEV;
982
983 mutex_lock(&the_tps->lock);
984
985 pr_debug("%s: %s low_pwr, chgconfig 0x%02x vdcdc1 0x%02x\n",
986 DRIVER_NAME,
987 mode ? "enable" : "disable",
988 i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG),
989 i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
990
991 chgconfig = i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG);
992 vdcdc1 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1);
993
994 switch (mode) {
995 case OFF:
996 chgconfig &= ~TPS65013_AUA; /* disable AUA bit */
997 vdcdc1 &= ~TPS_ENABLE_LP; /* disable ENABLE_LP bit */
998 break;
999 /* case ON: */
1000 default:
1001 chgconfig |= TPS65013_AUA; /* enable AUA bit */
1002 vdcdc1 |= TPS_ENABLE_LP; /* enable ENABLE_LP bit */
1003 break;
1004 }
1005
1006 status = i2c_smbus_write_byte_data(the_tps->client,
1007 TPS_CHGCONFIG, chgconfig);
1008 if (status != 0) {
1009 printk(KERN_ERR "%s: Failed to write chconfig register\n",
1010 DRIVER_NAME);
1011 mutex_unlock(&the_tps->lock);
1012 return status;
1013 }
1014
1015 chgconfig = i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG);
1016 the_tps->chgconf = chgconfig;
1017 show_chgconfig(0, "chgconf", chgconfig);
1018
1019 status = i2c_smbus_write_byte_data(the_tps->client,
1020 TPS_VDCDC1, vdcdc1);
1021
1022 if (status != 0)
1023 printk(KERN_ERR "%s: Failed to write vdcdc1 register\n",
1024 DRIVER_NAME);
1025 else
1026 pr_debug("%s: vdcdc1 0x%02x\n", DRIVER_NAME,
1027 i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
1028
1029 mutex_unlock(&the_tps->lock);
1030
1031 return status;
1032}
1033EXPORT_SYMBOL(tps65013_set_low_pwr);
1034
1035/*-------------------------------------------------------------------------*/
1036
1037static int __init tps_init(void)
1038{
1039 u32 tries = 3;
1040 int status = -ENODEV;
1041
1042 printk(KERN_INFO "%s: version %s\n", DRIVER_NAME, DRIVER_VERSION);
1043
1044 /* some boards have startup glitches */
1045 while (tries--) {
1046 status = i2c_add_driver(&tps65010_driver);
1047 if (the_tps)
1048 break;
1049 i2c_del_driver(&tps65010_driver);
1050 if (!tries) {
1051 printk(KERN_ERR "%s: no chip?\n", DRIVER_NAME);
1052 return -ENODEV;
1053 }
1054 pr_debug("%s: re-probe ...\n", DRIVER_NAME);
1055 msleep(10);
1056 }
1057
1058 return status;
1059}
1060/* NOTE: this MUST be initialized before the other parts of the system
1061 * that rely on it ... but after the i2c bus on which this relies.
1062 * That is, much earlier than on PC-type systems, which don't often use
1063 * I2C as a core system bus.
1064 */
1065subsys_initcall(tps_init);
1066
1067static void __exit tps_exit(void)
1068{
1069 i2c_del_driver(&tps65010_driver);
1070}
1071module_exit(tps_exit);
1072
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
index dd843c4fbcc7..b59c385cbc12 100644
--- a/drivers/mfd/twl4030-core.c
+++ b/drivers/mfd/twl4030-core.c
@@ -33,6 +33,8 @@
33#include <linux/clk.h> 33#include <linux/clk.h>
34#include <linux/err.h> 34#include <linux/err.h>
35 35
36#include <linux/regulator/machine.h>
37
36#include <linux/i2c.h> 38#include <linux/i2c.h>
37#include <linux/i2c/twl4030.h> 39#include <linux/i2c/twl4030.h>
38 40
@@ -71,6 +73,13 @@
71#define twl_has_gpio() false 73#define twl_has_gpio() false
72#endif 74#endif
73 75
76#if defined(CONFIG_REGULATOR_TWL4030) \
77 || defined(CONFIG_REGULATOR_TWL4030_MODULE)
78#define twl_has_regulator() true
79#else
80#define twl_has_regulator() false
81#endif
82
74#if defined(CONFIG_TWL4030_MADC) || defined(CONFIG_TWL4030_MADC_MODULE) 83#if defined(CONFIG_TWL4030_MADC) || defined(CONFIG_TWL4030_MADC_MODULE)
75#define twl_has_madc() true 84#define twl_has_madc() true
76#else 85#else
@@ -149,6 +158,10 @@
149#define HIGH_PERF_SQ (1 << 3) 158#define HIGH_PERF_SQ (1 << 3)
150 159
151 160
161/* chip-specific feature flags, for i2c_device_id.driver_data */
162#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
163#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
164
152/*----------------------------------------------------------------------*/ 165/*----------------------------------------------------------------------*/
153 166
154/* is driver active, bound to a chip? */ 167/* is driver active, bound to a chip? */
@@ -225,7 +238,7 @@ static struct twl4030mapping twl4030_map[TWL4030_MODULE_LAST + 1] = {
225 * 238 *
226 * Returns the result of operation - 0 is success 239 * Returns the result of operation - 0 is success
227 */ 240 */
228int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, u8 num_bytes) 241int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
229{ 242{
230 int ret; 243 int ret;
231 int sid; 244 int sid;
@@ -274,7 +287,7 @@ EXPORT_SYMBOL(twl4030_i2c_write);
274 * 287 *
275 * Returns result of operation - num_bytes is success else failure. 288 * Returns result of operation - num_bytes is success else failure.
276 */ 289 */
277int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, u8 num_bytes) 290int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
278{ 291{
279 int ret; 292 int ret;
280 u8 val; 293 u8 val;
@@ -352,258 +365,258 @@ EXPORT_SYMBOL(twl4030_i2c_read_u8);
352 365
353/*----------------------------------------------------------------------*/ 366/*----------------------------------------------------------------------*/
354 367
355/* 368static struct device *
356 * NOTE: We know the first 8 IRQs after pdata->base_irq are 369add_numbered_child(unsigned chip, const char *name, int num,
357 * for the PIH, and the next are for the PWR_INT SIH, since 370 void *pdata, unsigned pdata_len,
358 * that's how twl_init_irq() sets things up. 371 bool can_wakeup, int irq0, int irq1)
359 */
360
361static int add_children(struct twl4030_platform_data *pdata)
362{ 372{
363 struct platform_device *pdev = NULL; 373 struct platform_device *pdev;
364 struct twl4030_client *twl = NULL; 374 struct twl4030_client *twl = &twl4030_modules[chip];
365 int status = 0; 375 int status;
376
377 pdev = platform_device_alloc(name, num);
378 if (!pdev) {
379 dev_dbg(&twl->client->dev, "can't alloc dev\n");
380 status = -ENOMEM;
381 goto err;
382 }
366 383
367 if (twl_has_bci() && pdata->bci) { 384 device_init_wakeup(&pdev->dev, can_wakeup);
368 twl = &twl4030_modules[3]; 385 pdev->dev.parent = &twl->client->dev;
369 386
370 pdev = platform_device_alloc("twl4030_bci", -1); 387 if (pdata) {
371 if (!pdev) { 388 status = platform_device_add_data(pdev, pdata, pdata_len);
372 pr_debug("%s: can't alloc bci dev\n", DRIVER_NAME); 389 if (status < 0) {
373 status = -ENOMEM; 390 dev_dbg(&pdev->dev, "can't add platform_data\n");
374 goto err; 391 goto err;
375 } 392 }
393 }
376 394
377 if (status == 0) { 395 if (irq0) {
378 pdev->dev.parent = &twl->client->dev; 396 struct resource r[2] = {
379 status = platform_device_add_data(pdev, pdata->bci, 397 { .start = irq0, .flags = IORESOURCE_IRQ, },
380 sizeof(*pdata->bci)); 398 { .start = irq1, .flags = IORESOURCE_IRQ, },
381 if (status < 0) { 399 };
382 dev_dbg(&twl->client->dev,
383 "can't add bci data, %d\n",
384 status);
385 goto err;
386 }
387 }
388
389 if (status == 0) {
390 struct resource r = {
391 .start = pdata->irq_base + 8 + 1,
392 .flags = IORESOURCE_IRQ,
393 };
394
395 status = platform_device_add_resources(pdev, &r, 1);
396 }
397
398 if (status == 0)
399 status = platform_device_add(pdev);
400 400
401 status = platform_device_add_resources(pdev, r, irq1 ? 2 : 1);
401 if (status < 0) { 402 if (status < 0) {
402 platform_device_put(pdev); 403 dev_dbg(&pdev->dev, "can't add irqs\n");
403 dev_dbg(&twl->client->dev,
404 "can't create bci dev, %d\n",
405 status);
406 goto err; 404 goto err;
407 } 405 }
408 } 406 }
409 407
410 if (twl_has_gpio() && pdata->gpio) { 408 status = platform_device_add(pdev);
411 twl = &twl4030_modules[1];
412 409
413 pdev = platform_device_alloc("twl4030_gpio", -1); 410err:
414 if (!pdev) { 411 if (status < 0) {
415 pr_debug("%s: can't alloc gpio dev\n", DRIVER_NAME); 412 platform_device_put(pdev);
416 status = -ENOMEM; 413 dev_err(&twl->client->dev, "can't add %s dev\n", name);
417 goto err; 414 return ERR_PTR(status);
418 } 415 }
416 return &pdev->dev;
417}
419 418
420 /* more driver model init */ 419static inline struct device *add_child(unsigned chip, const char *name,
421 if (status == 0) { 420 void *pdata, unsigned pdata_len,
422 pdev->dev.parent = &twl->client->dev; 421 bool can_wakeup, int irq0, int irq1)
423 /* device_init_wakeup(&pdev->dev, 1); */ 422{
424 423 return add_numbered_child(chip, name, -1, pdata, pdata_len,
425 status = platform_device_add_data(pdev, pdata->gpio, 424 can_wakeup, irq0, irq1);
426 sizeof(*pdata->gpio)); 425}
427 if (status < 0) {
428 dev_dbg(&twl->client->dev,
429 "can't add gpio data, %d\n",
430 status);
431 goto err;
432 }
433 }
434 426
435 /* GPIO module IRQ */ 427static struct device *
436 if (status == 0) { 428add_regulator_linked(int num, struct regulator_init_data *pdata,
437 struct resource r = { 429 struct regulator_consumer_supply *consumers,
438 .start = pdata->irq_base + 0, 430 unsigned num_consumers)
439 .flags = IORESOURCE_IRQ, 431{
440 }; 432 /* regulator framework demands init_data ... */
433 if (!pdata)
434 return NULL;
441 435
442 status = platform_device_add_resources(pdev, &r, 1); 436 if (consumers) {
443 } 437 pdata->consumer_supplies = consumers;
438 pdata->num_consumer_supplies = num_consumers;
439 }
444 440
445 if (status == 0) 441 /* NOTE: we currently ignore regulator IRQs, e.g. for short circuits */
446 status = platform_device_add(pdev); 442 return add_numbered_child(3, "twl4030_reg", num,
443 pdata, sizeof(*pdata), false, 0, 0);
444}
447 445
448 if (status < 0) { 446static struct device *
449 platform_device_put(pdev); 447add_regulator(int num, struct regulator_init_data *pdata)
450 dev_dbg(&twl->client->dev, 448{
451 "can't create gpio dev, %d\n", 449 return add_regulator_linked(num, pdata, NULL, 0);
452 status); 450}
453 goto err; 451
454 } 452/*
453 * NOTE: We know the first 8 IRQs after pdata->base_irq are
454 * for the PIH, and the next are for the PWR_INT SIH, since
455 * that's how twl_init_irq() sets things up.
456 */
457
458static int
459add_children(struct twl4030_platform_data *pdata, unsigned long features)
460{
461 struct device *child;
462 struct device *usb_transceiver = NULL;
463
464 if (twl_has_bci() && pdata->bci && !(features & TPS_SUBSET)) {
465 child = add_child(3, "twl4030_bci",
466 pdata->bci, sizeof(*pdata->bci),
467 false,
468 /* irq0 = CHG_PRES, irq1 = BCI */
469 pdata->irq_base + 8 + 1, pdata->irq_base + 2);
470 if (IS_ERR(child))
471 return PTR_ERR(child);
472 }
473
474 if (twl_has_gpio() && pdata->gpio) {
475 child = add_child(1, "twl4030_gpio",
476 pdata->gpio, sizeof(*pdata->gpio),
477 false, pdata->irq_base + 0, 0);
478 if (IS_ERR(child))
479 return PTR_ERR(child);
455 } 480 }
456 481
457 if (twl_has_keypad() && pdata->keypad) { 482 if (twl_has_keypad() && pdata->keypad) {
458 pdev = platform_device_alloc("twl4030_keypad", -1); 483 child = add_child(2, "twl4030_keypad",
459 if (pdev) { 484 pdata->keypad, sizeof(*pdata->keypad),
460 twl = &twl4030_modules[2]; 485 true, pdata->irq_base + 1, 0);
461 pdev->dev.parent = &twl->client->dev; 486 if (IS_ERR(child))
462 device_init_wakeup(&pdev->dev, 1); 487 return PTR_ERR(child);
463 status = platform_device_add_data(pdev, pdata->keypad,
464 sizeof(*pdata->keypad));
465 if (status < 0) {
466 dev_dbg(&twl->client->dev,
467 "can't add keypad data, %d\n",
468 status);
469 platform_device_put(pdev);
470 goto err;
471 }
472 status = platform_device_add(pdev);
473 if (status < 0) {
474 platform_device_put(pdev);
475 dev_dbg(&twl->client->dev,
476 "can't create keypad dev, %d\n",
477 status);
478 goto err;
479 }
480 } else {
481 pr_debug("%s: can't alloc keypad dev\n", DRIVER_NAME);
482 status = -ENOMEM;
483 goto err;
484 }
485 } 488 }
486 489
487 if (twl_has_madc() && pdata->madc) { 490 if (twl_has_madc() && pdata->madc) {
488 pdev = platform_device_alloc("twl4030_madc", -1); 491 child = add_child(2, "twl4030_madc",
489 if (pdev) { 492 pdata->madc, sizeof(*pdata->madc),
490 twl = &twl4030_modules[2]; 493 true, pdata->irq_base + 3, 0);
491 pdev->dev.parent = &twl->client->dev; 494 if (IS_ERR(child))
492 device_init_wakeup(&pdev->dev, 1); 495 return PTR_ERR(child);
493 status = platform_device_add_data(pdev, pdata->madc,
494 sizeof(*pdata->madc));
495 if (status < 0) {
496 platform_device_put(pdev);
497 dev_dbg(&twl->client->dev,
498 "can't add madc data, %d\n",
499 status);
500 goto err;
501 }
502 status = platform_device_add(pdev);
503 if (status < 0) {
504 platform_device_put(pdev);
505 dev_dbg(&twl->client->dev,
506 "can't create madc dev, %d\n",
507 status);
508 goto err;
509 }
510 } else {
511 pr_debug("%s: can't alloc madc dev\n", DRIVER_NAME);
512 status = -ENOMEM;
513 goto err;
514 }
515 } 496 }
516 497
517 if (twl_has_rtc()) { 498 if (twl_has_rtc()) {
518 twl = &twl4030_modules[3];
519
520 pdev = platform_device_alloc("twl4030_rtc", -1);
521 if (!pdev) {
522 pr_debug("%s: can't alloc rtc dev\n", DRIVER_NAME);
523 status = -ENOMEM;
524 } else {
525 pdev->dev.parent = &twl->client->dev;
526 device_init_wakeup(&pdev->dev, 1);
527 }
528
529 /* 499 /*
530 * REVISIT platform_data here currently might use of 500 * REVISIT platform_data here currently might expose the
531 * "msecure" line ... but for now we just expect board 501 * "msecure" line ... but for now we just expect board
532 * setup to tell the chip "we are secure" at all times. 502 * setup to tell the chip "it's always ok to SET_TIME".
533 * Eventually, Linux might become more aware of such 503 * Eventually, Linux might become more aware of such
534 * HW security concerns, and "least privilege". 504 * HW security concerns, and "least privilege".
535 */ 505 */
536 506 child = add_child(3, "twl4030_rtc",
537 /* RTC module IRQ */ 507 NULL, 0,
538 if (status == 0) { 508 true, pdata->irq_base + 8 + 3, 0);
539 struct resource r = { 509 if (IS_ERR(child))
540 .start = pdata->irq_base + 8 + 3, 510 return PTR_ERR(child);
541 .flags = IORESOURCE_IRQ,
542 };
543
544 status = platform_device_add_resources(pdev, &r, 1);
545 }
546
547 if (status == 0)
548 status = platform_device_add(pdev);
549
550 if (status < 0) {
551 platform_device_put(pdev);
552 dev_dbg(&twl->client->dev,
553 "can't create rtc dev, %d\n",
554 status);
555 goto err;
556 }
557 } 511 }
558 512
559 if (twl_has_usb() && pdata->usb) { 513 if (twl_has_usb() && pdata->usb) {
560 twl = &twl4030_modules[0]; 514 child = add_child(0, "twl4030_usb",
561 515 pdata->usb, sizeof(*pdata->usb),
562 pdev = platform_device_alloc("twl4030_usb", -1); 516 true,
563 if (!pdev) { 517 /* irq0 = USB_PRES, irq1 = USB */
564 pr_debug("%s: can't alloc usb dev\n", DRIVER_NAME); 518 pdata->irq_base + 8 + 2, pdata->irq_base + 4);
565 status = -ENOMEM; 519 if (IS_ERR(child))
566 goto err; 520 return PTR_ERR(child);
567 } 521
568 522 /* we need to connect regulators to this transceiver */
569 if (status == 0) { 523 usb_transceiver = child;
570 pdev->dev.parent = &twl->client->dev; 524 }
571 device_init_wakeup(&pdev->dev, 1);
572 status = platform_device_add_data(pdev, pdata->usb,
573 sizeof(*pdata->usb));
574 if (status < 0) {
575 platform_device_put(pdev);
576 dev_dbg(&twl->client->dev,
577 "can't add usb data, %d\n",
578 status);
579 goto err;
580 }
581 }
582
583 if (status == 0) {
584 struct resource r = {
585 .start = pdata->irq_base + 8 + 2,
586 .flags = IORESOURCE_IRQ,
587 };
588 525
589 status = platform_device_add_resources(pdev, &r, 1); 526 if (twl_has_regulator()) {
590 } 527 /*
528 child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1);
529 if (IS_ERR(child))
530 return PTR_ERR(child);
531 */
532
533 child = add_regulator(TWL4030_REG_VMMC1, pdata->vmmc1);
534 if (IS_ERR(child))
535 return PTR_ERR(child);
536
537 child = add_regulator(TWL4030_REG_VDAC, pdata->vdac);
538 if (IS_ERR(child))
539 return PTR_ERR(child);
540
541 child = add_regulator((features & TWL4030_VAUX2)
542 ? TWL4030_REG_VAUX2_4030
543 : TWL4030_REG_VAUX2,
544 pdata->vaux2);
545 if (IS_ERR(child))
546 return PTR_ERR(child);
547 }
591 548
592 if (status == 0) 549 if (twl_has_regulator() && usb_transceiver) {
593 status = platform_device_add(pdev); 550 static struct regulator_consumer_supply usb1v5 = {
551 .supply = "usb1v5",
552 };
553 static struct regulator_consumer_supply usb1v8 = {
554 .supply = "usb1v8",
555 };
556 static struct regulator_consumer_supply usb3v1 = {
557 .supply = "usb3v1",
558 };
559
560 /* this is a template that gets copied */
561 struct regulator_init_data usb_fixed = {
562 .constraints.valid_modes_mask =
563 REGULATOR_MODE_NORMAL
564 | REGULATOR_MODE_STANDBY,
565 .constraints.valid_ops_mask =
566 REGULATOR_CHANGE_MODE
567 | REGULATOR_CHANGE_STATUS,
568 };
569
570 usb1v5.dev = usb_transceiver;
571 usb1v8.dev = usb_transceiver;
572 usb3v1.dev = usb_transceiver;
573
574 child = add_regulator_linked(TWL4030_REG_VUSB1V5, &usb_fixed,
575 &usb1v5, 1);
576 if (IS_ERR(child))
577 return PTR_ERR(child);
578
579 child = add_regulator_linked(TWL4030_REG_VUSB1V8, &usb_fixed,
580 &usb1v8, 1);
581 if (IS_ERR(child))
582 return PTR_ERR(child);
583
584 child = add_regulator_linked(TWL4030_REG_VUSB3V1, &usb_fixed,
585 &usb3v1, 1);
586 if (IS_ERR(child))
587 return PTR_ERR(child);
588 }
594 589
595 if (status < 0) { 590 /* maybe add LDOs that are omitted on cost-reduced parts */
596 platform_device_put(pdev); 591 if (twl_has_regulator() && !(features & TPS_SUBSET)) {
597 dev_dbg(&twl->client->dev, 592 /*
598 "can't create usb dev, %d\n", 593 child = add_regulator(TWL4030_REG_VPLL2, pdata->vpll2);
599 status); 594 if (IS_ERR(child))
600 } 595 return PTR_ERR(child);
596 */
597
598 child = add_regulator(TWL4030_REG_VMMC2, pdata->vmmc2);
599 if (IS_ERR(child))
600 return PTR_ERR(child);
601
602 child = add_regulator(TWL4030_REG_VSIM, pdata->vsim);
603 if (IS_ERR(child))
604 return PTR_ERR(child);
605
606 child = add_regulator(TWL4030_REG_VAUX1, pdata->vaux1);
607 if (IS_ERR(child))
608 return PTR_ERR(child);
609
610 child = add_regulator(TWL4030_REG_VAUX3, pdata->vaux3);
611 if (IS_ERR(child))
612 return PTR_ERR(child);
613
614 child = add_regulator(TWL4030_REG_VAUX4, pdata->vaux4);
615 if (IS_ERR(child))
616 return PTR_ERR(child);
601 } 617 }
602 618
603err: 619 return 0;
604 if (status)
605 pr_err("failed to add twl4030's children (status %d)\n", status);
606 return status;
607} 620}
608 621
609/*----------------------------------------------------------------------*/ 622/*----------------------------------------------------------------------*/
@@ -645,12 +658,7 @@ static void __init clocks_init(void)
645 osc = clk_get(NULL, "osc_ck"); 658 osc = clk_get(NULL, "osc_ck");
646 else 659 else
647 osc = clk_get(NULL, "osc_sys_ck"); 660 osc = clk_get(NULL, "osc_sys_ck");
648#else 661
649 /* REVISIT for non-OMAP systems, pass the clock rate from
650 * board init code, using platform_data.
651 */
652 osc = ERR_PTR(-EIO);
653#endif
654 if (IS_ERR(osc)) { 662 if (IS_ERR(osc)) {
655 printk(KERN_WARNING "Skipping twl4030 internal clock init and " 663 printk(KERN_WARNING "Skipping twl4030 internal clock init and "
656 "using bootloader value (unknown osc rate)\n"); 664 "using bootloader value (unknown osc rate)\n");
@@ -660,6 +668,18 @@ static void __init clocks_init(void)
660 rate = clk_get_rate(osc); 668 rate = clk_get_rate(osc);
661 clk_put(osc); 669 clk_put(osc);
662 670
671#else
672 /* REVISIT for non-OMAP systems, pass the clock rate from
673 * board init code, using platform_data.
674 */
675 osc = ERR_PTR(-EIO);
676
677 printk(KERN_WARNING "Skipping twl4030 internal clock init and "
678 "using bootloader value (unknown osc rate)\n");
679
680 return;
681#endif
682
663 switch (rate) { 683 switch (rate) {
664 case 19200000: 684 case 19200000:
665 ctrl = HFCLK_FREQ_19p2_MHZ; 685 ctrl = HFCLK_FREQ_19p2_MHZ;
@@ -764,7 +784,7 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id)
764 goto fail; 784 goto fail;
765 } 785 }
766 786
767 status = add_children(pdata); 787 status = add_children(pdata, id->driver_data);
768fail: 788fail:
769 if (status < 0) 789 if (status < 0)
770 twl4030_remove(client); 790 twl4030_remove(client);
@@ -772,11 +792,11 @@ fail:
772} 792}
773 793
774static const struct i2c_device_id twl4030_ids[] = { 794static const struct i2c_device_id twl4030_ids[] = {
775 { "twl4030", 0 }, /* "Triton 2" */ 795 { "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
776 { "tps65950", 0 }, /* catalog version of twl4030 */ 796 { "twl5030", 0 }, /* T2 updated */
777 { "tps65930", 0 }, /* fewer LDOs and DACs; no charger */ 797 { "tps65950", 0 }, /* catalog version of twl5030 */
778 { "tps65920", 0 }, /* fewer LDOs; no codec or charger */ 798 { "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
779 { "twl5030", 0 }, /* T2 updated */ 799 { "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
780 { /* end of list */ }, 800 { /* end of list */ },
781}; 801};
782MODULE_DEVICE_TABLE(i2c, twl4030_ids); 802MODULE_DEVICE_TABLE(i2c, twl4030_ids);
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index fae868a8d499..b10876036983 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -180,10 +180,15 @@ static struct completion irq_event;
180static int twl4030_irq_thread(void *data) 180static int twl4030_irq_thread(void *data)
181{ 181{
182 long irq = (long)data; 182 long irq = (long)data;
183 irq_desc_t *desc = irq_desc + irq; 183 struct irq_desc *desc = irq_to_desc(irq);
184 static unsigned i2c_errors; 184 static unsigned i2c_errors;
185 const static unsigned max_i2c_errors = 100; 185 const static unsigned max_i2c_errors = 100;
186 186
187 if (!desc) {
188 pr_err("twl4030: Invalid IRQ: %ld\n", irq);
189 return -EINVAL;
190 }
191
187 current->flags |= PF_NOFREEZE; 192 current->flags |= PF_NOFREEZE;
188 193
189 while (!kthread_should_stop()) { 194 while (!kthread_should_stop()) {
@@ -215,7 +220,13 @@ static int twl4030_irq_thread(void *data)
215 pih_isr; 220 pih_isr;
216 pih_isr >>= 1, module_irq++) { 221 pih_isr >>= 1, module_irq++) {
217 if (pih_isr & 0x1) { 222 if (pih_isr & 0x1) {
218 irq_desc_t *d = irq_desc + module_irq; 223 struct irq_desc *d = irq_to_desc(module_irq);
224
225 if (!d) {
226 pr_err("twl4030: Invalid SIH IRQ: %d\n",
227 module_irq);
228 return -EINVAL;
229 }
219 230
220 /* These can't be masked ... always warn 231 /* These can't be masked ... always warn
221 * if we get any surprises. 232 * if we get any surprises.
@@ -452,10 +463,16 @@ static void twl4030_sih_do_edge(struct work_struct *work)
452 /* Modify only the bits we know must change */ 463 /* Modify only the bits we know must change */
453 while (edge_change) { 464 while (edge_change) {
454 int i = fls(edge_change) - 1; 465 int i = fls(edge_change) - 1;
455 struct irq_desc *d = irq_desc + i + agent->irq_base; 466 struct irq_desc *d = irq_to_desc(i + agent->irq_base);
456 int byte = 1 + (i >> 2); 467 int byte = 1 + (i >> 2);
457 int off = (i & 0x3) * 2; 468 int off = (i & 0x3) * 2;
458 469
470 if (!d) {
471 pr_err("twl4030: Invalid IRQ: %d\n",
472 i + agent->irq_base);
473 return;
474 }
475
459 bytes[byte] &= ~(0x03 << off); 476 bytes[byte] &= ~(0x03 << off);
460 477
461 spin_lock_irq(&d->lock); 478 spin_lock_irq(&d->lock);
@@ -512,9 +529,14 @@ static void twl4030_sih_unmask(unsigned irq)
512static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 529static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
513{ 530{
514 struct sih_agent *sih = get_irq_chip_data(irq); 531 struct sih_agent *sih = get_irq_chip_data(irq);
515 struct irq_desc *desc = irq_desc + irq; 532 struct irq_desc *desc = irq_to_desc(irq);
516 unsigned long flags; 533 unsigned long flags;
517 534
535 if (!desc) {
536 pr_err("twl4030: Invalid IRQ: %d\n", irq);
537 return -EINVAL;
538 }
539
518 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 540 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
519 return -EINVAL; 541 return -EINVAL;
520 542
diff --git a/drivers/mfd/ucb1x00-assabet.c b/drivers/mfd/ucb1x00-assabet.c
index 61aeaf79640d..86fed4870f93 100644
--- a/drivers/mfd/ucb1x00-assabet.c
+++ b/drivers/mfd/ucb1x00-assabet.c
@@ -15,7 +15,7 @@
15#include <linux/proc_fs.h> 15#include <linux/proc_fs.h>
16#include <linux/device.h> 16#include <linux/device.h>
17 17
18#include <asm/dma.h> 18#include <mach/dma.h>
19 19
20#include "ucb1x00.h" 20#include "ucb1x00.h"
21 21
diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c
index a316f1b75933..6860c924f364 100644
--- a/drivers/mfd/ucb1x00-core.c
+++ b/drivers/mfd/ucb1x00-core.c
@@ -25,7 +25,7 @@
25#include <linux/device.h> 25#include <linux/device.h>
26#include <linux/mutex.h> 26#include <linux/mutex.h>
27 27
28#include <asm/dma.h> 28#include <mach/dma.h>
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30 30
31#include "ucb1x00.h" 31#include "ucb1x00.h"
diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c
index 44762ca86a8d..61b7d3eb9a2f 100644
--- a/drivers/mfd/ucb1x00-ts.c
+++ b/drivers/mfd/ucb1x00-ts.c
@@ -31,7 +31,7 @@
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/kthread.h> 32#include <linux/kthread.h>
33 33
34#include <asm/dma.h> 34#include <mach/dma.h>
35#include <mach/collie.h> 35#include <mach/collie.h>
36#include <asm/mach-types.h> 36#include <asm/mach-types.h>
37 37
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index 0d47fb9e4b3b..f92595c8f165 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -63,7 +63,6 @@
63 */ 63 */
64static DEFINE_MUTEX(io_mutex); 64static DEFINE_MUTEX(io_mutex);
65static DEFINE_MUTEX(reg_lock_mutex); 65static DEFINE_MUTEX(reg_lock_mutex);
66static DEFINE_MUTEX(auxadc_mutex);
67 66
68/* Perform a physical read from the device. 67/* Perform a physical read from the device.
69 */ 68 */
@@ -299,6 +298,13 @@ int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
299} 298}
300EXPORT_SYMBOL_GPL(wm8350_block_write); 299EXPORT_SYMBOL_GPL(wm8350_block_write);
301 300
301/**
302 * wm8350_reg_lock()
303 *
304 * The WM8350 has a hardware lock which can be used to prevent writes to
305 * some registers (generally those which can cause particularly serious
306 * problems if misused). This function enables that lock.
307 */
302int wm8350_reg_lock(struct wm8350 *wm8350) 308int wm8350_reg_lock(struct wm8350 *wm8350)
303{ 309{
304 u16 key = WM8350_LOCK_KEY; 310 u16 key = WM8350_LOCK_KEY;
@@ -314,6 +320,15 @@ int wm8350_reg_lock(struct wm8350 *wm8350)
314} 320}
315EXPORT_SYMBOL_GPL(wm8350_reg_lock); 321EXPORT_SYMBOL_GPL(wm8350_reg_lock);
316 322
323/**
324 * wm8350_reg_unlock()
325 *
326 * The WM8350 has a hardware lock which can be used to prevent writes to
327 * some registers (generally those which can cause particularly serious
328 * problems if misused). This function disables that lock so updates
329 * can be performed. For maximum safety this should be done only when
330 * required.
331 */
317int wm8350_reg_unlock(struct wm8350 *wm8350) 332int wm8350_reg_unlock(struct wm8350 *wm8350)
318{ 333{
319 u16 key = WM8350_UNLOCK_KEY; 334 u16 key = WM8350_UNLOCK_KEY;
@@ -1066,38 +1081,158 @@ int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
1066} 1081}
1067EXPORT_SYMBOL_GPL(wm8350_unmask_irq); 1082EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1068 1083
1084int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
1085{
1086 u16 reg, result = 0;
1087 int tries = 5;
1088
1089 if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
1090 return -EINVAL;
1091 if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
1092 && (scale != 0 || vref != 0))
1093 return -EINVAL;
1094
1095 mutex_lock(&wm8350->auxadc_mutex);
1096
1097 /* Turn on the ADC */
1098 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1099 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
1100
1101 if (scale || vref) {
1102 reg = scale << 13;
1103 reg |= vref << 12;
1104 wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
1105 }
1106
1107 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1108 reg |= 1 << channel | WM8350_AUXADC_POLL;
1109 wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
1110
1111 do {
1112 schedule_timeout_interruptible(1);
1113 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1114 } while (tries-- && (reg & WM8350_AUXADC_POLL));
1115
1116 if (!tries)
1117 dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
1118 else
1119 result = wm8350_reg_read(wm8350,
1120 WM8350_AUX1_READBACK + channel);
1121
1122 /* Turn off the ADC */
1123 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1124 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
1125 reg & ~WM8350_AUXADC_ENA);
1126
1127 mutex_unlock(&wm8350->auxadc_mutex);
1128
1129 return result & WM8350_AUXADC_DATA1_MASK;
1130}
1131EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
1132
1069/* 1133/*
1070 * Cache is always host endian. 1134 * Cache is always host endian.
1071 */ 1135 */
1072static int wm8350_create_cache(struct wm8350 *wm8350, int mode) 1136static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
1073{ 1137{
1074 int i, ret = 0; 1138 int i, ret = 0;
1075 u16 value; 1139 u16 value;
1076 const u16 *reg_map; 1140 const u16 *reg_map;
1077 1141
1078 switch (mode) { 1142 switch (type) {
1079#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1080 case 0: 1143 case 0:
1081 reg_map = wm8350_mode0_defaults; 1144 switch (mode) {
1082 break; 1145#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1146 case 0:
1147 reg_map = wm8350_mode0_defaults;
1148 break;
1083#endif 1149#endif
1084#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1 1150#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1085 case 1: 1151 case 1:
1086 reg_map = wm8350_mode1_defaults; 1152 reg_map = wm8350_mode1_defaults;
1087 break; 1153 break;
1088#endif 1154#endif
1089#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2 1155#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1090 case 2: 1156 case 2:
1091 reg_map = wm8350_mode2_defaults; 1157 reg_map = wm8350_mode2_defaults;
1092 break; 1158 break;
1093#endif 1159#endif
1094#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3 1160#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1095 case 3: 1161 case 3:
1096 reg_map = wm8350_mode3_defaults; 1162 reg_map = wm8350_mode3_defaults;
1163 break;
1164#endif
1165 default:
1166 dev_err(wm8350->dev,
1167 "WM8350 configuration mode %d not supported\n",
1168 mode);
1169 return -EINVAL;
1170 }
1097 break; 1171 break;
1172
1173 case 1:
1174 switch (mode) {
1175#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
1176 case 0:
1177 reg_map = wm8351_mode0_defaults;
1178 break;
1179#endif
1180#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
1181 case 1:
1182 reg_map = wm8351_mode1_defaults;
1183 break;
1184#endif
1185#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
1186 case 2:
1187 reg_map = wm8351_mode2_defaults;
1188 break;
1098#endif 1189#endif
1190#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
1191 case 3:
1192 reg_map = wm8351_mode3_defaults;
1193 break;
1194#endif
1195 default:
1196 dev_err(wm8350->dev,
1197 "WM8351 configuration mode %d not supported\n",
1198 mode);
1199 return -EINVAL;
1200 }
1201 break;
1202
1203 case 2:
1204 switch (mode) {
1205#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
1206 case 0:
1207 reg_map = wm8352_mode0_defaults;
1208 break;
1209#endif
1210#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
1211 case 1:
1212 reg_map = wm8352_mode1_defaults;
1213 break;
1214#endif
1215#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
1216 case 2:
1217 reg_map = wm8352_mode2_defaults;
1218 break;
1219#endif
1220#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
1221 case 3:
1222 reg_map = wm8352_mode3_defaults;
1223 break;
1224#endif
1225 default:
1226 dev_err(wm8350->dev,
1227 "WM8352 configuration mode %d not supported\n",
1228 mode);
1229 return -EINVAL;
1230 }
1231 break;
1232
1099 default: 1233 default:
1100 dev_err(wm8350->dev, "Configuration mode %d not supported\n", 1234 dev_err(wm8350->dev,
1235 "WM835x configuration mode %d not supported\n",
1101 mode); 1236 mode);
1102 return -EINVAL; 1237 return -EINVAL;
1103 } 1238 }
@@ -1163,53 +1298,113 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1163 struct wm8350_platform_data *pdata) 1298 struct wm8350_platform_data *pdata)
1164{ 1299{
1165 int ret = -EINVAL; 1300 int ret = -EINVAL;
1166 u16 id1, id2, mask, mode; 1301 u16 id1, id2, mask_rev;
1302 u16 cust_id, mode, chip_rev;
1167 1303
1168 /* get WM8350 revision and config mode */ 1304 /* get WM8350 revision and config mode */
1169 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1); 1305 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1170 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2); 1306 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1307 wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev), &mask_rev);
1171 1308
1172 id1 = be16_to_cpu(id1); 1309 id1 = be16_to_cpu(id1);
1173 id2 = be16_to_cpu(id2); 1310 id2 = be16_to_cpu(id2);
1311 mask_rev = be16_to_cpu(mask_rev);
1174 1312
1175 if (id1 == 0x6143) { 1313 if (id1 != 0x6143) {
1176 switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) { 1314 dev_err(wm8350->dev,
1315 "Device with ID %x is not a WM8350\n", id1);
1316 ret = -ENODEV;
1317 goto err;
1318 }
1319
1320 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1321 cust_id = id2 & WM8350_CUST_ID_MASK;
1322 chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
1323 dev_info(wm8350->dev,
1324 "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
1325 mode, cust_id, mask_rev, chip_rev);
1326
1327 if (cust_id != 0) {
1328 dev_err(wm8350->dev, "Unsupported CUST_ID\n");
1329 ret = -ENODEV;
1330 goto err;
1331 }
1332
1333 switch (mask_rev) {
1334 case 0:
1335 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1336 wm8350->pmic.max_isink = WM8350_ISINK_B;
1337
1338 switch (chip_rev) {
1177 case WM8350_REV_E: 1339 case WM8350_REV_E:
1178 dev_info(wm8350->dev, "Found Rev E device\n"); 1340 dev_info(wm8350->dev, "WM8350 Rev E\n");
1179 wm8350->rev = WM8350_REV_E;
1180 break; 1341 break;
1181 case WM8350_REV_F: 1342 case WM8350_REV_F:
1182 dev_info(wm8350->dev, "Found Rev F device\n"); 1343 dev_info(wm8350->dev, "WM8350 Rev F\n");
1183 wm8350->rev = WM8350_REV_F;
1184 break; 1344 break;
1185 case WM8350_REV_G: 1345 case WM8350_REV_G:
1186 dev_info(wm8350->dev, "Found Rev G device\n"); 1346 dev_info(wm8350->dev, "WM8350 Rev G\n");
1187 wm8350->rev = WM8350_REV_G; 1347 wm8350->power.rev_g_coeff = 1;
1348 break;
1349 case WM8350_REV_H:
1350 dev_info(wm8350->dev, "WM8350 Rev H\n");
1351 wm8350->power.rev_g_coeff = 1;
1188 break; 1352 break;
1189 default: 1353 default:
1190 /* For safety we refuse to run on unknown hardware */ 1354 /* For safety we refuse to run on unknown hardware */
1191 dev_info(wm8350->dev, "Found unknown rev\n"); 1355 dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
1192 ret = -ENODEV; 1356 ret = -ENODEV;
1193 goto err; 1357 goto err;
1194 } 1358 }
1195 } else { 1359 break;
1196 dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n", 1360
1197 id1); 1361 case 1:
1362 wm8350->pmic.max_dcdc = WM8350_DCDC_4;
1363 wm8350->pmic.max_isink = WM8350_ISINK_A;
1364
1365 switch (chip_rev) {
1366 case 0:
1367 dev_info(wm8350->dev, "WM8351 Rev A\n");
1368 wm8350->power.rev_g_coeff = 1;
1369 break;
1370
1371 default:
1372 dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
1373 ret = -ENODEV;
1374 goto err;
1375 }
1376 break;
1377
1378 case 2:
1379 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1380 wm8350->pmic.max_isink = WM8350_ISINK_B;
1381
1382 switch (chip_rev) {
1383 case 0:
1384 dev_info(wm8350->dev, "WM8352 Rev A\n");
1385 wm8350->power.rev_g_coeff = 1;
1386 break;
1387
1388 default:
1389 dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
1390 ret = -ENODEV;
1391 goto err;
1392 }
1393 break;
1394
1395 default:
1396 dev_err(wm8350->dev, "Unknown MASK_REV\n");
1198 ret = -ENODEV; 1397 ret = -ENODEV;
1199 goto err; 1398 goto err;
1200 } 1399 }
1201 1400
1202 mode = id2 & WM8350_CONF_STS_MASK >> 10; 1401 ret = wm8350_create_cache(wm8350, mask_rev, mode);
1203 mask = id2 & WM8350_CUST_ID_MASK;
1204 dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
1205
1206 ret = wm8350_create_cache(wm8350, mode);
1207 if (ret < 0) { 1402 if (ret < 0) {
1208 printk(KERN_ERR "wm8350: failed to create register cache\n"); 1403 dev_err(wm8350->dev, "Failed to create register cache\n");
1209 return ret; 1404 return ret;
1210 } 1405 }
1211 1406
1212 if (pdata->init) { 1407 if (pdata && pdata->init) {
1213 ret = pdata->init(wm8350); 1408 ret = pdata->init(wm8350);
1214 if (ret != 0) { 1409 if (ret != 0) {
1215 dev_err(wm8350->dev, "Platform init() failed: %d\n", 1410 dev_err(wm8350->dev, "Platform init() failed: %d\n",
@@ -1218,6 +1413,7 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
1218 } 1413 }
1219 } 1414 }
1220 1415
1416 mutex_init(&wm8350->auxadc_mutex);
1221 mutex_init(&wm8350->irq_mutex); 1417 mutex_init(&wm8350->irq_mutex);
1222 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker); 1418 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1223 if (irq) { 1419 if (irq) {
@@ -1257,6 +1453,9 @@ void wm8350_device_exit(struct wm8350 *wm8350)
1257{ 1453{
1258 int i; 1454 int i;
1259 1455
1456 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
1457 platform_device_unregister(wm8350->pmic.led[i].pdev);
1458
1260 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++) 1459 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
1261 platform_device_unregister(wm8350->pmic.pdev[i]); 1460 platform_device_unregister(wm8350->pmic.pdev[i]);
1262 1461
diff --git a/drivers/mfd/wm8350-i2c.c b/drivers/mfd/wm8350-i2c.c
index 3e0ce0e50ea2..8d8c93217572 100644
--- a/drivers/mfd/wm8350-i2c.c
+++ b/drivers/mfd/wm8350-i2c.c
@@ -1,8 +1,6 @@
1/* 1/*
2 * wm8350-i2c.c -- Generic I2C driver for Wolfson WM8350 PMIC 2 * wm8350-i2c.c -- Generic I2C driver for Wolfson WM8350 PMIC
3 * 3 *
4 * This driver defines and configures the WM8350 for the Freescale i.MX32ADS.
5 *
6 * Copyright 2007, 2008 Wolfson Microelectronics PLC. 4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
7 * 5 *
8 * Author: Liam Girdwood 6 * Author: Liam Girdwood
@@ -99,6 +97,8 @@ static int wm8350_i2c_remove(struct i2c_client *i2c)
99 97
100static const struct i2c_device_id wm8350_i2c_id[] = { 98static const struct i2c_device_id wm8350_i2c_id[] = {
101 { "wm8350", 0 }, 99 { "wm8350", 0 },
100 { "wm8351", 0 },
101 { "wm8352", 0 },
102 { } 102 { }
103}; 103};
104MODULE_DEVICE_TABLE(i2c, wm8350_i2c_id); 104MODULE_DEVICE_TABLE(i2c, wm8350_i2c_id);
diff --git a/drivers/mfd/wm8350-regmap.c b/drivers/mfd/wm8350-regmap.c
index 974678db22cd..68887b817d17 100644
--- a/drivers/mfd/wm8350-regmap.c
+++ b/drivers/mfd/wm8350-regmap.c
@@ -1074,6 +1074,2102 @@ const u16 wm8350_mode3_defaults[] = {
1074}; 1074};
1075#endif 1075#endif
1076 1076
1077#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
1078
1079#undef WM8350_HAVE_CONFIG_MODE
1080#define WM8350_HAVE_CONFIG_MODE
1081
1082const u16 wm8351_mode0_defaults[] = {
1083 0x6143, /* R0 - Reset/ID */
1084 0x0000, /* R1 - ID */
1085 0x0001, /* R2 - Revision */
1086 0x1C02, /* R3 - System Control 1 */
1087 0x0004, /* R4 - System Control 2 */
1088 0x0000, /* R5 - System Hibernate */
1089 0x8A00, /* R6 - Interface Control */
1090 0x0000, /* R7 */
1091 0x8000, /* R8 - Power mgmt (1) */
1092 0x0000, /* R9 - Power mgmt (2) */
1093 0x0000, /* R10 - Power mgmt (3) */
1094 0x2000, /* R11 - Power mgmt (4) */
1095 0x0E00, /* R12 - Power mgmt (5) */
1096 0x0000, /* R13 - Power mgmt (6) */
1097 0x0000, /* R14 - Power mgmt (7) */
1098 0x0000, /* R15 */
1099 0x0000, /* R16 - RTC Seconds/Minutes */
1100 0x0100, /* R17 - RTC Hours/Day */
1101 0x0101, /* R18 - RTC Date/Month */
1102 0x1400, /* R19 - RTC Year */
1103 0x0000, /* R20 - Alarm Seconds/Minutes */
1104 0x0000, /* R21 - Alarm Hours/Day */
1105 0x0000, /* R22 - Alarm Date/Month */
1106 0x0320, /* R23 - RTC Time Control */
1107 0x0000, /* R24 - System Interrupts */
1108 0x0000, /* R25 - Interrupt Status 1 */
1109 0x0000, /* R26 - Interrupt Status 2 */
1110 0x0000, /* R27 */
1111 0x0000, /* R28 - Under Voltage Interrupt status */
1112 0x0000, /* R29 - Over Current Interrupt status */
1113 0x0000, /* R30 - GPIO Interrupt Status */
1114 0x0000, /* R31 - Comparator Interrupt Status */
1115 0x3FFF, /* R32 - System Interrupts Mask */
1116 0x0000, /* R33 - Interrupt Status 1 Mask */
1117 0x0000, /* R34 - Interrupt Status 2 Mask */
1118 0x0000, /* R35 */
1119 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1120 0x0000, /* R37 - Over Current Interrupt status Mask */
1121 0x0000, /* R38 - GPIO Interrupt Status Mask */
1122 0x0000, /* R39 - Comparator Interrupt Status Mask */
1123 0x0040, /* R40 - Clock Control 1 */
1124 0x0000, /* R41 - Clock Control 2 */
1125 0x3A00, /* R42 - FLL Control 1 */
1126 0x7086, /* R43 - FLL Control 2 */
1127 0xC226, /* R44 - FLL Control 3 */
1128 0x0000, /* R45 - FLL Control 4 */
1129 0x0000, /* R46 */
1130 0x0000, /* R47 */
1131 0x0000, /* R48 - DAC Control */
1132 0x0000, /* R49 */
1133 0x00C0, /* R50 - DAC Digital Volume L */
1134 0x00C0, /* R51 - DAC Digital Volume R */
1135 0x0000, /* R52 */
1136 0x0040, /* R53 - DAC LR Rate */
1137 0x0000, /* R54 - DAC Clock Control */
1138 0x0000, /* R55 */
1139 0x0000, /* R56 */
1140 0x0000, /* R57 */
1141 0x4000, /* R58 - DAC Mute */
1142 0x0000, /* R59 - DAC Mute Volume */
1143 0x0000, /* R60 - DAC Side */
1144 0x0000, /* R61 */
1145 0x0000, /* R62 */
1146 0x0000, /* R63 */
1147 0x8000, /* R64 - ADC Control */
1148 0x0000, /* R65 */
1149 0x00C0, /* R66 - ADC Digital Volume L */
1150 0x00C0, /* R67 - ADC Digital Volume R */
1151 0x0000, /* R68 - ADC Divider */
1152 0x0000, /* R69 */
1153 0x0040, /* R70 - ADC LR Rate */
1154 0x0000, /* R71 */
1155 0x0303, /* R72 - Input Control */
1156 0x0000, /* R73 - IN3 Input Control */
1157 0x0000, /* R74 - Mic Bias Control */
1158 0x0000, /* R75 */
1159 0x0000, /* R76 - Output Control */
1160 0x0000, /* R77 - Jack Detect */
1161 0x0000, /* R78 - Anti Pop Control */
1162 0x0000, /* R79 */
1163 0x0040, /* R80 - Left Input Volume */
1164 0x0040, /* R81 - Right Input Volume */
1165 0x0000, /* R82 */
1166 0x0000, /* R83 */
1167 0x0000, /* R84 */
1168 0x0000, /* R85 */
1169 0x0000, /* R86 */
1170 0x0000, /* R87 */
1171 0x0800, /* R88 - Left Mixer Control */
1172 0x1000, /* R89 - Right Mixer Control */
1173 0x0000, /* R90 */
1174 0x0000, /* R91 */
1175 0x0000, /* R92 - OUT3 Mixer Control */
1176 0x0000, /* R93 - OUT4 Mixer Control */
1177 0x0000, /* R94 */
1178 0x0000, /* R95 */
1179 0x0000, /* R96 - Output Left Mixer Volume */
1180 0x0000, /* R97 - Output Right Mixer Volume */
1181 0x0000, /* R98 - Input Mixer Volume L */
1182 0x0000, /* R99 - Input Mixer Volume R */
1183 0x0000, /* R100 - Input Mixer Volume */
1184 0x0000, /* R101 */
1185 0x0000, /* R102 */
1186 0x0000, /* R103 */
1187 0x00E4, /* R104 - OUT1L Volume */
1188 0x00E4, /* R105 - OUT1R Volume */
1189 0x00E4, /* R106 - OUT2L Volume */
1190 0x02E4, /* R107 - OUT2R Volume */
1191 0x0000, /* R108 */
1192 0x0000, /* R109 */
1193 0x0000, /* R110 */
1194 0x0000, /* R111 - BEEP Volume */
1195 0x0A00, /* R112 - AI Formating */
1196 0x0000, /* R113 - ADC DAC COMP */
1197 0x0020, /* R114 - AI ADC Control */
1198 0x0020, /* R115 - AI DAC Control */
1199 0x0000, /* R116 */
1200 0x0000, /* R117 */
1201 0x0000, /* R118 */
1202 0x0000, /* R119 */
1203 0x0000, /* R120 */
1204 0x0000, /* R121 */
1205 0x0000, /* R122 */
1206 0x0000, /* R123 */
1207 0x0000, /* R124 */
1208 0x0000, /* R125 */
1209 0x0000, /* R126 */
1210 0x0000, /* R127 */
1211 0x1FFF, /* R128 - GPIO Debounce */
1212 0x0000, /* R129 - GPIO Pin pull up Control */
1213 0x0000, /* R130 - GPIO Pull down Control */
1214 0x0000, /* R131 - GPIO Interrupt Mode */
1215 0x0000, /* R132 */
1216 0x0000, /* R133 - GPIO Control */
1217 0x0FFC, /* R134 - GPIO Configuration (i/o) */
1218 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
1219 0x0000, /* R136 */
1220 0x0000, /* R137 */
1221 0x0000, /* R138 */
1222 0x0000, /* R139 */
1223 0x0013, /* R140 - GPIO Function Select 1 */
1224 0x0000, /* R141 - GPIO Function Select 2 */
1225 0x0000, /* R142 - GPIO Function Select 3 */
1226 0x0003, /* R143 - GPIO Function Select 4 */
1227 0x0000, /* R144 - Digitiser Control (1) */
1228 0x0002, /* R145 - Digitiser Control (2) */
1229 0x0000, /* R146 */
1230 0x0000, /* R147 */
1231 0x0000, /* R148 */
1232 0x0000, /* R149 */
1233 0x0000, /* R150 */
1234 0x0000, /* R151 */
1235 0x7000, /* R152 - AUX1 Readback */
1236 0x7000, /* R153 - AUX2 Readback */
1237 0x7000, /* R154 - AUX3 Readback */
1238 0x7000, /* R155 - AUX4 Readback */
1239 0x0000, /* R156 - USB Voltage Readback */
1240 0x0000, /* R157 - LINE Voltage Readback */
1241 0x0000, /* R158 - BATT Voltage Readback */
1242 0x0000, /* R159 - Chip Temp Readback */
1243 0x0000, /* R160 */
1244 0x0000, /* R161 */
1245 0x0000, /* R162 */
1246 0x0000, /* R163 - Generic Comparator Control */
1247 0x0000, /* R164 - Generic comparator 1 */
1248 0x0000, /* R165 - Generic comparator 2 */
1249 0x0000, /* R166 - Generic comparator 3 */
1250 0x0000, /* R167 - Generic comparator 4 */
1251 0xA00F, /* R168 - Battery Charger Control 1 */
1252 0x0B06, /* R169 - Battery Charger Control 2 */
1253 0x0000, /* R170 - Battery Charger Control 3 */
1254 0x0000, /* R171 */
1255 0x0000, /* R172 - Current Sink Driver A */
1256 0x0000, /* R173 - CSA Flash control */
1257 0x0000, /* R174 */
1258 0x0000, /* R175 */
1259 0x0000, /* R176 - DCDC/LDO requested */
1260 0x032D, /* R177 - DCDC Active options */
1261 0x0000, /* R178 - DCDC Sleep options */
1262 0x0025, /* R179 - Power-check comparator */
1263 0x000E, /* R180 - DCDC1 Control */
1264 0x0000, /* R181 - DCDC1 Timeouts */
1265 0x1006, /* R182 - DCDC1 Low Power */
1266 0x0018, /* R183 - DCDC2 Control */
1267 0x0000, /* R184 - DCDC2 Timeouts */
1268 0x0000, /* R185 */
1269 0x0000, /* R186 - DCDC3 Control */
1270 0x0000, /* R187 - DCDC3 Timeouts */
1271 0x0006, /* R188 - DCDC3 Low Power */
1272 0x0000, /* R189 - DCDC4 Control */
1273 0x0000, /* R190 - DCDC4 Timeouts */
1274 0x0006, /* R191 - DCDC4 Low Power */
1275 0x0008, /* R192 */
1276 0x0000, /* R193 */
1277 0x0000, /* R194 */
1278 0x0000, /* R195 */
1279 0x0000, /* R196 */
1280 0x0006, /* R197 */
1281 0x0000, /* R198 */
1282 0x0003, /* R199 - Limit Switch Control */
1283 0x001C, /* R200 - LDO1 Control */
1284 0x0000, /* R201 - LDO1 Timeouts */
1285 0x001C, /* R202 - LDO1 Low Power */
1286 0x001B, /* R203 - LDO2 Control */
1287 0x0000, /* R204 - LDO2 Timeouts */
1288 0x001C, /* R205 - LDO2 Low Power */
1289 0x001B, /* R206 - LDO3 Control */
1290 0x0000, /* R207 - LDO3 Timeouts */
1291 0x001C, /* R208 - LDO3 Low Power */
1292 0x001B, /* R209 - LDO4 Control */
1293 0x0000, /* R210 - LDO4 Timeouts */
1294 0x001C, /* R211 - LDO4 Low Power */
1295 0x0000, /* R212 */
1296 0x0000, /* R213 */
1297 0x0000, /* R214 */
1298 0x0000, /* R215 - VCC_FAULT Masks */
1299 0x001F, /* R216 - Main Bandgap Control */
1300 0x0000, /* R217 - OSC Control */
1301 0x9000, /* R218 - RTC Tick Control */
1302 0x0000, /* R219 - Security1 */
1303 0x4000, /* R220 */
1304 0x0000, /* R221 */
1305 0x0000, /* R222 */
1306 0x0000, /* R223 */
1307 0x0000, /* R224 - Signal overrides */
1308 0x0000, /* R225 - DCDC/LDO status */
1309 0x0000, /* R226 - Charger Overides/status */
1310 0x0000, /* R227 - misc overrides */
1311 0x0000, /* R228 - Supply overrides/status 1 */
1312 0x0000, /* R229 - Supply overrides/status 2 */
1313 0xE000, /* R230 - GPIO Pin Status */
1314 0x0000, /* R231 - comparotor overrides */
1315 0x0000, /* R232 */
1316 0x0000, /* R233 - State Machine status */
1317 0x1200, /* R234 - FLL Test 1 */
1318 0x0000, /* R235 */
1319 0x8000, /* R236 */
1320 0x0000, /* R237 */
1321 0x0000, /* R238 */
1322 0x0000, /* R239 */
1323 0x0003, /* R240 */
1324 0x0000, /* R241 */
1325 0x0000, /* R242 */
1326 0x0004, /* R243 */
1327 0x0300, /* R244 */
1328 0x0000, /* R245 */
1329 0x0200, /* R246 */
1330 0x0000, /* R247 */
1331 0x1000, /* R248 - DCDC1 Test Controls */
1332 0x1000, /* R249 */
1333 0x1000, /* R250 - DCDC3 Test Controls */
1334 0x1000, /* R251 - DCDC4 Test Controls */
1335};
1336#endif
1337
1338#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
1339
1340#undef WM8350_HAVE_CONFIG_MODE
1341#define WM8350_HAVE_CONFIG_MODE
1342
1343const u16 wm8351_mode1_defaults[] = {
1344 0x6143, /* R0 - Reset/ID */
1345 0x0000, /* R1 - ID */
1346 0x0001, /* R2 - Revision */
1347 0x1C02, /* R3 - System Control 1 */
1348 0x0204, /* R4 - System Control 2 */
1349 0x0000, /* R5 - System Hibernate */
1350 0x8A00, /* R6 - Interface Control */
1351 0x0000, /* R7 */
1352 0x8000, /* R8 - Power mgmt (1) */
1353 0x0000, /* R9 - Power mgmt (2) */
1354 0x0000, /* R10 - Power mgmt (3) */
1355 0x2000, /* R11 - Power mgmt (4) */
1356 0x0E00, /* R12 - Power mgmt (5) */
1357 0x0000, /* R13 - Power mgmt (6) */
1358 0x0000, /* R14 - Power mgmt (7) */
1359 0x0000, /* R15 */
1360 0x0000, /* R16 - RTC Seconds/Minutes */
1361 0x0100, /* R17 - RTC Hours/Day */
1362 0x0101, /* R18 - RTC Date/Month */
1363 0x1400, /* R19 - RTC Year */
1364 0x0000, /* R20 - Alarm Seconds/Minutes */
1365 0x0000, /* R21 - Alarm Hours/Day */
1366 0x0000, /* R22 - Alarm Date/Month */
1367 0x0320, /* R23 - RTC Time Control */
1368 0x0000, /* R24 - System Interrupts */
1369 0x0000, /* R25 - Interrupt Status 1 */
1370 0x0000, /* R26 - Interrupt Status 2 */
1371 0x0000, /* R27 */
1372 0x0000, /* R28 - Under Voltage Interrupt status */
1373 0x0000, /* R29 - Over Current Interrupt status */
1374 0x0000, /* R30 - GPIO Interrupt Status */
1375 0x0000, /* R31 - Comparator Interrupt Status */
1376 0x3FFF, /* R32 - System Interrupts Mask */
1377 0x0000, /* R33 - Interrupt Status 1 Mask */
1378 0x0000, /* R34 - Interrupt Status 2 Mask */
1379 0x0000, /* R35 */
1380 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1381 0x0000, /* R37 - Over Current Interrupt status Mask */
1382 0x0000, /* R38 - GPIO Interrupt Status Mask */
1383 0x0000, /* R39 - Comparator Interrupt Status Mask */
1384 0x0040, /* R40 - Clock Control 1 */
1385 0x0000, /* R41 - Clock Control 2 */
1386 0x3A00, /* R42 - FLL Control 1 */
1387 0x7086, /* R43 - FLL Control 2 */
1388 0xC226, /* R44 - FLL Control 3 */
1389 0x0000, /* R45 - FLL Control 4 */
1390 0x0000, /* R46 */
1391 0x0000, /* R47 */
1392 0x0000, /* R48 - DAC Control */
1393 0x0000, /* R49 */
1394 0x00C0, /* R50 - DAC Digital Volume L */
1395 0x00C0, /* R51 - DAC Digital Volume R */
1396 0x0000, /* R52 */
1397 0x0040, /* R53 - DAC LR Rate */
1398 0x0000, /* R54 - DAC Clock Control */
1399 0x0000, /* R55 */
1400 0x0000, /* R56 */
1401 0x0000, /* R57 */
1402 0x4000, /* R58 - DAC Mute */
1403 0x0000, /* R59 - DAC Mute Volume */
1404 0x0000, /* R60 - DAC Side */
1405 0x0000, /* R61 */
1406 0x0000, /* R62 */
1407 0x0000, /* R63 */
1408 0x8000, /* R64 - ADC Control */
1409 0x0000, /* R65 */
1410 0x00C0, /* R66 - ADC Digital Volume L */
1411 0x00C0, /* R67 - ADC Digital Volume R */
1412 0x0000, /* R68 - ADC Divider */
1413 0x0000, /* R69 */
1414 0x0040, /* R70 - ADC LR Rate */
1415 0x0000, /* R71 */
1416 0x0303, /* R72 - Input Control */
1417 0x0000, /* R73 - IN3 Input Control */
1418 0x0000, /* R74 - Mic Bias Control */
1419 0x0000, /* R75 */
1420 0x0000, /* R76 - Output Control */
1421 0x0000, /* R77 - Jack Detect */
1422 0x0000, /* R78 - Anti Pop Control */
1423 0x0000, /* R79 */
1424 0x0040, /* R80 - Left Input Volume */
1425 0x0040, /* R81 - Right Input Volume */
1426 0x0000, /* R82 */
1427 0x0000, /* R83 */
1428 0x0000, /* R84 */
1429 0x0000, /* R85 */
1430 0x0000, /* R86 */
1431 0x0000, /* R87 */
1432 0x0800, /* R88 - Left Mixer Control */
1433 0x1000, /* R89 - Right Mixer Control */
1434 0x0000, /* R90 */
1435 0x0000, /* R91 */
1436 0x0000, /* R92 - OUT3 Mixer Control */
1437 0x0000, /* R93 - OUT4 Mixer Control */
1438 0x0000, /* R94 */
1439 0x0000, /* R95 */
1440 0x0000, /* R96 - Output Left Mixer Volume */
1441 0x0000, /* R97 - Output Right Mixer Volume */
1442 0x0000, /* R98 - Input Mixer Volume L */
1443 0x0000, /* R99 - Input Mixer Volume R */
1444 0x0000, /* R100 - Input Mixer Volume */
1445 0x0000, /* R101 */
1446 0x0000, /* R102 */
1447 0x0000, /* R103 */
1448 0x00E4, /* R104 - OUT1L Volume */
1449 0x00E4, /* R105 - OUT1R Volume */
1450 0x00E4, /* R106 - OUT2L Volume */
1451 0x02E4, /* R107 - OUT2R Volume */
1452 0x0000, /* R108 */
1453 0x0000, /* R109 */
1454 0x0000, /* R110 */
1455 0x0000, /* R111 - BEEP Volume */
1456 0x0A00, /* R112 - AI Formating */
1457 0x0000, /* R113 - ADC DAC COMP */
1458 0x0020, /* R114 - AI ADC Control */
1459 0x0020, /* R115 - AI DAC Control */
1460 0x0000, /* R116 */
1461 0x0000, /* R117 */
1462 0x0000, /* R118 */
1463 0x0000, /* R119 */
1464 0x0000, /* R120 */
1465 0x0000, /* R121 */
1466 0x0000, /* R122 */
1467 0x0000, /* R123 */
1468 0x0000, /* R124 */
1469 0x0000, /* R125 */
1470 0x0000, /* R126 */
1471 0x0000, /* R127 */
1472 0x1FFF, /* R128 - GPIO Debounce */
1473 0x0000, /* R129 - GPIO Pin pull up Control */
1474 0x0000, /* R130 - GPIO Pull down Control */
1475 0x0000, /* R131 - GPIO Interrupt Mode */
1476 0x0000, /* R132 */
1477 0x0000, /* R133 - GPIO Control */
1478 0x0CFB, /* R134 - GPIO Configuration (i/o) */
1479 0x0C1F, /* R135 - GPIO Pin Polarity / Type */
1480 0x0000, /* R136 */
1481 0x0000, /* R137 */
1482 0x0000, /* R138 */
1483 0x0000, /* R139 */
1484 0x0300, /* R140 - GPIO Function Select 1 */
1485 0x1110, /* R141 - GPIO Function Select 2 */
1486 0x0013, /* R142 - GPIO Function Select 3 */
1487 0x0003, /* R143 - GPIO Function Select 4 */
1488 0x0000, /* R144 - Digitiser Control (1) */
1489 0x0002, /* R145 - Digitiser Control (2) */
1490 0x0000, /* R146 */
1491 0x0000, /* R147 */
1492 0x0000, /* R148 */
1493 0x0000, /* R149 */
1494 0x0000, /* R150 */
1495 0x0000, /* R151 */
1496 0x7000, /* R152 - AUX1 Readback */
1497 0x7000, /* R153 - AUX2 Readback */
1498 0x7000, /* R154 - AUX3 Readback */
1499 0x7000, /* R155 - AUX4 Readback */
1500 0x0000, /* R156 - USB Voltage Readback */
1501 0x0000, /* R157 - LINE Voltage Readback */
1502 0x0000, /* R158 - BATT Voltage Readback */
1503 0x0000, /* R159 - Chip Temp Readback */
1504 0x0000, /* R160 */
1505 0x0000, /* R161 */
1506 0x0000, /* R162 */
1507 0x0000, /* R163 - Generic Comparator Control */
1508 0x0000, /* R164 - Generic comparator 1 */
1509 0x0000, /* R165 - Generic comparator 2 */
1510 0x0000, /* R166 - Generic comparator 3 */
1511 0x0000, /* R167 - Generic comparator 4 */
1512 0xA00F, /* R168 - Battery Charger Control 1 */
1513 0x0B06, /* R169 - Battery Charger Control 2 */
1514 0x0000, /* R170 - Battery Charger Control 3 */
1515 0x0000, /* R171 */
1516 0x0000, /* R172 - Current Sink Driver A */
1517 0x0000, /* R173 - CSA Flash control */
1518 0x0000, /* R174 */
1519 0x0000, /* R175 */
1520 0x0000, /* R176 - DCDC/LDO requested */
1521 0x032D, /* R177 - DCDC Active options */
1522 0x0000, /* R178 - DCDC Sleep options */
1523 0x0025, /* R179 - Power-check comparator */
1524 0x000E, /* R180 - DCDC1 Control */
1525 0x0C00, /* R181 - DCDC1 Timeouts */
1526 0x1006, /* R182 - DCDC1 Low Power */
1527 0x0018, /* R183 - DCDC2 Control */
1528 0x0000, /* R184 - DCDC2 Timeouts */
1529 0x0000, /* R185 */
1530 0x0026, /* R186 - DCDC3 Control */
1531 0x0400, /* R187 - DCDC3 Timeouts */
1532 0x0006, /* R188 - DCDC3 Low Power */
1533 0x0062, /* R189 - DCDC4 Control */
1534 0x0800, /* R190 - DCDC4 Timeouts */
1535 0x0006, /* R191 - DCDC4 Low Power */
1536 0x0008, /* R192 */
1537 0x0000, /* R193 */
1538 0x0000, /* R194 */
1539 0x000A, /* R195 */
1540 0x1000, /* R196 */
1541 0x0006, /* R197 */
1542 0x0000, /* R198 */
1543 0x0003, /* R199 - Limit Switch Control */
1544 0x0006, /* R200 - LDO1 Control */
1545 0x0000, /* R201 - LDO1 Timeouts */
1546 0x001C, /* R202 - LDO1 Low Power */
1547 0x0010, /* R203 - LDO2 Control */
1548 0x0C00, /* R204 - LDO2 Timeouts */
1549 0x001C, /* R205 - LDO2 Low Power */
1550 0x001F, /* R206 - LDO3 Control */
1551 0x0800, /* R207 - LDO3 Timeouts */
1552 0x001C, /* R208 - LDO3 Low Power */
1553 0x000A, /* R209 - LDO4 Control */
1554 0x0800, /* R210 - LDO4 Timeouts */
1555 0x001C, /* R211 - LDO4 Low Power */
1556 0x0000, /* R212 */
1557 0x0000, /* R213 */
1558 0x0000, /* R214 */
1559 0x0000, /* R215 - VCC_FAULT Masks */
1560 0x001F, /* R216 - Main Bandgap Control */
1561 0x0000, /* R217 - OSC Control */
1562 0x9000, /* R218 - RTC Tick Control */
1563 0x0000, /* R219 - Security1 */
1564 0x4000, /* R220 */
1565 0x0000, /* R221 */
1566 0x0000, /* R222 */
1567 0x0000, /* R223 */
1568 0x0000, /* R224 - Signal overrides */
1569 0x0000, /* R225 - DCDC/LDO status */
1570 0x0000, /* R226 - Charger Overides/status */
1571 0x0000, /* R227 - misc overrides */
1572 0x0000, /* R228 - Supply overrides/status 1 */
1573 0x0000, /* R229 - Supply overrides/status 2 */
1574 0xE000, /* R230 - GPIO Pin Status */
1575 0x0000, /* R231 - comparotor overrides */
1576 0x0000, /* R232 */
1577 0x0000, /* R233 - State Machine status */
1578 0x1200, /* R234 - FLL Test 1 */
1579 0x0000, /* R235 */
1580 0x8000, /* R236 */
1581 0x0000, /* R237 */
1582 0x0000, /* R238 */
1583 0x0000, /* R239 */
1584 0x0003, /* R240 */
1585 0x0000, /* R241 */
1586 0x0000, /* R242 */
1587 0x0004, /* R243 */
1588 0x0300, /* R244 */
1589 0x0000, /* R245 */
1590 0x0200, /* R246 */
1591 0x1000, /* R247 */
1592 0x1000, /* R248 - DCDC1 Test Controls */
1593 0x1000, /* R249 */
1594 0x1000, /* R250 - DCDC3 Test Controls */
1595 0x1000, /* R251 - DCDC4 Test Controls */
1596};
1597#endif
1598
1599#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
1600
1601#undef WM8350_HAVE_CONFIG_MODE
1602#define WM8350_HAVE_CONFIG_MODE
1603
1604const u16 wm8351_mode2_defaults[] = {
1605 0x6143, /* R0 - Reset/ID */
1606 0x0000, /* R1 - ID */
1607 0x0001, /* R2 - Revision */
1608 0x1C02, /* R3 - System Control 1 */
1609 0x0214, /* R4 - System Control 2 */
1610 0x0000, /* R5 - System Hibernate */
1611 0x8A00, /* R6 - Interface Control */
1612 0x0000, /* R7 */
1613 0x8000, /* R8 - Power mgmt (1) */
1614 0x0000, /* R9 - Power mgmt (2) */
1615 0x0000, /* R10 - Power mgmt (3) */
1616 0x2000, /* R11 - Power mgmt (4) */
1617 0x0E00, /* R12 - Power mgmt (5) */
1618 0x0000, /* R13 - Power mgmt (6) */
1619 0x0000, /* R14 - Power mgmt (7) */
1620 0x0000, /* R15 */
1621 0x0000, /* R16 - RTC Seconds/Minutes */
1622 0x0100, /* R17 - RTC Hours/Day */
1623 0x0101, /* R18 - RTC Date/Month */
1624 0x1400, /* R19 - RTC Year */
1625 0x0000, /* R20 - Alarm Seconds/Minutes */
1626 0x0000, /* R21 - Alarm Hours/Day */
1627 0x0000, /* R22 - Alarm Date/Month */
1628 0x0320, /* R23 - RTC Time Control */
1629 0x0000, /* R24 - System Interrupts */
1630 0x0000, /* R25 - Interrupt Status 1 */
1631 0x0000, /* R26 - Interrupt Status 2 */
1632 0x0000, /* R27 */
1633 0x0000, /* R28 - Under Voltage Interrupt status */
1634 0x0000, /* R29 - Over Current Interrupt status */
1635 0x0000, /* R30 - GPIO Interrupt Status */
1636 0x0000, /* R31 - Comparator Interrupt Status */
1637 0x3FFF, /* R32 - System Interrupts Mask */
1638 0x0000, /* R33 - Interrupt Status 1 Mask */
1639 0x0000, /* R34 - Interrupt Status 2 Mask */
1640 0x0000, /* R35 */
1641 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1642 0x0000, /* R37 - Over Current Interrupt status Mask */
1643 0x0000, /* R38 - GPIO Interrupt Status Mask */
1644 0x0000, /* R39 - Comparator Interrupt Status Mask */
1645 0x0040, /* R40 - Clock Control 1 */
1646 0x0000, /* R41 - Clock Control 2 */
1647 0x3A00, /* R42 - FLL Control 1 */
1648 0x7086, /* R43 - FLL Control 2 */
1649 0xC226, /* R44 - FLL Control 3 */
1650 0x0000, /* R45 - FLL Control 4 */
1651 0x0000, /* R46 */
1652 0x0000, /* R47 */
1653 0x0000, /* R48 - DAC Control */
1654 0x0000, /* R49 */
1655 0x00C0, /* R50 - DAC Digital Volume L */
1656 0x00C0, /* R51 - DAC Digital Volume R */
1657 0x0000, /* R52 */
1658 0x0040, /* R53 - DAC LR Rate */
1659 0x0000, /* R54 - DAC Clock Control */
1660 0x0000, /* R55 */
1661 0x0000, /* R56 */
1662 0x0000, /* R57 */
1663 0x4000, /* R58 - DAC Mute */
1664 0x0000, /* R59 - DAC Mute Volume */
1665 0x0000, /* R60 - DAC Side */
1666 0x0000, /* R61 */
1667 0x0000, /* R62 */
1668 0x0000, /* R63 */
1669 0x8000, /* R64 - ADC Control */
1670 0x0000, /* R65 */
1671 0x00C0, /* R66 - ADC Digital Volume L */
1672 0x00C0, /* R67 - ADC Digital Volume R */
1673 0x0000, /* R68 - ADC Divider */
1674 0x0000, /* R69 */
1675 0x0040, /* R70 - ADC LR Rate */
1676 0x0000, /* R71 */
1677 0x0303, /* R72 - Input Control */
1678 0x0000, /* R73 - IN3 Input Control */
1679 0x0000, /* R74 - Mic Bias Control */
1680 0x0000, /* R75 */
1681 0x0000, /* R76 - Output Control */
1682 0x0000, /* R77 - Jack Detect */
1683 0x0000, /* R78 - Anti Pop Control */
1684 0x0000, /* R79 */
1685 0x0040, /* R80 - Left Input Volume */
1686 0x0040, /* R81 - Right Input Volume */
1687 0x0000, /* R82 */
1688 0x0000, /* R83 */
1689 0x0000, /* R84 */
1690 0x0000, /* R85 */
1691 0x0000, /* R86 */
1692 0x0000, /* R87 */
1693 0x0800, /* R88 - Left Mixer Control */
1694 0x1000, /* R89 - Right Mixer Control */
1695 0x0000, /* R90 */
1696 0x0000, /* R91 */
1697 0x0000, /* R92 - OUT3 Mixer Control */
1698 0x0000, /* R93 - OUT4 Mixer Control */
1699 0x0000, /* R94 */
1700 0x0000, /* R95 */
1701 0x0000, /* R96 - Output Left Mixer Volume */
1702 0x0000, /* R97 - Output Right Mixer Volume */
1703 0x0000, /* R98 - Input Mixer Volume L */
1704 0x0000, /* R99 - Input Mixer Volume R */
1705 0x0000, /* R100 - Input Mixer Volume */
1706 0x0000, /* R101 */
1707 0x0000, /* R102 */
1708 0x0000, /* R103 */
1709 0x00E4, /* R104 - OUT1L Volume */
1710 0x00E4, /* R105 - OUT1R Volume */
1711 0x00E4, /* R106 - OUT2L Volume */
1712 0x02E4, /* R107 - OUT2R Volume */
1713 0x0000, /* R108 */
1714 0x0000, /* R109 */
1715 0x0000, /* R110 */
1716 0x0000, /* R111 - BEEP Volume */
1717 0x0A00, /* R112 - AI Formating */
1718 0x0000, /* R113 - ADC DAC COMP */
1719 0x0020, /* R114 - AI ADC Control */
1720 0x0020, /* R115 - AI DAC Control */
1721 0x0000, /* R116 */
1722 0x0000, /* R117 */
1723 0x0000, /* R118 */
1724 0x0000, /* R119 */
1725 0x0000, /* R120 */
1726 0x0000, /* R121 */
1727 0x0000, /* R122 */
1728 0x0000, /* R123 */
1729 0x0000, /* R124 */
1730 0x0000, /* R125 */
1731 0x0000, /* R126 */
1732 0x0000, /* R127 */
1733 0x1FFF, /* R128 - GPIO Debounce */
1734 0x0000, /* R129 - GPIO Pin pull up Control */
1735 0x0110, /* R130 - GPIO Pull down Control */
1736 0x0000, /* R131 - GPIO Interrupt Mode */
1737 0x0000, /* R132 */
1738 0x0000, /* R133 - GPIO Control */
1739 0x09FA, /* R134 - GPIO Configuration (i/o) */
1740 0x0DF6, /* R135 - GPIO Pin Polarity / Type */
1741 0x0000, /* R136 */
1742 0x0000, /* R137 */
1743 0x0000, /* R138 */
1744 0x0000, /* R139 */
1745 0x1310, /* R140 - GPIO Function Select 1 */
1746 0x0003, /* R141 - GPIO Function Select 2 */
1747 0x2000, /* R142 - GPIO Function Select 3 */
1748 0x0000, /* R143 - GPIO Function Select 4 */
1749 0x0000, /* R144 - Digitiser Control (1) */
1750 0x0002, /* R145 - Digitiser Control (2) */
1751 0x0000, /* R146 */
1752 0x0000, /* R147 */
1753 0x0000, /* R148 */
1754 0x0000, /* R149 */
1755 0x0000, /* R150 */
1756 0x0000, /* R151 */
1757 0x7000, /* R152 - AUX1 Readback */
1758 0x7000, /* R153 - AUX2 Readback */
1759 0x7000, /* R154 - AUX3 Readback */
1760 0x7000, /* R155 - AUX4 Readback */
1761 0x0000, /* R156 - USB Voltage Readback */
1762 0x0000, /* R157 - LINE Voltage Readback */
1763 0x0000, /* R158 - BATT Voltage Readback */
1764 0x0000, /* R159 - Chip Temp Readback */
1765 0x0000, /* R160 */
1766 0x0000, /* R161 */
1767 0x0000, /* R162 */
1768 0x0000, /* R163 - Generic Comparator Control */
1769 0x0000, /* R164 - Generic comparator 1 */
1770 0x0000, /* R165 - Generic comparator 2 */
1771 0x0000, /* R166 - Generic comparator 3 */
1772 0x0000, /* R167 - Generic comparator 4 */
1773 0xA00F, /* R168 - Battery Charger Control 1 */
1774 0x0B06, /* R169 - Battery Charger Control 2 */
1775 0x0000, /* R170 - Battery Charger Control 3 */
1776 0x0000, /* R171 */
1777 0x0000, /* R172 - Current Sink Driver A */
1778 0x0000, /* R173 - CSA Flash control */
1779 0x0000, /* R174 */
1780 0x0000, /* R175 */
1781 0x0000, /* R176 - DCDC/LDO requested */
1782 0x032D, /* R177 - DCDC Active options */
1783 0x0000, /* R178 - DCDC Sleep options */
1784 0x0025, /* R179 - Power-check comparator */
1785 0x001A, /* R180 - DCDC1 Control */
1786 0x0800, /* R181 - DCDC1 Timeouts */
1787 0x1006, /* R182 - DCDC1 Low Power */
1788 0x0018, /* R183 - DCDC2 Control */
1789 0x0000, /* R184 - DCDC2 Timeouts */
1790 0x0000, /* R185 */
1791 0x0056, /* R186 - DCDC3 Control */
1792 0x0400, /* R187 - DCDC3 Timeouts */
1793 0x0006, /* R188 - DCDC3 Low Power */
1794 0x0026, /* R189 - DCDC4 Control */
1795 0x0C00, /* R190 - DCDC4 Timeouts */
1796 0x0006, /* R191 - DCDC4 Low Power */
1797 0x0008, /* R192 */
1798 0x0000, /* R193 */
1799 0x0000, /* R194 */
1800 0x0026, /* R195 */
1801 0x0C00, /* R196 */
1802 0x0006, /* R197 */
1803 0x0000, /* R198 */
1804 0x0003, /* R199 - Limit Switch Control */
1805 0x001C, /* R200 - LDO1 Control */
1806 0x0400, /* R201 - LDO1 Timeouts */
1807 0x001C, /* R202 - LDO1 Low Power */
1808 0x0010, /* R203 - LDO2 Control */
1809 0x0C00, /* R204 - LDO2 Timeouts */
1810 0x001C, /* R205 - LDO2 Low Power */
1811 0x0015, /* R206 - LDO3 Control */
1812 0x0000, /* R207 - LDO3 Timeouts */
1813 0x001C, /* R208 - LDO3 Low Power */
1814 0x001A, /* R209 - LDO4 Control */
1815 0x0000, /* R210 - LDO4 Timeouts */
1816 0x001C, /* R211 - LDO4 Low Power */
1817 0x0000, /* R212 */
1818 0x0000, /* R213 */
1819 0x0000, /* R214 */
1820 0x0000, /* R215 - VCC_FAULT Masks */
1821 0x001F, /* R216 - Main Bandgap Control */
1822 0x0000, /* R217 - OSC Control */
1823 0x9000, /* R218 - RTC Tick Control */
1824 0x0000, /* R219 - Security1 */
1825 0x4000, /* R220 */
1826 0x0000, /* R221 */
1827 0x0000, /* R222 */
1828 0x0000, /* R223 */
1829 0x0000, /* R224 - Signal overrides */
1830 0x0000, /* R225 - DCDC/LDO status */
1831 0x0000, /* R226 - Charger Overides/status */
1832 0x0000, /* R227 - misc overrides */
1833 0x0000, /* R228 - Supply overrides/status 1 */
1834 0x0000, /* R229 - Supply overrides/status 2 */
1835 0xE000, /* R230 - GPIO Pin Status */
1836 0x0000, /* R231 - comparotor overrides */
1837 0x0000, /* R232 */
1838 0x0000, /* R233 - State Machine status */
1839 0x1200, /* R234 - FLL Test 1 */
1840 0x0000, /* R235 */
1841 0x8000, /* R236 */
1842 0x0000, /* R237 */
1843 0x0000, /* R238 */
1844 0x0000, /* R239 */
1845 0x0003, /* R240 */
1846 0x0000, /* R241 */
1847 0x0000, /* R242 */
1848 0x0004, /* R243 */
1849 0x0300, /* R244 */
1850 0x0000, /* R245 */
1851 0x0200, /* R246 */
1852 0x0000, /* R247 */
1853 0x1000, /* R248 - DCDC1 Test Controls */
1854 0x1000, /* R249 */
1855 0x1000, /* R250 - DCDC3 Test Controls */
1856 0x1000, /* R251 - DCDC4 Test Controls */
1857};
1858#endif
1859
1860#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
1861
1862#undef WM8350_HAVE_CONFIG_MODE
1863#define WM8350_HAVE_CONFIG_MODE
1864
1865const u16 wm8351_mode3_defaults[] = {
1866 0x6143, /* R0 - Reset/ID */
1867 0x0000, /* R1 - ID */
1868 0x0001, /* R2 - Revision */
1869 0x1C02, /* R3 - System Control 1 */
1870 0x0204, /* R4 - System Control 2 */
1871 0x0000, /* R5 - System Hibernate */
1872 0x8A00, /* R6 - Interface Control */
1873 0x0000, /* R7 */
1874 0x8000, /* R8 - Power mgmt (1) */
1875 0x0000, /* R9 - Power mgmt (2) */
1876 0x0000, /* R10 - Power mgmt (3) */
1877 0x2000, /* R11 - Power mgmt (4) */
1878 0x0E00, /* R12 - Power mgmt (5) */
1879 0x0000, /* R13 - Power mgmt (6) */
1880 0x0000, /* R14 - Power mgmt (7) */
1881 0x0000, /* R15 */
1882 0x0000, /* R16 - RTC Seconds/Minutes */
1883 0x0100, /* R17 - RTC Hours/Day */
1884 0x0101, /* R18 - RTC Date/Month */
1885 0x1400, /* R19 - RTC Year */
1886 0x0000, /* R20 - Alarm Seconds/Minutes */
1887 0x0000, /* R21 - Alarm Hours/Day */
1888 0x0000, /* R22 - Alarm Date/Month */
1889 0x0320, /* R23 - RTC Time Control */
1890 0x0000, /* R24 - System Interrupts */
1891 0x0000, /* R25 - Interrupt Status 1 */
1892 0x0000, /* R26 - Interrupt Status 2 */
1893 0x0000, /* R27 */
1894 0x0000, /* R28 - Under Voltage Interrupt status */
1895 0x0000, /* R29 - Over Current Interrupt status */
1896 0x0000, /* R30 - GPIO Interrupt Status */
1897 0x0000, /* R31 - Comparator Interrupt Status */
1898 0x3FFF, /* R32 - System Interrupts Mask */
1899 0x0000, /* R33 - Interrupt Status 1 Mask */
1900 0x0000, /* R34 - Interrupt Status 2 Mask */
1901 0x0000, /* R35 */
1902 0x0000, /* R36 - Under Voltage Interrupt status Mask */
1903 0x0000, /* R37 - Over Current Interrupt status Mask */
1904 0x0000, /* R38 - GPIO Interrupt Status Mask */
1905 0x0000, /* R39 - Comparator Interrupt Status Mask */
1906 0x0040, /* R40 - Clock Control 1 */
1907 0x0000, /* R41 - Clock Control 2 */
1908 0x3A00, /* R42 - FLL Control 1 */
1909 0x7086, /* R43 - FLL Control 2 */
1910 0xC226, /* R44 - FLL Control 3 */
1911 0x0000, /* R45 - FLL Control 4 */
1912 0x0000, /* R46 */
1913 0x0000, /* R47 */
1914 0x0000, /* R48 - DAC Control */
1915 0x0000, /* R49 */
1916 0x00C0, /* R50 - DAC Digital Volume L */
1917 0x00C0, /* R51 - DAC Digital Volume R */
1918 0x0000, /* R52 */
1919 0x0040, /* R53 - DAC LR Rate */
1920 0x0000, /* R54 - DAC Clock Control */
1921 0x0000, /* R55 */
1922 0x0000, /* R56 */
1923 0x0000, /* R57 */
1924 0x4000, /* R58 - DAC Mute */
1925 0x0000, /* R59 - DAC Mute Volume */
1926 0x0000, /* R60 - DAC Side */
1927 0x0000, /* R61 */
1928 0x0000, /* R62 */
1929 0x0000, /* R63 */
1930 0x8000, /* R64 - ADC Control */
1931 0x0000, /* R65 */
1932 0x00C0, /* R66 - ADC Digital Volume L */
1933 0x00C0, /* R67 - ADC Digital Volume R */
1934 0x0000, /* R68 - ADC Divider */
1935 0x0000, /* R69 */
1936 0x0040, /* R70 - ADC LR Rate */
1937 0x0000, /* R71 */
1938 0x0303, /* R72 - Input Control */
1939 0x0000, /* R73 - IN3 Input Control */
1940 0x0000, /* R74 - Mic Bias Control */
1941 0x0000, /* R75 */
1942 0x0000, /* R76 - Output Control */
1943 0x0000, /* R77 - Jack Detect */
1944 0x0000, /* R78 - Anti Pop Control */
1945 0x0000, /* R79 */
1946 0x0040, /* R80 - Left Input Volume */
1947 0x0040, /* R81 - Right Input Volume */
1948 0x0000, /* R82 */
1949 0x0000, /* R83 */
1950 0x0000, /* R84 */
1951 0x0000, /* R85 */
1952 0x0000, /* R86 */
1953 0x0000, /* R87 */
1954 0x0800, /* R88 - Left Mixer Control */
1955 0x1000, /* R89 - Right Mixer Control */
1956 0x0000, /* R90 */
1957 0x0000, /* R91 */
1958 0x0000, /* R92 - OUT3 Mixer Control */
1959 0x0000, /* R93 - OUT4 Mixer Control */
1960 0x0000, /* R94 */
1961 0x0000, /* R95 */
1962 0x0000, /* R96 - Output Left Mixer Volume */
1963 0x0000, /* R97 - Output Right Mixer Volume */
1964 0x0000, /* R98 - Input Mixer Volume L */
1965 0x0000, /* R99 - Input Mixer Volume R */
1966 0x0000, /* R100 - Input Mixer Volume */
1967 0x0000, /* R101 */
1968 0x0000, /* R102 */
1969 0x0000, /* R103 */
1970 0x00E4, /* R104 - OUT1L Volume */
1971 0x00E4, /* R105 - OUT1R Volume */
1972 0x00E4, /* R106 - OUT2L Volume */
1973 0x02E4, /* R107 - OUT2R Volume */
1974 0x0000, /* R108 */
1975 0x0000, /* R109 */
1976 0x0000, /* R110 */
1977 0x0000, /* R111 - BEEP Volume */
1978 0x0A00, /* R112 - AI Formating */
1979 0x0000, /* R113 - ADC DAC COMP */
1980 0x0020, /* R114 - AI ADC Control */
1981 0x0020, /* R115 - AI DAC Control */
1982 0x0000, /* R116 */
1983 0x0000, /* R117 */
1984 0x0000, /* R118 */
1985 0x0000, /* R119 */
1986 0x0000, /* R120 */
1987 0x0000, /* R121 */
1988 0x0000, /* R122 */
1989 0x0000, /* R123 */
1990 0x0000, /* R124 */
1991 0x0000, /* R125 */
1992 0x0000, /* R126 */
1993 0x0000, /* R127 */
1994 0x1FFF, /* R128 - GPIO Debounce */
1995 0x0010, /* R129 - GPIO Pin pull up Control */
1996 0x0000, /* R130 - GPIO Pull down Control */
1997 0x0000, /* R131 - GPIO Interrupt Mode */
1998 0x0000, /* R132 */
1999 0x0000, /* R133 - GPIO Control */
2000 0x0BFB, /* R134 - GPIO Configuration (i/o) */
2001 0x0FFD, /* R135 - GPIO Pin Polarity / Type */
2002 0x0000, /* R136 */
2003 0x0000, /* R137 */
2004 0x0000, /* R138 */
2005 0x0000, /* R139 */
2006 0x0310, /* R140 - GPIO Function Select 1 */
2007 0x0001, /* R141 - GPIO Function Select 2 */
2008 0x2300, /* R142 - GPIO Function Select 3 */
2009 0x0003, /* R143 - GPIO Function Select 4 */
2010 0x0000, /* R144 - Digitiser Control (1) */
2011 0x0002, /* R145 - Digitiser Control (2) */
2012 0x0000, /* R146 */
2013 0x0000, /* R147 */
2014 0x0000, /* R148 */
2015 0x0000, /* R149 */
2016 0x0000, /* R150 */
2017 0x0000, /* R151 */
2018 0x7000, /* R152 - AUX1 Readback */
2019 0x7000, /* R153 - AUX2 Readback */
2020 0x7000, /* R154 - AUX3 Readback */
2021 0x7000, /* R155 - AUX4 Readback */
2022 0x0000, /* R156 - USB Voltage Readback */
2023 0x0000, /* R157 - LINE Voltage Readback */
2024 0x0000, /* R158 - BATT Voltage Readback */
2025 0x0000, /* R159 - Chip Temp Readback */
2026 0x0000, /* R160 */
2027 0x0000, /* R161 */
2028 0x0000, /* R162 */
2029 0x0000, /* R163 - Generic Comparator Control */
2030 0x0000, /* R164 - Generic comparator 1 */
2031 0x0000, /* R165 - Generic comparator 2 */
2032 0x0000, /* R166 - Generic comparator 3 */
2033 0x0000, /* R167 - Generic comparator 4 */
2034 0xA00F, /* R168 - Battery Charger Control 1 */
2035 0x0B06, /* R169 - Battery Charger Control 2 */
2036 0x0000, /* R170 - Battery Charger Control 3 */
2037 0x0000, /* R171 */
2038 0x0000, /* R172 - Current Sink Driver A */
2039 0x0000, /* R173 - CSA Flash control */
2040 0x0000, /* R174 */
2041 0x0000, /* R175 */
2042 0x0000, /* R176 - DCDC/LDO requested */
2043 0x032D, /* R177 - DCDC Active options */
2044 0x0000, /* R178 - DCDC Sleep options */
2045 0x0025, /* R179 - Power-check comparator */
2046 0x000E, /* R180 - DCDC1 Control */
2047 0x0400, /* R181 - DCDC1 Timeouts */
2048 0x1006, /* R182 - DCDC1 Low Power */
2049 0x0018, /* R183 - DCDC2 Control */
2050 0x0000, /* R184 - DCDC2 Timeouts */
2051 0x0000, /* R185 */
2052 0x0026, /* R186 - DCDC3 Control */
2053 0x0800, /* R187 - DCDC3 Timeouts */
2054 0x0006, /* R188 - DCDC3 Low Power */
2055 0x0062, /* R189 - DCDC4 Control */
2056 0x1400, /* R190 - DCDC4 Timeouts */
2057 0x0006, /* R191 - DCDC4 Low Power */
2058 0x0008, /* R192 */
2059 0x0000, /* R193 */
2060 0x0000, /* R194 */
2061 0x0026, /* R195 */
2062 0x0400, /* R196 */
2063 0x0006, /* R197 */
2064 0x0000, /* R198 */
2065 0x0003, /* R199 - Limit Switch Control */
2066 0x0006, /* R200 - LDO1 Control */
2067 0x0C00, /* R201 - LDO1 Timeouts */
2068 0x001C, /* R202 - LDO1 Low Power */
2069 0x0016, /* R203 - LDO2 Control */
2070 0x0000, /* R204 - LDO2 Timeouts */
2071 0x001C, /* R205 - LDO2 Low Power */
2072 0x0019, /* R206 - LDO3 Control */
2073 0x0000, /* R207 - LDO3 Timeouts */
2074 0x001C, /* R208 - LDO3 Low Power */
2075 0x001A, /* R209 - LDO4 Control */
2076 0x1000, /* R210 - LDO4 Timeouts */
2077 0x001C, /* R211 - LDO4 Low Power */
2078 0x0000, /* R212 */
2079 0x0000, /* R213 */
2080 0x0000, /* R214 */
2081 0x0000, /* R215 - VCC_FAULT Masks */
2082 0x001F, /* R216 - Main Bandgap Control */
2083 0x0000, /* R217 - OSC Control */
2084 0x9000, /* R218 - RTC Tick Control */
2085 0x0000, /* R219 - Security1 */
2086 0x4000, /* R220 */
2087 0x0000, /* R221 */
2088 0x0000, /* R222 */
2089 0x0000, /* R223 */
2090 0x0000, /* R224 - Signal overrides */
2091 0x0000, /* R225 - DCDC/LDO status */
2092 0x0000, /* R226 - Charger Overides/status */
2093 0x0000, /* R227 - misc overrides */
2094 0x0000, /* R228 - Supply overrides/status 1 */
2095 0x0000, /* R229 - Supply overrides/status 2 */
2096 0xE000, /* R230 - GPIO Pin Status */
2097 0x0000, /* R231 - comparotor overrides */
2098 0x0000, /* R232 */
2099 0x0000, /* R233 - State Machine status */
2100 0x1200, /* R234 - FLL Test 1 */
2101 0x0000, /* R235 */
2102 0x8000, /* R236 */
2103 0x0000, /* R237 */
2104 0x0000, /* R238 */
2105 0x0000, /* R239 */
2106 0x0003, /* R240 */
2107 0x0000, /* R241 */
2108 0x0000, /* R242 */
2109 0x0004, /* R243 */
2110 0x0300, /* R244 */
2111 0x0000, /* R245 */
2112 0x0200, /* R246 */
2113 0x0000, /* R247 */
2114 0x1000, /* R248 - DCDC1 Test Controls */
2115 0x1000, /* R249 */
2116 0x1000, /* R250 - DCDC3 Test Controls */
2117 0x1000, /* R251 - DCDC4 Test Controls */
2118};
2119#endif
2120
2121#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
2122
2123#undef WM8350_HAVE_CONFIG_MODE
2124#define WM8350_HAVE_CONFIG_MODE
2125
2126const u16 wm8352_mode0_defaults[] = {
2127 0x6143, /* R0 - Reset/ID */
2128 0x0000, /* R1 - ID */
2129 0x0002, /* R2 - Revision */
2130 0x1C02, /* R3 - System Control 1 */
2131 0x0004, /* R4 - System Control 2 */
2132 0x0000, /* R5 - System Hibernate */
2133 0x8A00, /* R6 - Interface Control */
2134 0x0000, /* R7 */
2135 0x8000, /* R8 - Power mgmt (1) */
2136 0x0000, /* R9 - Power mgmt (2) */
2137 0x0000, /* R10 - Power mgmt (3) */
2138 0x2000, /* R11 - Power mgmt (4) */
2139 0x0E00, /* R12 - Power mgmt (5) */
2140 0x0000, /* R13 - Power mgmt (6) */
2141 0x0000, /* R14 - Power mgmt (7) */
2142 0x0000, /* R15 */
2143 0x0000, /* R16 - RTC Seconds/Minutes */
2144 0x0100, /* R17 - RTC Hours/Day */
2145 0x0101, /* R18 - RTC Date/Month */
2146 0x1400, /* R19 - RTC Year */
2147 0x0000, /* R20 - Alarm Seconds/Minutes */
2148 0x0000, /* R21 - Alarm Hours/Day */
2149 0x0000, /* R22 - Alarm Date/Month */
2150 0x0320, /* R23 - RTC Time Control */
2151 0x0000, /* R24 - System Interrupts */
2152 0x0000, /* R25 - Interrupt Status 1 */
2153 0x0000, /* R26 - Interrupt Status 2 */
2154 0x0000, /* R27 */
2155 0x0000, /* R28 - Under Voltage Interrupt status */
2156 0x0000, /* R29 - Over Current Interrupt status */
2157 0x0000, /* R30 - GPIO Interrupt Status */
2158 0x0000, /* R31 - Comparator Interrupt Status */
2159 0x3FFF, /* R32 - System Interrupts Mask */
2160 0x0000, /* R33 - Interrupt Status 1 Mask */
2161 0x0000, /* R34 - Interrupt Status 2 Mask */
2162 0x0000, /* R35 */
2163 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2164 0x0000, /* R37 - Over Current Interrupt status Mask */
2165 0x0000, /* R38 - GPIO Interrupt Status Mask */
2166 0x0000, /* R39 - Comparator Interrupt Status Mask */
2167 0x0040, /* R40 - Clock Control 1 */
2168 0x0000, /* R41 - Clock Control 2 */
2169 0x3A00, /* R42 - FLL Control 1 */
2170 0x7086, /* R43 - FLL Control 2 */
2171 0xC226, /* R44 - FLL Control 3 */
2172 0x0000, /* R45 - FLL Control 4 */
2173 0x0000, /* R46 */
2174 0x0000, /* R47 */
2175 0x0000, /* R48 - DAC Control */
2176 0x0000, /* R49 */
2177 0x00C0, /* R50 - DAC Digital Volume L */
2178 0x00C0, /* R51 - DAC Digital Volume R */
2179 0x0000, /* R52 */
2180 0x0040, /* R53 - DAC LR Rate */
2181 0x0000, /* R54 - DAC Clock Control */
2182 0x0000, /* R55 */
2183 0x0000, /* R56 */
2184 0x0000, /* R57 */
2185 0x4000, /* R58 - DAC Mute */
2186 0x0000, /* R59 - DAC Mute Volume */
2187 0x0000, /* R60 - DAC Side */
2188 0x0000, /* R61 */
2189 0x0000, /* R62 */
2190 0x0000, /* R63 */
2191 0x8000, /* R64 - ADC Control */
2192 0x0000, /* R65 */
2193 0x00C0, /* R66 - ADC Digital Volume L */
2194 0x00C0, /* R67 - ADC Digital Volume R */
2195 0x0000, /* R68 - ADC Divider */
2196 0x0000, /* R69 */
2197 0x0040, /* R70 - ADC LR Rate */
2198 0x0000, /* R71 */
2199 0x0303, /* R72 - Input Control */
2200 0x0000, /* R73 - IN3 Input Control */
2201 0x0000, /* R74 - Mic Bias Control */
2202 0x0000, /* R75 */
2203 0x0000, /* R76 - Output Control */
2204 0x0000, /* R77 - Jack Detect */
2205 0x0000, /* R78 - Anti Pop Control */
2206 0x0000, /* R79 */
2207 0x0040, /* R80 - Left Input Volume */
2208 0x0040, /* R81 - Right Input Volume */
2209 0x0000, /* R82 */
2210 0x0000, /* R83 */
2211 0x0000, /* R84 */
2212 0x0000, /* R85 */
2213 0x0000, /* R86 */
2214 0x0000, /* R87 */
2215 0x0800, /* R88 - Left Mixer Control */
2216 0x1000, /* R89 - Right Mixer Control */
2217 0x0000, /* R90 */
2218 0x0000, /* R91 */
2219 0x0000, /* R92 - OUT3 Mixer Control */
2220 0x0000, /* R93 - OUT4 Mixer Control */
2221 0x0000, /* R94 */
2222 0x0000, /* R95 */
2223 0x0000, /* R96 - Output Left Mixer Volume */
2224 0x0000, /* R97 - Output Right Mixer Volume */
2225 0x0000, /* R98 - Input Mixer Volume L */
2226 0x0000, /* R99 - Input Mixer Volume R */
2227 0x0000, /* R100 - Input Mixer Volume */
2228 0x0000, /* R101 */
2229 0x0000, /* R102 */
2230 0x0000, /* R103 */
2231 0x00E4, /* R104 - OUT1L Volume */
2232 0x00E4, /* R105 - OUT1R Volume */
2233 0x00E4, /* R106 - OUT2L Volume */
2234 0x02E4, /* R107 - OUT2R Volume */
2235 0x0000, /* R108 */
2236 0x0000, /* R109 */
2237 0x0000, /* R110 */
2238 0x0000, /* R111 - BEEP Volume */
2239 0x0A00, /* R112 - AI Formating */
2240 0x0000, /* R113 - ADC DAC COMP */
2241 0x0020, /* R114 - AI ADC Control */
2242 0x0020, /* R115 - AI DAC Control */
2243 0x0000, /* R116 */
2244 0x0000, /* R117 */
2245 0x0000, /* R118 */
2246 0x0000, /* R119 */
2247 0x0000, /* R120 */
2248 0x0000, /* R121 */
2249 0x0000, /* R122 */
2250 0x0000, /* R123 */
2251 0x0000, /* R124 */
2252 0x0000, /* R125 */
2253 0x0000, /* R126 */
2254 0x0000, /* R127 */
2255 0x1FFF, /* R128 - GPIO Debounce */
2256 0x0000, /* R129 - GPIO Pin pull up Control */
2257 0x0000, /* R130 - GPIO Pull down Control */
2258 0x0000, /* R131 - GPIO Interrupt Mode */
2259 0x0000, /* R132 */
2260 0x0000, /* R133 - GPIO Control */
2261 0x0FFC, /* R134 - GPIO Configuration (i/o) */
2262 0x0FFC, /* R135 - GPIO Pin Polarity / Type */
2263 0x0000, /* R136 */
2264 0x0000, /* R137 */
2265 0x0000, /* R138 */
2266 0x0000, /* R139 */
2267 0x0013, /* R140 - GPIO Function Select 1 */
2268 0x0000, /* R141 - GPIO Function Select 2 */
2269 0x0000, /* R142 - GPIO Function Select 3 */
2270 0x0003, /* R143 - GPIO Function Select 4 */
2271 0x0000, /* R144 - Digitiser Control (1) */
2272 0x0002, /* R145 - Digitiser Control (2) */
2273 0x0000, /* R146 */
2274 0x0000, /* R147 */
2275 0x0000, /* R148 */
2276 0x0000, /* R149 */
2277 0x0000, /* R150 */
2278 0x0000, /* R151 */
2279 0x7000, /* R152 - AUX1 Readback */
2280 0x7000, /* R153 - AUX2 Readback */
2281 0x7000, /* R154 - AUX3 Readback */
2282 0x7000, /* R155 - AUX4 Readback */
2283 0x0000, /* R156 - USB Voltage Readback */
2284 0x0000, /* R157 - LINE Voltage Readback */
2285 0x0000, /* R158 - BATT Voltage Readback */
2286 0x0000, /* R159 - Chip Temp Readback */
2287 0x0000, /* R160 */
2288 0x0000, /* R161 */
2289 0x0000, /* R162 */
2290 0x0000, /* R163 - Generic Comparator Control */
2291 0x0000, /* R164 - Generic comparator 1 */
2292 0x0000, /* R165 - Generic comparator 2 */
2293 0x0000, /* R166 - Generic comparator 3 */
2294 0x0000, /* R167 - Generic comparator 4 */
2295 0xA00F, /* R168 - Battery Charger Control 1 */
2296 0x0B06, /* R169 - Battery Charger Control 2 */
2297 0x0000, /* R170 - Battery Charger Control 3 */
2298 0x0000, /* R171 */
2299 0x0000, /* R172 - Current Sink Driver A */
2300 0x0000, /* R173 - CSA Flash control */
2301 0x0000, /* R174 - Current Sink Driver B */
2302 0x0000, /* R175 - CSB Flash control */
2303 0x0000, /* R176 - DCDC/LDO requested */
2304 0x032D, /* R177 - DCDC Active options */
2305 0x0000, /* R178 - DCDC Sleep options */
2306 0x0025, /* R179 - Power-check comparator */
2307 0x000E, /* R180 - DCDC1 Control */
2308 0x0000, /* R181 - DCDC1 Timeouts */
2309 0x1006, /* R182 - DCDC1 Low Power */
2310 0x0018, /* R183 - DCDC2 Control */
2311 0x0000, /* R184 - DCDC2 Timeouts */
2312 0x0000, /* R185 */
2313 0x0000, /* R186 - DCDC3 Control */
2314 0x0000, /* R187 - DCDC3 Timeouts */
2315 0x0006, /* R188 - DCDC3 Low Power */
2316 0x0000, /* R189 - DCDC4 Control */
2317 0x0000, /* R190 - DCDC4 Timeouts */
2318 0x0006, /* R191 - DCDC4 Low Power */
2319 0x0008, /* R192 - DCDC5 Control */
2320 0x0000, /* R193 - DCDC5 Timeouts */
2321 0x0000, /* R194 */
2322 0x0000, /* R195 - DCDC6 Control */
2323 0x0000, /* R196 - DCDC6 Timeouts */
2324 0x0006, /* R197 - DCDC6 Low Power */
2325 0x0000, /* R198 */
2326 0x0003, /* R199 - Limit Switch Control */
2327 0x001C, /* R200 - LDO1 Control */
2328 0x0000, /* R201 - LDO1 Timeouts */
2329 0x001C, /* R202 - LDO1 Low Power */
2330 0x001B, /* R203 - LDO2 Control */
2331 0x0000, /* R204 - LDO2 Timeouts */
2332 0x001C, /* R205 - LDO2 Low Power */
2333 0x001B, /* R206 - LDO3 Control */
2334 0x0000, /* R207 - LDO3 Timeouts */
2335 0x001C, /* R208 - LDO3 Low Power */
2336 0x001B, /* R209 - LDO4 Control */
2337 0x0000, /* R210 - LDO4 Timeouts */
2338 0x001C, /* R211 - LDO4 Low Power */
2339 0x0000, /* R212 */
2340 0x0000, /* R213 */
2341 0x0000, /* R214 */
2342 0x0000, /* R215 - VCC_FAULT Masks */
2343 0x001F, /* R216 - Main Bandgap Control */
2344 0x0000, /* R217 - OSC Control */
2345 0x9000, /* R218 - RTC Tick Control */
2346 0x0000, /* R219 - Security1 */
2347 0x4000, /* R220 */
2348 0x0000, /* R221 */
2349 0x0000, /* R222 */
2350 0x0000, /* R223 */
2351 0x0000, /* R224 - Signal overrides */
2352 0x0000, /* R225 - DCDC/LDO status */
2353 0x0000, /* R226 - Charger Overides/status */
2354 0x0000, /* R227 - misc overrides */
2355 0x0000, /* R228 - Supply overrides/status 1 */
2356 0x0000, /* R229 - Supply overrides/status 2 */
2357 0xE000, /* R230 - GPIO Pin Status */
2358 0x0000, /* R231 - comparotor overrides */
2359 0x0000, /* R232 */
2360 0x0000, /* R233 - State Machine status */
2361 0x1200, /* R234 */
2362 0x0000, /* R235 */
2363 0x8000, /* R236 */
2364 0x0000, /* R237 */
2365 0x0000, /* R238 */
2366 0x0000, /* R239 */
2367 0x0003, /* R240 */
2368 0x0000, /* R241 */
2369 0x0000, /* R242 */
2370 0x0004, /* R243 */
2371 0x0300, /* R244 */
2372 0x0000, /* R245 */
2373 0x0200, /* R246 */
2374 0x0000, /* R247 */
2375 0x1000, /* R248 - DCDC1 Test Controls */
2376 0x5000, /* R249 */
2377 0x1000, /* R250 - DCDC3 Test Controls */
2378 0x1000, /* R251 - DCDC4 Test Controls */
2379 0x5100, /* R252 */
2380 0x1000, /* R253 - DCDC6 Test Controls */
2381};
2382#endif
2383
2384#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
2385
2386#undef WM8350_HAVE_CONFIG_MODE
2387#define WM8350_HAVE_CONFIG_MODE
2388
2389const u16 wm8352_mode1_defaults[] = {
2390 0x6143, /* R0 - Reset/ID */
2391 0x0000, /* R1 - ID */
2392 0x0002, /* R2 - Revision */
2393 0x1C02, /* R3 - System Control 1 */
2394 0x0204, /* R4 - System Control 2 */
2395 0x0000, /* R5 - System Hibernate */
2396 0x8A00, /* R6 - Interface Control */
2397 0x0000, /* R7 */
2398 0x8000, /* R8 - Power mgmt (1) */
2399 0x0000, /* R9 - Power mgmt (2) */
2400 0x0000, /* R10 - Power mgmt (3) */
2401 0x2000, /* R11 - Power mgmt (4) */
2402 0x0E00, /* R12 - Power mgmt (5) */
2403 0x0000, /* R13 - Power mgmt (6) */
2404 0x0000, /* R14 - Power mgmt (7) */
2405 0x0000, /* R15 */
2406 0x0000, /* R16 - RTC Seconds/Minutes */
2407 0x0100, /* R17 - RTC Hours/Day */
2408 0x0101, /* R18 - RTC Date/Month */
2409 0x1400, /* R19 - RTC Year */
2410 0x0000, /* R20 - Alarm Seconds/Minutes */
2411 0x0000, /* R21 - Alarm Hours/Day */
2412 0x0000, /* R22 - Alarm Date/Month */
2413 0x0320, /* R23 - RTC Time Control */
2414 0x0000, /* R24 - System Interrupts */
2415 0x0000, /* R25 - Interrupt Status 1 */
2416 0x0000, /* R26 - Interrupt Status 2 */
2417 0x0000, /* R27 */
2418 0x0000, /* R28 - Under Voltage Interrupt status */
2419 0x0000, /* R29 - Over Current Interrupt status */
2420 0x0000, /* R30 - GPIO Interrupt Status */
2421 0x0000, /* R31 - Comparator Interrupt Status */
2422 0x3FFF, /* R32 - System Interrupts Mask */
2423 0x0000, /* R33 - Interrupt Status 1 Mask */
2424 0x0000, /* R34 - Interrupt Status 2 Mask */
2425 0x0000, /* R35 */
2426 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2427 0x0000, /* R37 - Over Current Interrupt status Mask */
2428 0x0000, /* R38 - GPIO Interrupt Status Mask */
2429 0x0000, /* R39 - Comparator Interrupt Status Mask */
2430 0x0040, /* R40 - Clock Control 1 */
2431 0x0000, /* R41 - Clock Control 2 */
2432 0x3A00, /* R42 - FLL Control 1 */
2433 0x7086, /* R43 - FLL Control 2 */
2434 0xC226, /* R44 - FLL Control 3 */
2435 0x0000, /* R45 - FLL Control 4 */
2436 0x0000, /* R46 */
2437 0x0000, /* R47 */
2438 0x0000, /* R48 - DAC Control */
2439 0x0000, /* R49 */
2440 0x00C0, /* R50 - DAC Digital Volume L */
2441 0x00C0, /* R51 - DAC Digital Volume R */
2442 0x0000, /* R52 */
2443 0x0040, /* R53 - DAC LR Rate */
2444 0x0000, /* R54 - DAC Clock Control */
2445 0x0000, /* R55 */
2446 0x0000, /* R56 */
2447 0x0000, /* R57 */
2448 0x4000, /* R58 - DAC Mute */
2449 0x0000, /* R59 - DAC Mute Volume */
2450 0x0000, /* R60 - DAC Side */
2451 0x0000, /* R61 */
2452 0x0000, /* R62 */
2453 0x0000, /* R63 */
2454 0x8000, /* R64 - ADC Control */
2455 0x0000, /* R65 */
2456 0x00C0, /* R66 - ADC Digital Volume L */
2457 0x00C0, /* R67 - ADC Digital Volume R */
2458 0x0000, /* R68 - ADC Divider */
2459 0x0000, /* R69 */
2460 0x0040, /* R70 - ADC LR Rate */
2461 0x0000, /* R71 */
2462 0x0303, /* R72 - Input Control */
2463 0x0000, /* R73 - IN3 Input Control */
2464 0x0000, /* R74 - Mic Bias Control */
2465 0x0000, /* R75 */
2466 0x0000, /* R76 - Output Control */
2467 0x0000, /* R77 - Jack Detect */
2468 0x0000, /* R78 - Anti Pop Control */
2469 0x0000, /* R79 */
2470 0x0040, /* R80 - Left Input Volume */
2471 0x0040, /* R81 - Right Input Volume */
2472 0x0000, /* R82 */
2473 0x0000, /* R83 */
2474 0x0000, /* R84 */
2475 0x0000, /* R85 */
2476 0x0000, /* R86 */
2477 0x0000, /* R87 */
2478 0x0800, /* R88 - Left Mixer Control */
2479 0x1000, /* R89 - Right Mixer Control */
2480 0x0000, /* R90 */
2481 0x0000, /* R91 */
2482 0x0000, /* R92 - OUT3 Mixer Control */
2483 0x0000, /* R93 - OUT4 Mixer Control */
2484 0x0000, /* R94 */
2485 0x0000, /* R95 */
2486 0x0000, /* R96 - Output Left Mixer Volume */
2487 0x0000, /* R97 - Output Right Mixer Volume */
2488 0x0000, /* R98 - Input Mixer Volume L */
2489 0x0000, /* R99 - Input Mixer Volume R */
2490 0x0000, /* R100 - Input Mixer Volume */
2491 0x0000, /* R101 */
2492 0x0000, /* R102 */
2493 0x0000, /* R103 */
2494 0x00E4, /* R104 - OUT1L Volume */
2495 0x00E4, /* R105 - OUT1R Volume */
2496 0x00E4, /* R106 - OUT2L Volume */
2497 0x02E4, /* R107 - OUT2R Volume */
2498 0x0000, /* R108 */
2499 0x0000, /* R109 */
2500 0x0000, /* R110 */
2501 0x0000, /* R111 - BEEP Volume */
2502 0x0A00, /* R112 - AI Formating */
2503 0x0000, /* R113 - ADC DAC COMP */
2504 0x0020, /* R114 - AI ADC Control */
2505 0x0020, /* R115 - AI DAC Control */
2506 0x0000, /* R116 */
2507 0x0000, /* R117 */
2508 0x0000, /* R118 */
2509 0x0000, /* R119 */
2510 0x0000, /* R120 */
2511 0x0000, /* R121 */
2512 0x0000, /* R122 */
2513 0x0000, /* R123 */
2514 0x0000, /* R124 */
2515 0x0000, /* R125 */
2516 0x0000, /* R126 */
2517 0x0000, /* R127 */
2518 0x1FFF, /* R128 - GPIO Debounce */
2519 0x0000, /* R129 - GPIO Pin pull up Control */
2520 0x0000, /* R130 - GPIO Pull down Control */
2521 0x0000, /* R131 - GPIO Interrupt Mode */
2522 0x0000, /* R132 */
2523 0x0000, /* R133 - GPIO Control */
2524 0x0BFB, /* R134 - GPIO Configuration (i/o) */
2525 0x0FFF, /* R135 - GPIO Pin Polarity / Type */
2526 0x0000, /* R136 */
2527 0x0000, /* R137 */
2528 0x0000, /* R138 */
2529 0x0000, /* R139 */
2530 0x0300, /* R140 - GPIO Function Select 1 */
2531 0x0000, /* R141 - GPIO Function Select 2 */
2532 0x2300, /* R142 - GPIO Function Select 3 */
2533 0x0003, /* R143 - GPIO Function Select 4 */
2534 0x0000, /* R144 - Digitiser Control (1) */
2535 0x0002, /* R145 - Digitiser Control (2) */
2536 0x0000, /* R146 */
2537 0x0000, /* R147 */
2538 0x0000, /* R148 */
2539 0x0000, /* R149 */
2540 0x0000, /* R150 */
2541 0x0000, /* R151 */
2542 0x7000, /* R152 - AUX1 Readback */
2543 0x7000, /* R153 - AUX2 Readback */
2544 0x7000, /* R154 - AUX3 Readback */
2545 0x7000, /* R155 - AUX4 Readback */
2546 0x0000, /* R156 - USB Voltage Readback */
2547 0x0000, /* R157 - LINE Voltage Readback */
2548 0x0000, /* R158 - BATT Voltage Readback */
2549 0x0000, /* R159 - Chip Temp Readback */
2550 0x0000, /* R160 */
2551 0x0000, /* R161 */
2552 0x0000, /* R162 */
2553 0x0000, /* R163 - Generic Comparator Control */
2554 0x0000, /* R164 - Generic comparator 1 */
2555 0x0000, /* R165 - Generic comparator 2 */
2556 0x0000, /* R166 - Generic comparator 3 */
2557 0x0000, /* R167 - Generic comparator 4 */
2558 0xA00F, /* R168 - Battery Charger Control 1 */
2559 0x0B06, /* R169 - Battery Charger Control 2 */
2560 0x0000, /* R170 - Battery Charger Control 3 */
2561 0x0000, /* R171 */
2562 0x0000, /* R172 - Current Sink Driver A */
2563 0x0000, /* R173 - CSA Flash control */
2564 0x0000, /* R174 - Current Sink Driver B */
2565 0x0000, /* R175 - CSB Flash control */
2566 0x0000, /* R176 - DCDC/LDO requested */
2567 0x032D, /* R177 - DCDC Active options */
2568 0x0000, /* R178 - DCDC Sleep options */
2569 0x0025, /* R179 - Power-check comparator */
2570 0x0062, /* R180 - DCDC1 Control */
2571 0x0400, /* R181 - DCDC1 Timeouts */
2572 0x1006, /* R182 - DCDC1 Low Power */
2573 0x0018, /* R183 - DCDC2 Control */
2574 0x0000, /* R184 - DCDC2 Timeouts */
2575 0x0000, /* R185 */
2576 0x0006, /* R186 - DCDC3 Control */
2577 0x0800, /* R187 - DCDC3 Timeouts */
2578 0x0006, /* R188 - DCDC3 Low Power */
2579 0x0006, /* R189 - DCDC4 Control */
2580 0x0C00, /* R190 - DCDC4 Timeouts */
2581 0x0006, /* R191 - DCDC4 Low Power */
2582 0x0008, /* R192 - DCDC5 Control */
2583 0x0000, /* R193 - DCDC5 Timeouts */
2584 0x0000, /* R194 */
2585 0x0026, /* R195 - DCDC6 Control */
2586 0x1000, /* R196 - DCDC6 Timeouts */
2587 0x0006, /* R197 - DCDC6 Low Power */
2588 0x0000, /* R198 */
2589 0x0003, /* R199 - Limit Switch Control */
2590 0x0002, /* R200 - LDO1 Control */
2591 0x0000, /* R201 - LDO1 Timeouts */
2592 0x001C, /* R202 - LDO1 Low Power */
2593 0x001A, /* R203 - LDO2 Control */
2594 0x0000, /* R204 - LDO2 Timeouts */
2595 0x001C, /* R205 - LDO2 Low Power */
2596 0x001F, /* R206 - LDO3 Control */
2597 0x0000, /* R207 - LDO3 Timeouts */
2598 0x001C, /* R208 - LDO3 Low Power */
2599 0x001F, /* R209 - LDO4 Control */
2600 0x0000, /* R210 - LDO4 Timeouts */
2601 0x001C, /* R211 - LDO4 Low Power */
2602 0x0000, /* R212 */
2603 0x0000, /* R213 */
2604 0x0000, /* R214 */
2605 0x0000, /* R215 - VCC_FAULT Masks */
2606 0x001F, /* R216 - Main Bandgap Control */
2607 0x0000, /* R217 - OSC Control */
2608 0x9000, /* R218 - RTC Tick Control */
2609 0x0000, /* R219 - Security1 */
2610 0x4000, /* R220 */
2611 0x0000, /* R221 */
2612 0x0000, /* R222 */
2613 0x0000, /* R223 */
2614 0x0000, /* R224 - Signal overrides */
2615 0x0000, /* R225 - DCDC/LDO status */
2616 0x0000, /* R226 - Charger Overides/status */
2617 0x0000, /* R227 - misc overrides */
2618 0x0000, /* R228 - Supply overrides/status 1 */
2619 0x0000, /* R229 - Supply overrides/status 2 */
2620 0xE000, /* R230 - GPIO Pin Status */
2621 0x0000, /* R231 - comparotor overrides */
2622 0x0000, /* R232 */
2623 0x0000, /* R233 - State Machine status */
2624 0x1200, /* R234 */
2625 0x0000, /* R235 */
2626 0x8000, /* R236 */
2627 0x0000, /* R237 */
2628 0x0000, /* R238 */
2629 0x0000, /* R239 */
2630 0x0003, /* R240 */
2631 0x0000, /* R241 */
2632 0x0000, /* R242 */
2633 0x0004, /* R243 */
2634 0x0300, /* R244 */
2635 0x0000, /* R245 */
2636 0x0200, /* R246 */
2637 0x0000, /* R247 */
2638 0x1000, /* R248 - DCDC1 Test Controls */
2639 0x5000, /* R249 */
2640 0x1000, /* R250 - DCDC3 Test Controls */
2641 0x1000, /* R251 - DCDC4 Test Controls */
2642 0x5100, /* R252 */
2643 0x1000, /* R253 - DCDC6 Test Controls */
2644};
2645#endif
2646
2647#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
2648
2649#undef WM8350_HAVE_CONFIG_MODE
2650#define WM8350_HAVE_CONFIG_MODE
2651
2652const u16 wm8352_mode2_defaults[] = {
2653 0x6143, /* R0 - Reset/ID */
2654 0x0000, /* R1 - ID */
2655 0x0002, /* R2 - Revision */
2656 0x1C02, /* R3 - System Control 1 */
2657 0x0204, /* R4 - System Control 2 */
2658 0x0000, /* R5 - System Hibernate */
2659 0x8A00, /* R6 - Interface Control */
2660 0x0000, /* R7 */
2661 0x8000, /* R8 - Power mgmt (1) */
2662 0x0000, /* R9 - Power mgmt (2) */
2663 0x0000, /* R10 - Power mgmt (3) */
2664 0x2000, /* R11 - Power mgmt (4) */
2665 0x0E00, /* R12 - Power mgmt (5) */
2666 0x0000, /* R13 - Power mgmt (6) */
2667 0x0000, /* R14 - Power mgmt (7) */
2668 0x0000, /* R15 */
2669 0x0000, /* R16 - RTC Seconds/Minutes */
2670 0x0100, /* R17 - RTC Hours/Day */
2671 0x0101, /* R18 - RTC Date/Month */
2672 0x1400, /* R19 - RTC Year */
2673 0x0000, /* R20 - Alarm Seconds/Minutes */
2674 0x0000, /* R21 - Alarm Hours/Day */
2675 0x0000, /* R22 - Alarm Date/Month */
2676 0x0320, /* R23 - RTC Time Control */
2677 0x0000, /* R24 - System Interrupts */
2678 0x0000, /* R25 - Interrupt Status 1 */
2679 0x0000, /* R26 - Interrupt Status 2 */
2680 0x0000, /* R27 */
2681 0x0000, /* R28 - Under Voltage Interrupt status */
2682 0x0000, /* R29 - Over Current Interrupt status */
2683 0x0000, /* R30 - GPIO Interrupt Status */
2684 0x0000, /* R31 - Comparator Interrupt Status */
2685 0x3FFF, /* R32 - System Interrupts Mask */
2686 0x0000, /* R33 - Interrupt Status 1 Mask */
2687 0x0000, /* R34 - Interrupt Status 2 Mask */
2688 0x0000, /* R35 */
2689 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2690 0x0000, /* R37 - Over Current Interrupt status Mask */
2691 0x0000, /* R38 - GPIO Interrupt Status Mask */
2692 0x0000, /* R39 - Comparator Interrupt Status Mask */
2693 0x0040, /* R40 - Clock Control 1 */
2694 0x0000, /* R41 - Clock Control 2 */
2695 0x3A00, /* R42 - FLL Control 1 */
2696 0x7086, /* R43 - FLL Control 2 */
2697 0xC226, /* R44 - FLL Control 3 */
2698 0x0000, /* R45 - FLL Control 4 */
2699 0x0000, /* R46 */
2700 0x0000, /* R47 */
2701 0x0000, /* R48 - DAC Control */
2702 0x0000, /* R49 */
2703 0x00C0, /* R50 - DAC Digital Volume L */
2704 0x00C0, /* R51 - DAC Digital Volume R */
2705 0x0000, /* R52 */
2706 0x0040, /* R53 - DAC LR Rate */
2707 0x0000, /* R54 - DAC Clock Control */
2708 0x0000, /* R55 */
2709 0x0000, /* R56 */
2710 0x0000, /* R57 */
2711 0x4000, /* R58 - DAC Mute */
2712 0x0000, /* R59 - DAC Mute Volume */
2713 0x0000, /* R60 - DAC Side */
2714 0x0000, /* R61 */
2715 0x0000, /* R62 */
2716 0x0000, /* R63 */
2717 0x8000, /* R64 - ADC Control */
2718 0x0000, /* R65 */
2719 0x00C0, /* R66 - ADC Digital Volume L */
2720 0x00C0, /* R67 - ADC Digital Volume R */
2721 0x0000, /* R68 - ADC Divider */
2722 0x0000, /* R69 */
2723 0x0040, /* R70 - ADC LR Rate */
2724 0x0000, /* R71 */
2725 0x0303, /* R72 - Input Control */
2726 0x0000, /* R73 - IN3 Input Control */
2727 0x0000, /* R74 - Mic Bias Control */
2728 0x0000, /* R75 */
2729 0x0000, /* R76 - Output Control */
2730 0x0000, /* R77 - Jack Detect */
2731 0x0000, /* R78 - Anti Pop Control */
2732 0x0000, /* R79 */
2733 0x0040, /* R80 - Left Input Volume */
2734 0x0040, /* R81 - Right Input Volume */
2735 0x0000, /* R82 */
2736 0x0000, /* R83 */
2737 0x0000, /* R84 */
2738 0x0000, /* R85 */
2739 0x0000, /* R86 */
2740 0x0000, /* R87 */
2741 0x0800, /* R88 - Left Mixer Control */
2742 0x1000, /* R89 - Right Mixer Control */
2743 0x0000, /* R90 */
2744 0x0000, /* R91 */
2745 0x0000, /* R92 - OUT3 Mixer Control */
2746 0x0000, /* R93 - OUT4 Mixer Control */
2747 0x0000, /* R94 */
2748 0x0000, /* R95 */
2749 0x0000, /* R96 - Output Left Mixer Volume */
2750 0x0000, /* R97 - Output Right Mixer Volume */
2751 0x0000, /* R98 - Input Mixer Volume L */
2752 0x0000, /* R99 - Input Mixer Volume R */
2753 0x0000, /* R100 - Input Mixer Volume */
2754 0x0000, /* R101 */
2755 0x0000, /* R102 */
2756 0x0000, /* R103 */
2757 0x00E4, /* R104 - OUT1L Volume */
2758 0x00E4, /* R105 - OUT1R Volume */
2759 0x00E4, /* R106 - OUT2L Volume */
2760 0x02E4, /* R107 - OUT2R Volume */
2761 0x0000, /* R108 */
2762 0x0000, /* R109 */
2763 0x0000, /* R110 */
2764 0x0000, /* R111 - BEEP Volume */
2765 0x0A00, /* R112 - AI Formating */
2766 0x0000, /* R113 - ADC DAC COMP */
2767 0x0020, /* R114 - AI ADC Control */
2768 0x0020, /* R115 - AI DAC Control */
2769 0x0000, /* R116 */
2770 0x0000, /* R117 */
2771 0x0000, /* R118 */
2772 0x0000, /* R119 */
2773 0x0000, /* R120 */
2774 0x0000, /* R121 */
2775 0x0000, /* R122 */
2776 0x0000, /* R123 */
2777 0x0000, /* R124 */
2778 0x0000, /* R125 */
2779 0x0000, /* R126 */
2780 0x0000, /* R127 */
2781 0x1FFF, /* R128 - GPIO Debounce */
2782 0x0000, /* R129 - GPIO Pin pull up Control */
2783 0x0110, /* R130 - GPIO Pull down Control */
2784 0x0000, /* R131 - GPIO Interrupt Mode */
2785 0x0000, /* R132 */
2786 0x0000, /* R133 - GPIO Control */
2787 0x09DA, /* R134 - GPIO Configuration (i/o) */
2788 0x0DD6, /* R135 - GPIO Pin Polarity / Type */
2789 0x0000, /* R136 */
2790 0x0000, /* R137 */
2791 0x0000, /* R138 */
2792 0x0000, /* R139 */
2793 0x1310, /* R140 - GPIO Function Select 1 */
2794 0x0033, /* R141 - GPIO Function Select 2 */
2795 0x2000, /* R142 - GPIO Function Select 3 */
2796 0x0000, /* R143 - GPIO Function Select 4 */
2797 0x0000, /* R144 - Digitiser Control (1) */
2798 0x0002, /* R145 - Digitiser Control (2) */
2799 0x0000, /* R146 */
2800 0x0000, /* R147 */
2801 0x0000, /* R148 */
2802 0x0000, /* R149 */
2803 0x0000, /* R150 */
2804 0x0000, /* R151 */
2805 0x7000, /* R152 - AUX1 Readback */
2806 0x7000, /* R153 - AUX2 Readback */
2807 0x7000, /* R154 - AUX3 Readback */
2808 0x7000, /* R155 - AUX4 Readback */
2809 0x0000, /* R156 - USB Voltage Readback */
2810 0x0000, /* R157 - LINE Voltage Readback */
2811 0x0000, /* R158 - BATT Voltage Readback */
2812 0x0000, /* R159 - Chip Temp Readback */
2813 0x0000, /* R160 */
2814 0x0000, /* R161 */
2815 0x0000, /* R162 */
2816 0x0000, /* R163 - Generic Comparator Control */
2817 0x0000, /* R164 - Generic comparator 1 */
2818 0x0000, /* R165 - Generic comparator 2 */
2819 0x0000, /* R166 - Generic comparator 3 */
2820 0x0000, /* R167 - Generic comparator 4 */
2821 0xA00F, /* R168 - Battery Charger Control 1 */
2822 0x0B06, /* R169 - Battery Charger Control 2 */
2823 0x0000, /* R170 - Battery Charger Control 3 */
2824 0x0000, /* R171 */
2825 0x0000, /* R172 - Current Sink Driver A */
2826 0x0000, /* R173 - CSA Flash control */
2827 0x0000, /* R174 - Current Sink Driver B */
2828 0x0000, /* R175 - CSB Flash control */
2829 0x0000, /* R176 - DCDC/LDO requested */
2830 0x032D, /* R177 - DCDC Active options */
2831 0x0000, /* R178 - DCDC Sleep options */
2832 0x0025, /* R179 - Power-check comparator */
2833 0x000E, /* R180 - DCDC1 Control */
2834 0x0800, /* R181 - DCDC1 Timeouts */
2835 0x1006, /* R182 - DCDC1 Low Power */
2836 0x0018, /* R183 - DCDC2 Control */
2837 0x0000, /* R184 - DCDC2 Timeouts */
2838 0x0000, /* R185 */
2839 0x0056, /* R186 - DCDC3 Control */
2840 0x1800, /* R187 - DCDC3 Timeouts */
2841 0x0006, /* R188 - DCDC3 Low Power */
2842 0x000E, /* R189 - DCDC4 Control */
2843 0x1000, /* R190 - DCDC4 Timeouts */
2844 0x0006, /* R191 - DCDC4 Low Power */
2845 0x0008, /* R192 - DCDC5 Control */
2846 0x0000, /* R193 - DCDC5 Timeouts */
2847 0x0000, /* R194 */
2848 0x0026, /* R195 - DCDC6 Control */
2849 0x0C00, /* R196 - DCDC6 Timeouts */
2850 0x0006, /* R197 - DCDC6 Low Power */
2851 0x0000, /* R198 */
2852 0x0003, /* R199 - Limit Switch Control */
2853 0x001C, /* R200 - LDO1 Control */
2854 0x0000, /* R201 - LDO1 Timeouts */
2855 0x001C, /* R202 - LDO1 Low Power */
2856 0x0006, /* R203 - LDO2 Control */
2857 0x0400, /* R204 - LDO2 Timeouts */
2858 0x001C, /* R205 - LDO2 Low Power */
2859 0x001C, /* R206 - LDO3 Control */
2860 0x1400, /* R207 - LDO3 Timeouts */
2861 0x001C, /* R208 - LDO3 Low Power */
2862 0x001A, /* R209 - LDO4 Control */
2863 0x0000, /* R210 - LDO4 Timeouts */
2864 0x001C, /* R211 - LDO4 Low Power */
2865 0x0000, /* R212 */
2866 0x0000, /* R213 */
2867 0x0000, /* R214 */
2868 0x0000, /* R215 - VCC_FAULT Masks */
2869 0x001F, /* R216 - Main Bandgap Control */
2870 0x0000, /* R217 - OSC Control */
2871 0x9000, /* R218 - RTC Tick Control */
2872 0x0000, /* R219 - Security1 */
2873 0x4000, /* R220 */
2874 0x0000, /* R221 */
2875 0x0000, /* R222 */
2876 0x0000, /* R223 */
2877 0x0000, /* R224 - Signal overrides */
2878 0x0000, /* R225 - DCDC/LDO status */
2879 0x0000, /* R226 - Charger Overides/status */
2880 0x0000, /* R227 - misc overrides */
2881 0x0000, /* R228 - Supply overrides/status 1 */
2882 0x0000, /* R229 - Supply overrides/status 2 */
2883 0xE000, /* R230 - GPIO Pin Status */
2884 0x0000, /* R231 - comparotor overrides */
2885 0x0000, /* R232 */
2886 0x0000, /* R233 - State Machine status */
2887 0x1200, /* R234 */
2888 0x0000, /* R235 */
2889 0x8000, /* R236 */
2890 0x0000, /* R237 */
2891 0x0000, /* R238 */
2892 0x0000, /* R239 */
2893 0x0003, /* R240 */
2894 0x0000, /* R241 */
2895 0x0000, /* R242 */
2896 0x0004, /* R243 */
2897 0x0300, /* R244 */
2898 0x0000, /* R245 */
2899 0x0200, /* R246 */
2900 0x0000, /* R247 */
2901 0x1000, /* R248 - DCDC1 Test Controls */
2902 0x5000, /* R249 */
2903 0x1000, /* R250 - DCDC3 Test Controls */
2904 0x1000, /* R251 - DCDC4 Test Controls */
2905 0x5100, /* R252 */
2906 0x1000, /* R253 - DCDC6 Test Controls */
2907};
2908#endif
2909
2910#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
2911
2912#undef WM8350_HAVE_CONFIG_MODE
2913#define WM8350_HAVE_CONFIG_MODE
2914
2915const u16 wm8352_mode3_defaults[] = {
2916 0x6143, /* R0 - Reset/ID */
2917 0x0000, /* R1 - ID */
2918 0x0002, /* R2 - Revision */
2919 0x1C02, /* R3 - System Control 1 */
2920 0x0204, /* R4 - System Control 2 */
2921 0x0000, /* R5 - System Hibernate */
2922 0x8A00, /* R6 - Interface Control */
2923 0x0000, /* R7 */
2924 0x8000, /* R8 - Power mgmt (1) */
2925 0x0000, /* R9 - Power mgmt (2) */
2926 0x0000, /* R10 - Power mgmt (3) */
2927 0x2000, /* R11 - Power mgmt (4) */
2928 0x0E00, /* R12 - Power mgmt (5) */
2929 0x0000, /* R13 - Power mgmt (6) */
2930 0x0000, /* R14 - Power mgmt (7) */
2931 0x0000, /* R15 */
2932 0x0000, /* R16 - RTC Seconds/Minutes */
2933 0x0100, /* R17 - RTC Hours/Day */
2934 0x0101, /* R18 - RTC Date/Month */
2935 0x1400, /* R19 - RTC Year */
2936 0x0000, /* R20 - Alarm Seconds/Minutes */
2937 0x0000, /* R21 - Alarm Hours/Day */
2938 0x0000, /* R22 - Alarm Date/Month */
2939 0x0320, /* R23 - RTC Time Control */
2940 0x0000, /* R24 - System Interrupts */
2941 0x0000, /* R25 - Interrupt Status 1 */
2942 0x0000, /* R26 - Interrupt Status 2 */
2943 0x0000, /* R27 */
2944 0x0000, /* R28 - Under Voltage Interrupt status */
2945 0x0000, /* R29 - Over Current Interrupt status */
2946 0x0000, /* R30 - GPIO Interrupt Status */
2947 0x0000, /* R31 - Comparator Interrupt Status */
2948 0x3FFF, /* R32 - System Interrupts Mask */
2949 0x0000, /* R33 - Interrupt Status 1 Mask */
2950 0x0000, /* R34 - Interrupt Status 2 Mask */
2951 0x0000, /* R35 */
2952 0x0000, /* R36 - Under Voltage Interrupt status Mask */
2953 0x0000, /* R37 - Over Current Interrupt status Mask */
2954 0x0000, /* R38 - GPIO Interrupt Status Mask */
2955 0x0000, /* R39 - Comparator Interrupt Status Mask */
2956 0x0040, /* R40 - Clock Control 1 */
2957 0x0000, /* R41 - Clock Control 2 */
2958 0x3A00, /* R42 - FLL Control 1 */
2959 0x7086, /* R43 - FLL Control 2 */
2960 0xC226, /* R44 - FLL Control 3 */
2961 0x0000, /* R45 - FLL Control 4 */
2962 0x0000, /* R46 */
2963 0x0000, /* R47 */
2964 0x0000, /* R48 - DAC Control */
2965 0x0000, /* R49 */
2966 0x00C0, /* R50 - DAC Digital Volume L */
2967 0x00C0, /* R51 - DAC Digital Volume R */
2968 0x0000, /* R52 */
2969 0x0040, /* R53 - DAC LR Rate */
2970 0x0000, /* R54 - DAC Clock Control */
2971 0x0000, /* R55 */
2972 0x0000, /* R56 */
2973 0x0000, /* R57 */
2974 0x4000, /* R58 - DAC Mute */
2975 0x0000, /* R59 - DAC Mute Volume */
2976 0x0000, /* R60 - DAC Side */
2977 0x0000, /* R61 */
2978 0x0000, /* R62 */
2979 0x0000, /* R63 */
2980 0x8000, /* R64 - ADC Control */
2981 0x0000, /* R65 */
2982 0x00C0, /* R66 - ADC Digital Volume L */
2983 0x00C0, /* R67 - ADC Digital Volume R */
2984 0x0000, /* R68 - ADC Divider */
2985 0x0000, /* R69 */
2986 0x0040, /* R70 - ADC LR Rate */
2987 0x0000, /* R71 */
2988 0x0303, /* R72 - Input Control */
2989 0x0000, /* R73 - IN3 Input Control */
2990 0x0000, /* R74 - Mic Bias Control */
2991 0x0000, /* R75 */
2992 0x0000, /* R76 - Output Control */
2993 0x0000, /* R77 - Jack Detect */
2994 0x0000, /* R78 - Anti Pop Control */
2995 0x0000, /* R79 */
2996 0x0040, /* R80 - Left Input Volume */
2997 0x0040, /* R81 - Right Input Volume */
2998 0x0000, /* R82 */
2999 0x0000, /* R83 */
3000 0x0000, /* R84 */
3001 0x0000, /* R85 */
3002 0x0000, /* R86 */
3003 0x0000, /* R87 */
3004 0x0800, /* R88 - Left Mixer Control */
3005 0x1000, /* R89 - Right Mixer Control */
3006 0x0000, /* R90 */
3007 0x0000, /* R91 */
3008 0x0000, /* R92 - OUT3 Mixer Control */
3009 0x0000, /* R93 - OUT4 Mixer Control */
3010 0x0000, /* R94 */
3011 0x0000, /* R95 */
3012 0x0000, /* R96 - Output Left Mixer Volume */
3013 0x0000, /* R97 - Output Right Mixer Volume */
3014 0x0000, /* R98 - Input Mixer Volume L */
3015 0x0000, /* R99 - Input Mixer Volume R */
3016 0x0000, /* R100 - Input Mixer Volume */
3017 0x0000, /* R101 */
3018 0x0000, /* R102 */
3019 0x0000, /* R103 */
3020 0x00E4, /* R104 - OUT1L Volume */
3021 0x00E4, /* R105 - OUT1R Volume */
3022 0x00E4, /* R106 - OUT2L Volume */
3023 0x02E4, /* R107 - OUT2R Volume */
3024 0x0000, /* R108 */
3025 0x0000, /* R109 */
3026 0x0000, /* R110 */
3027 0x0000, /* R111 - BEEP Volume */
3028 0x0A00, /* R112 - AI Formating */
3029 0x0000, /* R113 - ADC DAC COMP */
3030 0x0020, /* R114 - AI ADC Control */
3031 0x0020, /* R115 - AI DAC Control */
3032 0x0000, /* R116 */
3033 0x0000, /* R117 */
3034 0x0000, /* R118 */
3035 0x0000, /* R119 */
3036 0x0000, /* R120 */
3037 0x0000, /* R121 */
3038 0x0000, /* R122 */
3039 0x0000, /* R123 */
3040 0x0000, /* R124 */
3041 0x0000, /* R125 */
3042 0x0000, /* R126 */
3043 0x0000, /* R127 */
3044 0x1FFF, /* R128 - GPIO Debounce */
3045 0x0010, /* R129 - GPIO Pin pull up Control */
3046 0x0000, /* R130 - GPIO Pull down Control */
3047 0x0000, /* R131 - GPIO Interrupt Mode */
3048 0x0000, /* R132 */
3049 0x0000, /* R133 - GPIO Control */
3050 0x0BFB, /* R134 - GPIO Configuration (i/o) */
3051 0x0FFD, /* R135 - GPIO Pin Polarity / Type */
3052 0x0000, /* R136 */
3053 0x0000, /* R137 */
3054 0x0000, /* R138 */
3055 0x0000, /* R139 */
3056 0x0310, /* R140 - GPIO Function Select 1 */
3057 0x0001, /* R141 - GPIO Function Select 2 */
3058 0x2300, /* R142 - GPIO Function Select 3 */
3059 0x0003, /* R143 - GPIO Function Select 4 */
3060 0x0000, /* R144 - Digitiser Control (1) */
3061 0x0002, /* R145 - Digitiser Control (2) */
3062 0x0000, /* R146 */
3063 0x0000, /* R147 */
3064 0x0000, /* R148 */
3065 0x0000, /* R149 */
3066 0x0000, /* R150 */
3067 0x0000, /* R151 */
3068 0x7000, /* R152 - AUX1 Readback */
3069 0x7000, /* R153 - AUX2 Readback */
3070 0x7000, /* R154 - AUX3 Readback */
3071 0x7000, /* R155 - AUX4 Readback */
3072 0x0000, /* R156 - USB Voltage Readback */
3073 0x0000, /* R157 - LINE Voltage Readback */
3074 0x0000, /* R158 - BATT Voltage Readback */
3075 0x0000, /* R159 - Chip Temp Readback */
3076 0x0000, /* R160 */
3077 0x0000, /* R161 */
3078 0x0000, /* R162 */
3079 0x0000, /* R163 - Generic Comparator Control */
3080 0x0000, /* R164 - Generic comparator 1 */
3081 0x0000, /* R165 - Generic comparator 2 */
3082 0x0000, /* R166 - Generic comparator 3 */
3083 0x0000, /* R167 - Generic comparator 4 */
3084 0xA00F, /* R168 - Battery Charger Control 1 */
3085 0x0B06, /* R169 - Battery Charger Control 2 */
3086 0x0000, /* R170 - Battery Charger Control 3 */
3087 0x0000, /* R171 */
3088 0x0000, /* R172 - Current Sink Driver A */
3089 0x0000, /* R173 - CSA Flash control */
3090 0x0000, /* R174 - Current Sink Driver B */
3091 0x0000, /* R175 - CSB Flash control */
3092 0x0000, /* R176 - DCDC/LDO requested */
3093 0x032D, /* R177 - DCDC Active options */
3094 0x0000, /* R178 - DCDC Sleep options */
3095 0x0025, /* R179 - Power-check comparator */
3096 0x0006, /* R180 - DCDC1 Control */
3097 0x0400, /* R181 - DCDC1 Timeouts */
3098 0x1006, /* R182 - DCDC1 Low Power */
3099 0x0018, /* R183 - DCDC2 Control */
3100 0x0000, /* R184 - DCDC2 Timeouts */
3101 0x0000, /* R185 */
3102 0x0050, /* R186 - DCDC3 Control */
3103 0x0C00, /* R187 - DCDC3 Timeouts */
3104 0x0006, /* R188 - DCDC3 Low Power */
3105 0x000E, /* R189 - DCDC4 Control */
3106 0x0400, /* R190 - DCDC4 Timeouts */
3107 0x0006, /* R191 - DCDC4 Low Power */
3108 0x0008, /* R192 - DCDC5 Control */
3109 0x0000, /* R193 - DCDC5 Timeouts */
3110 0x0000, /* R194 */
3111 0x0029, /* R195 - DCDC6 Control */
3112 0x0800, /* R196 - DCDC6 Timeouts */
3113 0x0006, /* R197 - DCDC6 Low Power */
3114 0x0000, /* R198 */
3115 0x0003, /* R199 - Limit Switch Control */
3116 0x001D, /* R200 - LDO1 Control */
3117 0x1000, /* R201 - LDO1 Timeouts */
3118 0x001C, /* R202 - LDO1 Low Power */
3119 0x0017, /* R203 - LDO2 Control */
3120 0x1000, /* R204 - LDO2 Timeouts */
3121 0x001C, /* R205 - LDO2 Low Power */
3122 0x0006, /* R206 - LDO3 Control */
3123 0x1000, /* R207 - LDO3 Timeouts */
3124 0x001C, /* R208 - LDO3 Low Power */
3125 0x0010, /* R209 - LDO4 Control */
3126 0x1000, /* R210 - LDO4 Timeouts */
3127 0x001C, /* R211 - LDO4 Low Power */
3128 0x0000, /* R212 */
3129 0x0000, /* R213 */
3130 0x0000, /* R214 */
3131 0x0000, /* R215 - VCC_FAULT Masks */
3132 0x001F, /* R216 - Main Bandgap Control */
3133 0x0000, /* R217 - OSC Control */
3134 0x9000, /* R218 - RTC Tick Control */
3135 0x0000, /* R219 - Security1 */
3136 0x4000, /* R220 */
3137 0x0000, /* R221 */
3138 0x0000, /* R222 */
3139 0x0000, /* R223 */
3140 0x0000, /* R224 - Signal overrides */
3141 0x0000, /* R225 - DCDC/LDO status */
3142 0x0000, /* R226 - Charger Overides/status */
3143 0x0000, /* R227 - misc overrides */
3144 0x0000, /* R228 - Supply overrides/status 1 */
3145 0x0000, /* R229 - Supply overrides/status 2 */
3146 0xE000, /* R230 - GPIO Pin Status */
3147 0x0000, /* R231 - comparotor overrides */
3148 0x0000, /* R232 */
3149 0x0000, /* R233 - State Machine status */
3150 0x1200, /* R234 */
3151 0x0000, /* R235 */
3152 0x8000, /* R236 */
3153 0x0000, /* R237 */
3154 0x0000, /* R238 */
3155 0x0000, /* R239 */
3156 0x0003, /* R240 */
3157 0x0000, /* R241 */
3158 0x0000, /* R242 */
3159 0x0004, /* R243 */
3160 0x0300, /* R244 */
3161 0x0000, /* R245 */
3162 0x0200, /* R246 */
3163 0x0000, /* R247 */
3164 0x1000, /* R248 - DCDC1 Test Controls */
3165 0x5000, /* R249 */
3166 0x1000, /* R250 - DCDC3 Test Controls */
3167 0x1000, /* R251 - DCDC4 Test Controls */
3168 0x5100, /* R252 */
3169 0x1000, /* R253 - DCDC6 Test Controls */
3170};
3171#endif
3172
1077/* The register defaults for the config mode used must be compiled in but 3173/* The register defaults for the config mode used must be compiled in but
1078 * due to the impact on kernel size it is possible to disable 3174 * due to the impact on kernel size it is possible to disable
1079 */ 3175 */
@@ -1307,14 +3403,14 @@ const struct wm8350_reg_access wm8350_reg_io_map[] = {
1307 { 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */ 3403 { 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */
1308 { 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */ 3404 { 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */
1309 { 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */ 3405 { 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */
1310 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R219 */ 3406 { 0xFFFF, 0xFFFF, 0x0000 }, /* R219 - Security */
1311 { 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */ 3407 { 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */
1312 { 0x0000, 0x0000, 0x0000 }, /* R221 */ 3408 { 0x0000, 0x0000, 0x0000 }, /* R221 */
1313 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */ 3409 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */
1314 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */ 3410 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */
1315 { 0x0000, 0x0000, 0x0000 }, /* R224 */ 3411 { 0x0000, 0x0000, 0x0000 }, /* R224 */
1316 { 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */ 3412 { 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
1317 { 0x0000, 0x0000, 0x0000 }, /* R226 */ 3413 { 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
1318 { 0x0000, 0x0000, 0xFFFF }, /* R227 */ 3414 { 0x0000, 0x0000, 0xFFFF }, /* R227 */
1319 { 0x0000, 0x0000, 0x0000 }, /* R228 */ 3415 { 0x0000, 0x0000, 0x0000 }, /* R228 */
1320 { 0x0000, 0x0000, 0x0000 }, /* R229 */ 3416 { 0x0000, 0x0000, 0x0000 }, /* R229 */
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
index 6a0cedb5bb8a..cf30d06a0104 100644
--- a/drivers/mfd/wm8400-core.c
+++ b/drivers/mfd/wm8400-core.c
@@ -15,6 +15,7 @@
15#include <linux/bug.h> 15#include <linux/bug.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/mfd/core.h>
18#include <linux/mfd/wm8400-private.h> 19#include <linux/mfd/wm8400-private.h>
19#include <linux/mfd/wm8400-audio.h> 20#include <linux/mfd/wm8400-audio.h>
20 21
@@ -239,6 +240,16 @@ void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
239} 240}
240EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache); 241EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
241 242
243static int wm8400_register_codec(struct wm8400 *wm8400)
244{
245 struct mfd_cell cell = {
246 .name = "wm8400-codec",
247 .driver_data = wm8400,
248 };
249
250 return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0);
251}
252
242/* 253/*
243 * wm8400_init - Generic initialisation 254 * wm8400_init - Generic initialisation
244 * 255 *
@@ -296,24 +307,32 @@ static int wm8400_init(struct wm8400 *wm8400,
296 reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT; 307 reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
297 dev_info(wm8400->dev, "WM8400 revision %x\n", reg); 308 dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
298 309
310 ret = wm8400_register_codec(wm8400);
311 if (ret != 0) {
312 dev_err(wm8400->dev, "Failed to register codec\n");
313 goto err_children;
314 }
315
299 if (pdata && pdata->platform_init) { 316 if (pdata && pdata->platform_init) {
300 ret = pdata->platform_init(wm8400->dev); 317 ret = pdata->platform_init(wm8400->dev);
301 if (ret != 0) 318 if (ret != 0) {
302 dev_err(wm8400->dev, "Platform init failed: %d\n", 319 dev_err(wm8400->dev, "Platform init failed: %d\n",
303 ret); 320 ret);
321 goto err_children;
322 }
304 } else 323 } else
305 dev_warn(wm8400->dev, "No platform initialisation supplied\n"); 324 dev_warn(wm8400->dev, "No platform initialisation supplied\n");
306 325
326 return 0;
327
328err_children:
329 mfd_remove_devices(wm8400->dev);
307 return ret; 330 return ret;
308} 331}
309 332
310static void wm8400_release(struct wm8400 *wm8400) 333static void wm8400_release(struct wm8400 *wm8400)
311{ 334{
312 int i; 335 mfd_remove_devices(wm8400->dev);
313
314 for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
315 if (wm8400->regulators[i].name)
316 platform_device_unregister(&wm8400->regulators[i]);
317} 336}
318 337
319#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 338#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 20:24:00 -0500