diff options
Diffstat (limited to 'drivers/mfd/wm8994-regmap.c')
-rw-r--r-- | drivers/mfd/wm8994-regmap.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/drivers/mfd/wm8994-regmap.c b/drivers/mfd/wm8994-regmap.c index 7605b6095453..bfd25af6ecb1 100644 --- a/drivers/mfd/wm8994-regmap.c +++ b/drivers/mfd/wm8994-regmap.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include "wm8994.h" | 20 | #include "wm8994.h" |
21 | 21 | ||
22 | static struct reg_default wm1811_defaults[] = { | 22 | static struct reg_default wm1811_defaults[] = { |
23 | { 0x0000, 0x1811 }, /* R0 - Software Reset */ | ||
24 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | 23 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
25 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | 24 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
26 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | 25 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
@@ -61,7 +60,7 @@ static struct reg_default wm1811_defaults[] = { | |||
61 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ | 60 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ |
62 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ | 61 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ |
63 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ | 62 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ |
64 | { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */ | 63 | { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */ |
65 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ | 64 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ |
66 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ | 65 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ |
67 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ | 66 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ |
@@ -69,16 +68,12 @@ static struct reg_default wm1811_defaults[] = { | |||
69 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ | 68 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ |
70 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ | 69 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ |
71 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ | 70 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ |
72 | { 0x0054, 0x0000 }, /* R84 - DC Servo (1) */ | ||
73 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ | 71 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ |
74 | { 0x0058, 0x0000 }, /* R88 - DC Servo Readback */ | ||
75 | { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */ | 72 | { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */ |
76 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ | 73 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ |
77 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ | 74 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ |
78 | { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */ | 75 | { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */ |
79 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ | 76 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ |
80 | { 0x00D2, 0x0000 }, /* R210 - Mic Detect 3 */ | ||
81 | { 0x0100, 0x0100 }, /* R256 - Chip Revision */ | ||
82 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ | 77 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ |
83 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ | 78 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ |
84 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ | 79 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ |
@@ -88,7 +83,6 @@ static struct reg_default wm1811_defaults[] = { | |||
88 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ | 83 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ |
89 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ | 84 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ |
90 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ | 85 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ |
91 | { 0x0212, 0x0000 }, /* R530 - Rate Status */ | ||
92 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ | 86 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ |
93 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ | 87 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ |
94 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ | 88 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ |
@@ -218,8 +212,6 @@ static struct reg_default wm1811_defaults[] = { | |||
218 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ | 212 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ |
219 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ | 213 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ |
220 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ | 214 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ |
221 | { 0x0730, 0x0000 }, /* R1840 - Interrupt Status 1 */ | ||
222 | { 0x0731, 0x0000 }, /* R1841 - Interrupt Status 2 */ | ||
223 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ | 215 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ |
224 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ | 216 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ |
225 | { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */ | 217 | { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */ |
@@ -228,7 +220,6 @@ static struct reg_default wm1811_defaults[] = { | |||
228 | }; | 220 | }; |
229 | 221 | ||
230 | static struct reg_default wm8994_defaults[] = { | 222 | static struct reg_default wm8994_defaults[] = { |
231 | { 0x0000, 0x8994 }, /* R0 - Software Reset */ | ||
232 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | 223 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
233 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | 224 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
234 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | 225 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
@@ -275,12 +266,9 @@ static struct reg_default wm8994_defaults[] = { | |||
275 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ | 266 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ |
276 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ | 267 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ |
277 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ | 268 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ |
278 | { 0x0054, 0x0000 }, /* R84 - DC Servo (1) */ | ||
279 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ | 269 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ |
280 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ | 270 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ |
281 | { 0x0058, 0x0000 }, /* R88 - DC Servo Readback */ | ||
282 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ | 271 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ |
283 | { 0x0100, 0x0003 }, /* R256 - Chip Revision */ | ||
284 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ | 272 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ |
285 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ | 273 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ |
286 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ | 274 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ |
@@ -292,7 +280,6 @@ static struct reg_default wm8994_defaults[] = { | |||
292 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ | 280 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ |
293 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ | 281 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ |
294 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ | 282 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ |
295 | { 0x0212, 0x0000 }, /* R530 - Rate Status */ | ||
296 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ | 283 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ |
297 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ | 284 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ |
298 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ | 285 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ |
@@ -445,9 +432,6 @@ static struct reg_default wm8994_defaults[] = { | |||
445 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ | 432 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ |
446 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ | 433 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ |
447 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ | 434 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ |
448 | { 0x0730, 0x0000 }, /* R1840 - Interrupt Status 1 */ | ||
449 | { 0x0731, 0x0000 }, /* R1841 - Interrupt Status 2 */ | ||
450 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ | ||
451 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ | 435 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ |
452 | { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */ | 436 | { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */ |
453 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ | 437 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ |
@@ -455,7 +439,6 @@ static struct reg_default wm8994_defaults[] = { | |||
455 | }; | 439 | }; |
456 | 440 | ||
457 | static struct reg_default wm8958_defaults[] = { | 441 | static struct reg_default wm8958_defaults[] = { |
458 | { 0x0000, 0x8958 }, /* R0 - Software Reset */ | ||
459 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | 442 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
460 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | 443 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
461 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | 444 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
@@ -970,6 +953,7 @@ static bool wm8994_readable_register(struct device *dev, unsigned int reg) | |||
970 | { | 953 | { |
971 | switch (reg) { | 954 | switch (reg) { |
972 | case WM8994_DC_SERVO_READBACK: | 955 | case WM8994_DC_SERVO_READBACK: |
956 | case WM8994_MICBIAS: | ||
973 | case WM8994_WRITE_SEQUENCER_CTRL_1: | 957 | case WM8994_WRITE_SEQUENCER_CTRL_1: |
974 | case WM8994_WRITE_SEQUENCER_CTRL_2: | 958 | case WM8994_WRITE_SEQUENCER_CTRL_2: |
975 | case WM8994_AIF1_ADC2_LEFT_VOLUME: | 959 | case WM8994_AIF1_ADC2_LEFT_VOLUME: |