aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/mfd/wm8400-core.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/mfd/wm8400-core.c')
-rw-r--r--drivers/mfd/wm8400-core.c455
1 files changed, 455 insertions, 0 deletions
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
new file mode 100644
index 000000000000..6a0cedb5bb8a
--- /dev/null
+++ b/drivers/mfd/wm8400-core.c
@@ -0,0 +1,455 @@
1/*
2 * Core driver for WM8400.
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/bug.h>
16#include <linux/i2c.h>
17#include <linux/kernel.h>
18#include <linux/mfd/wm8400-private.h>
19#include <linux/mfd/wm8400-audio.h>
20
21static struct {
22 u16 readable; /* Mask of readable bits */
23 u16 writable; /* Mask of writable bits */
24 u16 vol; /* Mask of volatile bits */
25 int is_codec; /* Register controlled by codec reset */
26 u16 default_val; /* Value on reset */
27} reg_data[] = {
28 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
29 { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
30 { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
31 { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
32 { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
33 { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
34 { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
35 { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
36 { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
37 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
38 { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
39 { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
40 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
41 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
42 { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
43 { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
44 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
45 { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
46 { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
47 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
48 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
49 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
50 { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
51 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
52 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
53 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
54 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
55 { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
56 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
57 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
58 { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
59 { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
60 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
61 { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
62 { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
63 { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
64 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
65 { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
66 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
67 { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
68 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
69 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
70 { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
71 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
72 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
73 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
74 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
75 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
76 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
77 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
78 { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
79 { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
80 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
81 { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
82 { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
83 { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
84 { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
85 { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
86 { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
87 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
88 { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
89 { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
90 { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
91 { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
92 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
93 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
94 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
95 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
96 { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
97 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
98 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
99 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
100 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
101 { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
102 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
103 { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
104 { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
105 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
106 { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
107 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
108 { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
109 { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
110 { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
111 { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
112 { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
113};
114
115static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
116{
117 int i, ret = 0;
118
119 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
120
121 /* If there are any volatile reads then read back the entire block */
122 for (i = reg; i < reg + num_regs; i++)
123 if (reg_data[i].vol) {
124 ret = wm8400->read_dev(wm8400->io_data, reg,
125 num_regs, dest);
126 if (ret != 0)
127 return ret;
128 for (i = 0; i < num_regs; i++)
129 dest[i] = be16_to_cpu(dest[i]);
130
131 return 0;
132 }
133
134 /* Otherwise use the cache */
135 memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
136
137 return 0;
138}
139
140static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
141 u16 *src)
142{
143 int ret, i;
144
145 BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
146
147 for (i = 0; i < num_regs; i++) {
148 BUG_ON(!reg_data[reg + i].writable);
149 wm8400->reg_cache[reg + i] = src[i];
150 src[i] = cpu_to_be16(src[i]);
151 }
152
153 /* Do the actual I/O */
154 ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
155 if (ret != 0)
156 return -EIO;
157
158 return 0;
159}
160
161/**
162 * wm8400_reg_read - Single register read
163 *
164 * @wm8400: Pointer to wm8400 control structure
165 * @reg: Register to read
166 *
167 * @return Read value
168 */
169u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
170{
171 u16 val;
172
173 mutex_lock(&wm8400->io_lock);
174
175 wm8400_read(wm8400, reg, 1, &val);
176
177 mutex_unlock(&wm8400->io_lock);
178
179 return val;
180}
181EXPORT_SYMBOL_GPL(wm8400_reg_read);
182
183int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
184{
185 int ret;
186
187 mutex_lock(&wm8400->io_lock);
188
189 ret = wm8400_read(wm8400, reg, count, data);
190
191 mutex_unlock(&wm8400->io_lock);
192
193 return ret;
194}
195EXPORT_SYMBOL_GPL(wm8400_block_read);
196
197/**
198 * wm8400_set_bits - Bitmask write
199 *
200 * @wm8400: Pointer to wm8400 control structure
201 * @reg: Register to access
202 * @mask: Mask of bits to change
203 * @val: Value to set for masked bits
204 */
205int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
206{
207 u16 tmp;
208 int ret;
209
210 mutex_lock(&wm8400->io_lock);
211
212 ret = wm8400_read(wm8400, reg, 1, &tmp);
213 tmp = (tmp & ~mask) | val;
214 if (ret == 0)
215 ret = wm8400_write(wm8400, reg, 1, &tmp);
216
217 mutex_unlock(&wm8400->io_lock);
218
219 return ret;
220}
221EXPORT_SYMBOL_GPL(wm8400_set_bits);
222
223/**
224 * wm8400_reset_codec_reg_cache - Reset cached codec registers to
225 * their default values.
226 */
227void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
228{
229 int i;
230
231 mutex_lock(&wm8400->io_lock);
232
233 /* Reset all codec registers to their initial value */
234 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
235 if (reg_data[i].is_codec)
236 wm8400->reg_cache[i] = reg_data[i].default_val;
237
238 mutex_unlock(&wm8400->io_lock);
239}
240EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
241
242/*
243 * wm8400_init - Generic initialisation
244 *
245 * The WM8400 can be configured as either an I2C or SPI device. Probe
246 * functions for each bus set up the accessors then call into this to
247 * set up the device itself.
248 */
249static int wm8400_init(struct wm8400 *wm8400,
250 struct wm8400_platform_data *pdata)
251{
252 u16 reg;
253 int ret, i;
254
255 mutex_init(&wm8400->io_lock);
256
257 wm8400->dev->driver_data = wm8400;
258
259 /* Check that this is actually a WM8400 */
260 ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
261 if (ret != 0) {
262 dev_err(wm8400->dev, "Chip ID register read failed\n");
263 return -EIO;
264 }
265 if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
266 dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
267 be16_to_cpu(reg));
268 return -ENODEV;
269 }
270
271 /* We don't know what state the hardware is in and since this
272 * is a PMIC we can't reset it safely so initialise the register
273 * cache from the hardware.
274 */
275 ret = wm8400->read_dev(wm8400->io_data, 0,
276 ARRAY_SIZE(wm8400->reg_cache),
277 wm8400->reg_cache);
278 if (ret != 0) {
279 dev_err(wm8400->dev, "Register cache read failed\n");
280 return -EIO;
281 }
282 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
283 wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
284
285 /* If the codec is in reset use hard coded values */
286 if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
287 for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
288 if (reg_data[i].is_codec)
289 wm8400->reg_cache[i] = reg_data[i].default_val;
290
291 ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
292 if (ret != 0) {
293 dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
294 return ret;
295 }
296 reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
297 dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
298
299 if (pdata && pdata->platform_init) {
300 ret = pdata->platform_init(wm8400->dev);
301 if (ret != 0)
302 dev_err(wm8400->dev, "Platform init failed: %d\n",
303 ret);
304 } else
305 dev_warn(wm8400->dev, "No platform initialisation supplied\n");
306
307 return ret;
308}
309
310static void wm8400_release(struct wm8400 *wm8400)
311{
312 int i;
313
314 for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
315 if (wm8400->regulators[i].name)
316 platform_device_unregister(&wm8400->regulators[i]);
317}
318
319#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
320static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
321{
322 struct i2c_client *i2c = io_data;
323 struct i2c_msg xfer[2];
324 int ret;
325
326 /* Write register */
327 xfer[0].addr = i2c->addr;
328 xfer[0].flags = 0;
329 xfer[0].len = 1;
330 xfer[0].buf = &reg;
331
332 /* Read data */
333 xfer[1].addr = i2c->addr;
334 xfer[1].flags = I2C_M_RD;
335 xfer[1].len = count * sizeof(u16);
336 xfer[1].buf = (u8 *)dest;
337
338 ret = i2c_transfer(i2c->adapter, xfer, 2);
339 if (ret == 2)
340 ret = 0;
341 else if (ret >= 0)
342 ret = -EIO;
343
344 return ret;
345}
346
347static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
348{
349 struct i2c_client *i2c = io_data;
350 u8 *msg;
351 int ret;
352
353 /* We add 1 byte for device register - ideally I2C would gather. */
354 msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
355 if (msg == NULL)
356 return -ENOMEM;
357
358 msg[0] = reg;
359 memcpy(&msg[1], src, count * sizeof(u16));
360
361 ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
362
363 if (ret == (count * 2) + 1)
364 ret = 0;
365 else if (ret >= 0)
366 ret = -EIO;
367
368 kfree(msg);
369
370 return ret;
371}
372
373static int wm8400_i2c_probe(struct i2c_client *i2c,
374 const struct i2c_device_id *id)
375{
376 struct wm8400 *wm8400;
377 int ret;
378
379 wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
380 if (wm8400 == NULL) {
381 ret = -ENOMEM;
382 goto err;
383 }
384
385 wm8400->io_data = i2c;
386 wm8400->read_dev = wm8400_i2c_read;
387 wm8400->write_dev = wm8400_i2c_write;
388 wm8400->dev = &i2c->dev;
389 i2c_set_clientdata(i2c, wm8400);
390
391 ret = wm8400_init(wm8400, i2c->dev.platform_data);
392 if (ret != 0)
393 goto struct_err;
394
395 return 0;
396
397struct_err:
398 i2c_set_clientdata(i2c, NULL);
399 kfree(wm8400);
400err:
401 return ret;
402}
403
404static int wm8400_i2c_remove(struct i2c_client *i2c)
405{
406 struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
407
408 wm8400_release(wm8400);
409 i2c_set_clientdata(i2c, NULL);
410 kfree(wm8400);
411
412 return 0;
413}
414
415static const struct i2c_device_id wm8400_i2c_id[] = {
416 { "wm8400", 0 },
417 { }
418};
419MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
420
421static struct i2c_driver wm8400_i2c_driver = {
422 .driver = {
423 .name = "WM8400",
424 .owner = THIS_MODULE,
425 },
426 .probe = wm8400_i2c_probe,
427 .remove = wm8400_i2c_remove,
428 .id_table = wm8400_i2c_id,
429};
430#endif
431
432static int __init wm8400_module_init(void)
433{
434 int ret = -ENODEV;
435
436#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
437 ret = i2c_add_driver(&wm8400_i2c_driver);
438 if (ret != 0)
439 pr_err("Failed to register I2C driver: %d\n", ret);
440#endif
441
442 return ret;
443}
444module_init(wm8400_module_init);
445
446static void __exit wm8400_module_exit(void)
447{
448#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
449 i2c_del_driver(&wm8400_i2c_driver);
450#endif
451}
452module_exit(wm8400_module_exit);
453
454MODULE_LICENSE("GPL");
455MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 01:26:36 -0500