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-rw-r--r--drivers/mfd/ti-ssp.c465
1 files changed, 0 insertions, 465 deletions
diff --git a/drivers/mfd/ti-ssp.c b/drivers/mfd/ti-ssp.c
deleted file mode 100644
index a5424579679c..000000000000
--- a/drivers/mfd/ti-ssp.c
+++ /dev/null
@@ -1,465 +0,0 @@
1/*
2 * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
3 *
4 * Copyright (C) 2010 Texas Instruments Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/errno.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/wait.h>
28#include <linux/clk.h>
29#include <linux/interrupt.h>
30#include <linux/device.h>
31#include <linux/spinlock.h>
32#include <linux/platform_device.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35#include <linux/sched.h>
36#include <linux/mfd/core.h>
37#include <linux/mfd/ti_ssp.h>
38
39/* Register Offsets */
40#define REG_REV 0x00
41#define REG_IOSEL_1 0x04
42#define REG_IOSEL_2 0x08
43#define REG_PREDIV 0x0c
44#define REG_INTR_ST 0x10
45#define REG_INTR_EN 0x14
46#define REG_TEST_CTRL 0x18
47
48/* Per port registers */
49#define PORT_CFG_2 0x00
50#define PORT_ADDR 0x04
51#define PORT_DATA 0x08
52#define PORT_CFG_1 0x0c
53#define PORT_STATE 0x10
54
55#define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT)
56#define SSP_PORT_CLKRATE_MASK 0x0f
57
58#define SSP_SEQRAM_WR_EN BIT(4)
59#define SSP_SEQRAM_RD_EN BIT(5)
60#define SSP_START BIT(15)
61#define SSP_BUSY BIT(10)
62#define SSP_PORT_ASL BIT(7)
63#define SSP_PORT_CFO1 BIT(6)
64
65#define SSP_PORT_SEQRAM_SIZE 32
66
67static const int ssp_port_base[] = {0x040, 0x080};
68static const int ssp_port_seqram[] = {0x100, 0x180};
69
70struct ti_ssp {
71 struct resource *res;
72 struct device *dev;
73 void __iomem *regs;
74 spinlock_t lock;
75 struct clk *clk;
76 int irq;
77 wait_queue_head_t wqh;
78
79 /*
80 * Some of the iosel2 register bits always read-back as 0, we need to
81 * remember these values so that we don't clobber previously set
82 * values.
83 */
84 u32 iosel2;
85};
86
87static inline struct ti_ssp *dev_to_ssp(struct device *dev)
88{
89 return dev_get_drvdata(dev->parent);
90}
91
92static inline int dev_to_port(struct device *dev)
93{
94 return to_platform_device(dev)->id;
95}
96
97/* Register Access Helpers, rmw() functions need to run locked */
98static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
99{
100 return __raw_readl(ssp->regs + reg);
101}
102
103static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
104{
105 __raw_writel(val, ssp->regs + reg);
106}
107
108static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
109{
110 ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
111}
112
113static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
114{
115 return ssp_read(ssp, ssp_port_base[port] + reg);
116}
117
118static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
119 u32 val)
120{
121 ssp_write(ssp, ssp_port_base[port] + reg, val);
122}
123
124static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
125 u32 mask, u32 bits)
126{
127 ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
128}
129
130static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
131 u32 bits)
132{
133 ssp_port_rmw(ssp, port, reg, bits, 0);
134}
135
136static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
137 u32 bits)
138{
139 ssp_port_rmw(ssp, port, reg, 0, bits);
140}
141
142/* Called to setup port clock mode, caller must hold ssp->lock */
143static int __set_mode(struct ti_ssp *ssp, int port, int mode)
144{
145 mode &= SSP_PORT_CONFIG_MASK;
146 ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
147
148 return 0;
149}
150
151int ti_ssp_set_mode(struct device *dev, int mode)
152{
153 struct ti_ssp *ssp = dev_to_ssp(dev);
154 int port = dev_to_port(dev);
155 int ret;
156
157 spin_lock(&ssp->lock);
158 ret = __set_mode(ssp, port, mode);
159 spin_unlock(&ssp->lock);
160
161 return ret;
162}
163EXPORT_SYMBOL(ti_ssp_set_mode);
164
165/* Called to setup iosel2, caller must hold ssp->lock */
166static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
167{
168 ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
169 ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
170}
171
172/* Called to setup port iosel, caller must hold ssp->lock */
173static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
174{
175 unsigned val, shift = port ? 16 : 0;
176
177 /* IOSEL1 gets the least significant 16 bits */
178 val = ssp_read(ssp, REG_IOSEL_1);
179 val &= 0xffff << (port ? 0 : 16);
180 val |= (iosel & 0xffff) << (port ? 16 : 0);
181 ssp_write(ssp, REG_IOSEL_1, val);
182
183 /* IOSEL2 gets the most significant 16 bits */
184 val = (iosel >> 16) & 0x7;
185 __set_iosel2(ssp, 0x7 << shift, val << shift);
186}
187
188int ti_ssp_set_iosel(struct device *dev, u32 iosel)
189{
190 struct ti_ssp *ssp = dev_to_ssp(dev);
191 int port = dev_to_port(dev);
192
193 spin_lock(&ssp->lock);
194 __set_iosel(ssp, port, iosel);
195 spin_unlock(&ssp->lock);
196
197 return 0;
198}
199EXPORT_SYMBOL(ti_ssp_set_iosel);
200
201int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
202{
203 struct ti_ssp *ssp = dev_to_ssp(dev);
204 int port = dev_to_port(dev);
205 int i;
206
207 if (len > SSP_PORT_SEQRAM_SIZE)
208 return -ENOSPC;
209
210 spin_lock(&ssp->lock);
211
212 /* Enable SeqRAM access */
213 ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
214
215 /* Copy code */
216 for (i = 0; i < len; i++) {
217 __raw_writel(prog[i], ssp->regs + offs + 4*i +
218 ssp_port_seqram[port]);
219 }
220
221 /* Disable SeqRAM access */
222 ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
223
224 spin_unlock(&ssp->lock);
225
226 return 0;
227}
228EXPORT_SYMBOL(ti_ssp_load);
229
230int ti_ssp_raw_read(struct device *dev)
231{
232 struct ti_ssp *ssp = dev_to_ssp(dev);
233 int port = dev_to_port(dev);
234 int shift = port ? 27 : 11;
235
236 return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
237}
238EXPORT_SYMBOL(ti_ssp_raw_read);
239
240int ti_ssp_raw_write(struct device *dev, u32 val)
241{
242 struct ti_ssp *ssp = dev_to_ssp(dev);
243 int port = dev_to_port(dev), shift;
244
245 spin_lock(&ssp->lock);
246
247 shift = port ? 22 : 6;
248 val &= 0xf;
249 __set_iosel2(ssp, 0xf << shift, val << shift);
250
251 spin_unlock(&ssp->lock);
252
253 return 0;
254}
255EXPORT_SYMBOL(ti_ssp_raw_write);
256
257static inline int __xfer_done(struct ti_ssp *ssp, int port)
258{
259 return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
260}
261
262int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output)
263{
264 struct ti_ssp *ssp = dev_to_ssp(dev);
265 int port = dev_to_port(dev);
266 int ret;
267
268 if (pc & ~(0x3f))
269 return -EINVAL;
270
271 /* Grab ssp->lock to serialize rmw on ssp registers */
272 spin_lock(&ssp->lock);
273
274 ssp_port_write(ssp, port, PORT_ADDR, input >> 16);
275 ssp_port_write(ssp, port, PORT_DATA, input & 0xffff);
276 ssp_port_rmw(ssp, port, PORT_CFG_1, 0x3f, pc);
277
278 /* grab wait queue head lock to avoid race with the isr */
279 spin_lock_irq(&ssp->wqh.lock);
280
281 /* kick off sequence execution in hardware */
282 ssp_port_set_bits(ssp, port, PORT_CFG_1, SSP_START);
283
284 /* drop ssp lock; no register writes beyond this */
285 spin_unlock(&ssp->lock);
286
287 ret = wait_event_interruptible_locked_irq(ssp->wqh,
288 __xfer_done(ssp, port));
289 spin_unlock_irq(&ssp->wqh.lock);
290
291 if (ret < 0)
292 return ret;
293
294 if (output) {
295 *output = (ssp_port_read(ssp, port, PORT_ADDR) << 16) |
296 (ssp_port_read(ssp, port, PORT_DATA) & 0xffff);
297 }
298
299 ret = ssp_port_read(ssp, port, PORT_STATE) & 0x3f; /* stop address */
300
301 return ret;
302}
303EXPORT_SYMBOL(ti_ssp_run);
304
305static irqreturn_t ti_ssp_interrupt(int irq, void *dev_data)
306{
307 struct ti_ssp *ssp = dev_data;
308
309 spin_lock(&ssp->wqh.lock);
310
311 ssp_write(ssp, REG_INTR_ST, 0x3);
312 wake_up_locked(&ssp->wqh);
313
314 spin_unlock(&ssp->wqh.lock);
315
316 return IRQ_HANDLED;
317}
318
319static int ti_ssp_probe(struct platform_device *pdev)
320{
321 static struct ti_ssp *ssp;
322 const struct ti_ssp_data *pdata = dev_get_platdata(&pdev->dev);
323 int error = 0, prediv = 0xff, id;
324 unsigned long sysclk;
325 struct device *dev = &pdev->dev;
326 struct mfd_cell cells[2];
327
328 ssp = kzalloc(sizeof(*ssp), GFP_KERNEL);
329 if (!ssp) {
330 dev_err(dev, "cannot allocate device info\n");
331 return -ENOMEM;
332 }
333
334 ssp->dev = dev;
335 dev_set_drvdata(dev, ssp);
336
337 ssp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
338 if (!ssp->res) {
339 error = -ENODEV;
340 dev_err(dev, "cannot determine register area\n");
341 goto error_res;
342 }
343
344 if (!request_mem_region(ssp->res->start, resource_size(ssp->res),
345 pdev->name)) {
346 error = -ENOMEM;
347 dev_err(dev, "cannot claim register memory\n");
348 goto error_res;
349 }
350
351 ssp->regs = ioremap(ssp->res->start, resource_size(ssp->res));
352 if (!ssp->regs) {
353 error = -ENOMEM;
354 dev_err(dev, "cannot map register memory\n");
355 goto error_map;
356 }
357
358 ssp->clk = clk_get(dev, NULL);
359 if (IS_ERR(ssp->clk)) {
360 error = PTR_ERR(ssp->clk);
361 dev_err(dev, "cannot claim device clock\n");
362 goto error_clk;
363 }
364
365 ssp->irq = platform_get_irq(pdev, 0);
366 if (ssp->irq < 0) {
367 error = -ENODEV;
368 dev_err(dev, "unknown irq\n");
369 goto error_irq;
370 }
371
372 error = request_threaded_irq(ssp->irq, NULL, ti_ssp_interrupt, 0,
373 dev_name(dev), ssp);
374 if (error < 0) {
375 dev_err(dev, "cannot acquire irq\n");
376 goto error_irq;
377 }
378
379 spin_lock_init(&ssp->lock);
380 init_waitqueue_head(&ssp->wqh);
381
382 /* Power on and initialize SSP */
383 error = clk_enable(ssp->clk);
384 if (error) {
385 dev_err(dev, "cannot enable device clock\n");
386 goto error_enable;
387 }
388
389 /* Reset registers to a sensible known state */
390 ssp_write(ssp, REG_IOSEL_1, 0);
391 ssp_write(ssp, REG_IOSEL_2, 0);
392 ssp_write(ssp, REG_INTR_EN, 0x3);
393 ssp_write(ssp, REG_INTR_ST, 0x3);
394 ssp_write(ssp, REG_TEST_CTRL, 0);
395 ssp_port_write(ssp, 0, PORT_CFG_1, SSP_PORT_ASL);
396 ssp_port_write(ssp, 1, PORT_CFG_1, SSP_PORT_ASL);
397 ssp_port_write(ssp, 0, PORT_CFG_2, SSP_PORT_CFO1);
398 ssp_port_write(ssp, 1, PORT_CFG_2, SSP_PORT_CFO1);
399
400 sysclk = clk_get_rate(ssp->clk);
401 if (pdata && pdata->out_clock)
402 prediv = (sysclk / pdata->out_clock) - 1;
403 prediv = clamp(prediv, 0, 0xff);
404 ssp_rmw(ssp, REG_PREDIV, 0xff, prediv);
405
406 memset(cells, 0, sizeof(cells));
407 for (id = 0; id < 2; id++) {
408 const struct ti_ssp_dev_data *data = &pdata->dev_data[id];
409
410 cells[id].id = id;
411 cells[id].name = data->dev_name;
412 cells[id].platform_data = data->pdata;
413 }
414
415 error = mfd_add_devices(dev, 0, cells, 2, NULL, 0, NULL);
416 if (error < 0) {
417 dev_err(dev, "cannot add mfd cells\n");
418 goto error_enable;
419 }
420
421 return 0;
422
423error_enable:
424 free_irq(ssp->irq, ssp);
425error_irq:
426 clk_put(ssp->clk);
427error_clk:
428 iounmap(ssp->regs);
429error_map:
430 release_mem_region(ssp->res->start, resource_size(ssp->res));
431error_res:
432 kfree(ssp);
433 return error;
434}
435
436static int ti_ssp_remove(struct platform_device *pdev)
437{
438 struct device *dev = &pdev->dev;
439 struct ti_ssp *ssp = dev_get_drvdata(dev);
440
441 mfd_remove_devices(dev);
442 clk_disable(ssp->clk);
443 free_irq(ssp->irq, ssp);
444 clk_put(ssp->clk);
445 iounmap(ssp->regs);
446 release_mem_region(ssp->res->start, resource_size(ssp->res));
447 kfree(ssp);
448 return 0;
449}
450
451static struct platform_driver ti_ssp_driver = {
452 .probe = ti_ssp_probe,
453 .remove = ti_ssp_remove,
454 .driver = {
455 .name = "ti-ssp",
456 .owner = THIS_MODULE,
457 }
458};
459
460module_platform_driver(ti_ssp_driver);
461
462MODULE_DESCRIPTION("Sequencer Serial Port (SSP) Driver");
463MODULE_AUTHOR("Cyril Chemparathy");
464MODULE_LICENSE("GPL");
465MODULE_ALIAS("platform:ti-ssp");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 23:14:29 -0500