1 files changed, 89 insertions, 21 deletions

diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 15dc848bc081..3b835f593e35 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -17,7 +17,6 @@
  *
  * Author:
  *   Wei WANG <wei_wang@realsil.com.cn>
- *   No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
  */
 
 #include <linux/module.h>
@@ -34,24 +33,95 @@ static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
         return val & 0x0F;
 }
 
+static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
+{
+        u8 driving_3v3[4][3] = {
+                {0x11, 0x11, 0x11},
+                {0x55, 0x55, 0x5C},
+                {0x99, 0x99, 0x92},
+                {0x99, 0x99, 0x92},
+        };
+        u8 driving_1v8[4][3] = {
+                {0x3C, 0x3C, 0x3C},
+                {0xB3, 0xB3, 0xB3},
+                {0xFE, 0xFE, 0xFE},
+                {0xC4, 0xC4, 0xC4},
+        };
+        u8 (*driving)[3], drive_sel;
+
+        if (voltage == OUTPUT_3V3) {
+                driving = driving_3v3;
+                drive_sel = pcr->sd30_drive_sel_3v3;
+        } else {
+                driving = driving_1v8;
+                drive_sel = pcr->sd30_drive_sel_1v8;
+        }
+
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
+                        0xFF, driving[drive_sel][0]);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
+                        0xFF, driving[drive_sel][1]);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
+                        0xFF, driving[drive_sel][2]);
+}
+
+static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
+{
+        u32 reg;
+
+        rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
+        dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+
+        if (!rtsx_vendor_setting_valid(reg))
+                return;
+
+        pcr->aspm_en = rtsx_reg_to_aspm(reg);
+        pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
+        pcr->card_drive_sel &= 0x3F;
+        pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
+
+        rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
+        dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
+        pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
+        if (rtsx_reg_check_reverse_socket(reg))
+                pcr->flags |= PCR_REVERSE_SOCKET;
+}
+
+static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
+{
+        /* Set relink_time to 0 */
+        rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
+        rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
+        rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
+
+        if (pm_state == HOST_ENTER_S3)
+                rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
+
+        rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
+}
+
 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 {
         rtsx_pci_init_cmd(pcr);
 
         /* Configure GPIO as output */
         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
+        /* Reset ASPM state to default value */
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
         /* Switch LDO3318 source from DV33 to card_3v3 */
         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
         /* LED shine disabled, set initial shine cycle period */
         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
-        /* Correct driving */
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-                        SD30_CLK_DRIVE_SEL, 0xFF, 0x99);
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-                        SD30_CMD_DRIVE_SEL, 0xFF, 0x99);
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-                        SD30_DAT_DRIVE_SEL, 0xFF, 0x92);
+        /* Configure driving */
+        rts5249_fill_driving(pcr, OUTPUT_3V3);
+        if (pcr->flags & PCR_REVERSE_SOCKET)
+                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
+                                AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
+        else
+                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
+                                AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
+        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
 
         return rtsx_pci_send_cmd(pcr, 100);
 }
@@ -129,15 +199,11 @@ static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
 static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 {
         int err;
-        u8 clk_drive, cmd_drive, dat_drive;
 
         if (voltage == OUTPUT_3V3) {
                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
                 if (err < 0)
                         return err;
-                clk_drive = 0x99;
-                cmd_drive = 0x99;
-                dat_drive = 0x92;
         } else if (voltage == OUTPUT_1V8) {
                 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
                 if (err < 0)
@@ -145,25 +211,18 @@ static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
                 if (err < 0)
                         return err;
-                clk_drive = 0xb3;
-                cmd_drive = 0xb3;
-                dat_drive = 0xb3;
         } else {
                 return -EINVAL;
         }
 
         /* set pad drive */
         rtsx_pci_init_cmd(pcr);
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
-                        0xFF, clk_drive);
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
-                        0xFF, cmd_drive);
-        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
-                        0xFF, dat_drive);
+        rts5249_fill_driving(pcr, voltage);
         return rtsx_pci_send_cmd(pcr, 100);
 }
 
 static const struct pcr_ops rts5249_pcr_ops = {
+        .fetch_vendor_settings = rts5249_fetch_vendor_settings,
         .extra_init_hw = rts5249_extra_init_hw,
         .optimize_phy = rts5249_optimize_phy,
         .turn_on_led = rts5249_turn_on_led,
@@ -173,6 +232,7 @@ static const struct pcr_ops rts5249_pcr_ops = {
         .card_power_on = rts5249_card_power_on,
         .card_power_off = rts5249_card_power_off,
         .switch_output_voltage = rts5249_switch_output_voltage,
+        .force_power_down = rts5249_force_power_down,
 };
 
 /* SD Pull Control Enable:
@@ -233,6 +293,14 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
         pcr->num_slots = 2;
         pcr->ops = &rts5249_pcr_ops;
 
+        pcr->flags = 0;
+        pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
+        pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
+        pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
+        pcr->aspm_en = ASPM_L1_EN;
+        pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
+        pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
+
         pcr->ic_version = rts5249_get_ic_version(pcr);
         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;