diff options
Diffstat (limited to 'drivers/mfd/omap-usb-host.c')
-rw-r--r-- | drivers/mfd/omap-usb-host.c | 231 |
1 files changed, 10 insertions, 221 deletions
diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c index 8a256dfe6ddf..23cec57c02ba 100644 --- a/drivers/mfd/omap-usb-host.c +++ b/drivers/mfd/omap-usb-host.c | |||
@@ -35,63 +35,6 @@ | |||
35 | 35 | ||
36 | /* OMAP USBHOST Register addresses */ | 36 | /* OMAP USBHOST Register addresses */ |
37 | 37 | ||
38 | /* TLL Register Set */ | ||
39 | #define OMAP_USBTLL_REVISION (0x00) | ||
40 | #define OMAP_USBTLL_SYSCONFIG (0x10) | ||
41 | #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) | ||
42 | #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) | ||
43 | #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) | ||
44 | #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) | ||
45 | #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) | ||
46 | |||
47 | #define OMAP_USBTLL_SYSSTATUS (0x14) | ||
48 | #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) | ||
49 | |||
50 | #define OMAP_USBTLL_IRQSTATUS (0x18) | ||
51 | #define OMAP_USBTLL_IRQENABLE (0x1C) | ||
52 | |||
53 | #define OMAP_TLL_SHARED_CONF (0x30) | ||
54 | #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) | ||
55 | #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) | ||
56 | #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) | ||
57 | #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) | ||
58 | #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) | ||
59 | |||
60 | #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) | ||
61 | #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 | ||
62 | #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) | ||
63 | #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) | ||
64 | #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) | ||
65 | #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) | ||
66 | #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) | ||
67 | #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) | ||
68 | |||
69 | #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 | ||
70 | #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 | ||
71 | #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 | ||
72 | #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 | ||
73 | #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 | ||
74 | #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 | ||
75 | #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 | ||
76 | #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 | ||
77 | #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA | ||
78 | #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB | ||
79 | |||
80 | #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) | ||
81 | #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) | ||
82 | #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) | ||
83 | #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) | ||
84 | #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) | ||
85 | #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) | ||
86 | #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) | ||
87 | #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) | ||
88 | #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) | ||
89 | |||
90 | #define OMAP_TLL_CHANNEL_COUNT 3 | ||
91 | #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) | ||
92 | #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) | ||
93 | #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) | ||
94 | |||
95 | /* UHH Register Set */ | 38 | /* UHH Register Set */ |
96 | #define OMAP_UHH_REVISION (0x00) | 39 | #define OMAP_UHH_REVISION (0x00) |
97 | #define OMAP_UHH_SYSCONFIG (0x10) | 40 | #define OMAP_UHH_SYSCONFIG (0x10) |
@@ -131,8 +74,6 @@ | |||
131 | #define OMAP4_P2_MODE_TLL (1 << 18) | 74 | #define OMAP4_P2_MODE_TLL (1 << 18) |
132 | #define OMAP4_P2_MODE_HSIC (3 << 18) | 75 | #define OMAP4_P2_MODE_HSIC (3 << 18) |
133 | 76 | ||
134 | #define OMAP_REV2_TLL_CHANNEL_COUNT 2 | ||
135 | |||
136 | #define OMAP_UHH_DEBUG_CSR (0x44) | 77 | #define OMAP_UHH_DEBUG_CSR (0x44) |
137 | 78 | ||
138 | /* Values of UHH_REVISION - Note: these are not given in the TRM */ | 79 | /* Values of UHH_REVISION - Note: these are not given in the TRM */ |
@@ -152,15 +93,12 @@ struct usbhs_hcd_omap { | |||
152 | struct clk *xclk60mhsp2_ck; | 93 | struct clk *xclk60mhsp2_ck; |
153 | struct clk *utmi_p1_fck; | 94 | struct clk *utmi_p1_fck; |
154 | struct clk *usbhost_p1_fck; | 95 | struct clk *usbhost_p1_fck; |
155 | struct clk *usbtll_p1_fck; | ||
156 | struct clk *utmi_p2_fck; | 96 | struct clk *utmi_p2_fck; |
157 | struct clk *usbhost_p2_fck; | 97 | struct clk *usbhost_p2_fck; |
158 | struct clk *usbtll_p2_fck; | ||
159 | struct clk *init_60m_fclk; | 98 | struct clk *init_60m_fclk; |
160 | struct clk *ehci_logic_fck; | 99 | struct clk *ehci_logic_fck; |
161 | 100 | ||
162 | void __iomem *uhh_base; | 101 | void __iomem *uhh_base; |
163 | void __iomem *tll_base; | ||
164 | 102 | ||
165 | struct usbhs_omap_platform_data platdata; | 103 | struct usbhs_omap_platform_data platdata; |
166 | 104 | ||
@@ -335,93 +273,6 @@ static bool is_ohci_port(enum usbhs_omap_port_mode pmode) | |||
335 | } | 273 | } |
336 | } | 274 | } |
337 | 275 | ||
338 | /* | ||
339 | * convert the port-mode enum to a value we can use in the FSLSMODE | ||
340 | * field of USBTLL_CHANNEL_CONF | ||
341 | */ | ||
342 | static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) | ||
343 | { | ||
344 | switch (mode) { | ||
345 | case OMAP_USBHS_PORT_MODE_UNUSED: | ||
346 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | ||
347 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; | ||
348 | |||
349 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | ||
350 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; | ||
351 | |||
352 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | ||
353 | return OMAP_TLL_FSLSMODE_3PIN_PHY; | ||
354 | |||
355 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | ||
356 | return OMAP_TLL_FSLSMODE_4PIN_PHY; | ||
357 | |||
358 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | ||
359 | return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; | ||
360 | |||
361 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | ||
362 | return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; | ||
363 | |||
364 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | ||
365 | return OMAP_TLL_FSLSMODE_3PIN_TLL; | ||
366 | |||
367 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | ||
368 | return OMAP_TLL_FSLSMODE_4PIN_TLL; | ||
369 | |||
370 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | ||
371 | return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; | ||
372 | |||
373 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | ||
374 | return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; | ||
375 | default: | ||
376 | pr_warning("Invalid port mode, using default\n"); | ||
377 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; | ||
378 | } | ||
379 | } | ||
380 | |||
381 | static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) | ||
382 | { | ||
383 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | ||
384 | struct usbhs_omap_platform_data *pdata = dev->platform_data; | ||
385 | unsigned reg; | ||
386 | int i; | ||
387 | |||
388 | /* Program Common TLL register */ | ||
389 | reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); | ||
390 | reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON | ||
391 | | OMAP_TLL_SHARED_CONF_USB_DIVRATION); | ||
392 | reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; | ||
393 | reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; | ||
394 | |||
395 | usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); | ||
396 | |||
397 | /* Enable channels now */ | ||
398 | for (i = 0; i < tll_channel_count; i++) { | ||
399 | reg = usbhs_read(omap->tll_base, | ||
400 | OMAP_TLL_CHANNEL_CONF(i)); | ||
401 | |||
402 | if (is_ohci_port(pdata->port_mode[i])) { | ||
403 | reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) | ||
404 | << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; | ||
405 | reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; | ||
406 | } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { | ||
407 | |||
408 | /* Disable AutoIdle, BitStuffing and use SDR Mode */ | ||
409 | reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE | ||
410 | | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF | ||
411 | | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); | ||
412 | |||
413 | } else | ||
414 | continue; | ||
415 | |||
416 | reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; | ||
417 | usbhs_write(omap->tll_base, | ||
418 | OMAP_TLL_CHANNEL_CONF(i), reg); | ||
419 | |||
420 | usbhs_writeb(omap->tll_base, | ||
421 | OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); | ||
422 | } | ||
423 | } | ||
424 | |||
425 | static int usbhs_runtime_resume(struct device *dev) | 276 | static int usbhs_runtime_resume(struct device *dev) |
426 | { | 277 | { |
427 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | 278 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); |
@@ -441,14 +292,11 @@ static int usbhs_runtime_resume(struct device *dev) | |||
441 | if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck)) | 292 | if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck)) |
442 | clk_enable(omap->ehci_logic_fck); | 293 | clk_enable(omap->ehci_logic_fck); |
443 | 294 | ||
444 | if (is_ehci_tll_mode(pdata->port_mode[0])) { | 295 | if (is_ehci_tll_mode(pdata->port_mode[0])) |
445 | clk_enable(omap->usbhost_p1_fck); | 296 | clk_enable(omap->usbhost_p1_fck); |
446 | clk_enable(omap->usbtll_p1_fck); | 297 | if (is_ehci_tll_mode(pdata->port_mode[1])) |
447 | } | ||
448 | if (is_ehci_tll_mode(pdata->port_mode[1])) { | ||
449 | clk_enable(omap->usbhost_p2_fck); | 298 | clk_enable(omap->usbhost_p2_fck); |
450 | clk_enable(omap->usbtll_p2_fck); | 299 | |
451 | } | ||
452 | clk_enable(omap->utmi_p1_fck); | 300 | clk_enable(omap->utmi_p1_fck); |
453 | clk_enable(omap->utmi_p2_fck); | 301 | clk_enable(omap->utmi_p2_fck); |
454 | 302 | ||
@@ -472,14 +320,11 @@ static int usbhs_runtime_suspend(struct device *dev) | |||
472 | 320 | ||
473 | spin_lock_irqsave(&omap->lock, flags); | 321 | spin_lock_irqsave(&omap->lock, flags); |
474 | 322 | ||
475 | if (is_ehci_tll_mode(pdata->port_mode[0])) { | 323 | if (is_ehci_tll_mode(pdata->port_mode[0])) |
476 | clk_disable(omap->usbhost_p1_fck); | 324 | clk_disable(omap->usbhost_p1_fck); |
477 | clk_disable(omap->usbtll_p1_fck); | 325 | if (is_ehci_tll_mode(pdata->port_mode[1])) |
478 | } | ||
479 | if (is_ehci_tll_mode(pdata->port_mode[1])) { | ||
480 | clk_disable(omap->usbhost_p2_fck); | 326 | clk_disable(omap->usbhost_p2_fck); |
481 | clk_disable(omap->usbtll_p2_fck); | 327 | |
482 | } | ||
483 | clk_disable(omap->utmi_p2_fck); | 328 | clk_disable(omap->utmi_p2_fck); |
484 | clk_disable(omap->utmi_p1_fck); | 329 | clk_disable(omap->utmi_p1_fck); |
485 | 330 | ||
@@ -501,8 +346,6 @@ static void omap_usbhs_init(struct device *dev) | |||
501 | 346 | ||
502 | dev_dbg(dev, "starting TI HSUSB Controller\n"); | 347 | dev_dbg(dev, "starting TI HSUSB Controller\n"); |
503 | 348 | ||
504 | pm_runtime_get_sync(dev); | ||
505 | |||
506 | if (pdata->ehci_data->phy_reset) { | 349 | if (pdata->ehci_data->phy_reset) { |
507 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) | 350 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) |
508 | gpio_request_one(pdata->ehci_data->reset_gpio_port[0], | 351 | gpio_request_one(pdata->ehci_data->reset_gpio_port[0], |
@@ -516,6 +359,7 @@ static void omap_usbhs_init(struct device *dev) | |||
516 | udelay(10); | 359 | udelay(10); |
517 | } | 360 | } |
518 | 361 | ||
362 | pm_runtime_get_sync(dev); | ||
519 | spin_lock_irqsave(&omap->lock, flags); | 363 | spin_lock_irqsave(&omap->lock, flags); |
520 | omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); | 364 | omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); |
521 | dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); | 365 | dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); |
@@ -581,22 +425,9 @@ static void omap_usbhs_init(struct device *dev) | |||
581 | usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); | 425 | usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); |
582 | dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); | 426 | dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); |
583 | 427 | ||
584 | if (is_ehci_tll_mode(pdata->port_mode[0]) || | ||
585 | is_ehci_tll_mode(pdata->port_mode[1]) || | ||
586 | is_ehci_tll_mode(pdata->port_mode[2]) || | ||
587 | (is_ohci_port(pdata->port_mode[0])) || | ||
588 | (is_ohci_port(pdata->port_mode[1])) || | ||
589 | (is_ohci_port(pdata->port_mode[2]))) { | ||
590 | |||
591 | /* Enable UTMI mode for required TLL channels */ | ||
592 | if (is_omap_usbhs_rev2(omap)) | ||
593 | usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); | ||
594 | else | ||
595 | usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); | ||
596 | } | ||
597 | |||
598 | spin_unlock_irqrestore(&omap->lock, flags); | 428 | spin_unlock_irqrestore(&omap->lock, flags); |
599 | 429 | ||
430 | pm_runtime_put_sync(dev); | ||
600 | if (pdata->ehci_data->phy_reset) { | 431 | if (pdata->ehci_data->phy_reset) { |
601 | /* Hold the PHY in RESET for enough time till | 432 | /* Hold the PHY in RESET for enough time till |
602 | * PHY is settled and ready | 433 | * PHY is settled and ready |
@@ -611,8 +442,6 @@ static void omap_usbhs_init(struct device *dev) | |||
611 | gpio_set_value_cansleep | 442 | gpio_set_value_cansleep |
612 | (pdata->ehci_data->reset_gpio_port[1], 1); | 443 | (pdata->ehci_data->reset_gpio_port[1], 1); |
613 | } | 444 | } |
614 | |||
615 | pm_runtime_put_sync(dev); | ||
616 | } | 445 | } |
617 | 446 | ||
618 | static void omap_usbhs_deinit(struct device *dev) | 447 | static void omap_usbhs_deinit(struct device *dev) |
@@ -715,32 +544,18 @@ static int __devinit usbhs_omap_probe(struct platform_device *pdev) | |||
715 | goto err_xclk60mhsp2_ck; | 544 | goto err_xclk60mhsp2_ck; |
716 | } | 545 | } |
717 | 546 | ||
718 | omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); | ||
719 | if (IS_ERR(omap->usbtll_p1_fck)) { | ||
720 | ret = PTR_ERR(omap->usbtll_p1_fck); | ||
721 | dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); | ||
722 | goto err_usbhost_p1_fck; | ||
723 | } | ||
724 | |||
725 | omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); | 547 | omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); |
726 | if (IS_ERR(omap->usbhost_p2_fck)) { | 548 | if (IS_ERR(omap->usbhost_p2_fck)) { |
727 | ret = PTR_ERR(omap->usbhost_p2_fck); | 549 | ret = PTR_ERR(omap->usbhost_p2_fck); |
728 | dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); | 550 | dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); |
729 | goto err_usbtll_p1_fck; | 551 | goto err_usbhost_p1_fck; |
730 | } | ||
731 | |||
732 | omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); | ||
733 | if (IS_ERR(omap->usbtll_p2_fck)) { | ||
734 | ret = PTR_ERR(omap->usbtll_p2_fck); | ||
735 | dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); | ||
736 | goto err_usbhost_p2_fck; | ||
737 | } | 552 | } |
738 | 553 | ||
739 | omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); | 554 | omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); |
740 | if (IS_ERR(omap->init_60m_fclk)) { | 555 | if (IS_ERR(omap->init_60m_fclk)) { |
741 | ret = PTR_ERR(omap->init_60m_fclk); | 556 | ret = PTR_ERR(omap->init_60m_fclk); |
742 | dev_err(dev, "init_60m_fclk failed error:%d\n", ret); | 557 | dev_err(dev, "init_60m_fclk failed error:%d\n", ret); |
743 | goto err_usbtll_p2_fck; | 558 | goto err_usbhost_p2_fck; |
744 | } | 559 | } |
745 | 560 | ||
746 | if (is_ehci_phy_mode(pdata->port_mode[0])) { | 561 | if (is_ehci_phy_mode(pdata->port_mode[0])) { |
@@ -786,20 +601,6 @@ static int __devinit usbhs_omap_probe(struct platform_device *pdev) | |||
786 | goto err_init_60m_fclk; | 601 | goto err_init_60m_fclk; |
787 | } | 602 | } |
788 | 603 | ||
789 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); | ||
790 | if (!res) { | ||
791 | dev_err(dev, "UHH EHCI get resource failed\n"); | ||
792 | ret = -ENODEV; | ||
793 | goto err_tll; | ||
794 | } | ||
795 | |||
796 | omap->tll_base = ioremap(res->start, resource_size(res)); | ||
797 | if (!omap->tll_base) { | ||
798 | dev_err(dev, "TLL ioremap failed\n"); | ||
799 | ret = -ENOMEM; | ||
800 | goto err_tll; | ||
801 | } | ||
802 | |||
803 | platform_set_drvdata(pdev, omap); | 604 | platform_set_drvdata(pdev, omap); |
804 | 605 | ||
805 | omap_usbhs_init(dev); | 606 | omap_usbhs_init(dev); |
@@ -813,23 +614,14 @@ static int __devinit usbhs_omap_probe(struct platform_device *pdev) | |||
813 | 614 | ||
814 | err_alloc: | 615 | err_alloc: |
815 | omap_usbhs_deinit(&pdev->dev); | 616 | omap_usbhs_deinit(&pdev->dev); |
816 | iounmap(omap->tll_base); | ||
817 | |||
818 | err_tll: | ||
819 | iounmap(omap->uhh_base); | 617 | iounmap(omap->uhh_base); |
820 | 618 | ||
821 | err_init_60m_fclk: | 619 | err_init_60m_fclk: |
822 | clk_put(omap->init_60m_fclk); | 620 | clk_put(omap->init_60m_fclk); |
823 | 621 | ||
824 | err_usbtll_p2_fck: | ||
825 | clk_put(omap->usbtll_p2_fck); | ||
826 | |||
827 | err_usbhost_p2_fck: | 622 | err_usbhost_p2_fck: |
828 | clk_put(omap->usbhost_p2_fck); | 623 | clk_put(omap->usbhost_p2_fck); |
829 | 624 | ||
830 | err_usbtll_p1_fck: | ||
831 | clk_put(omap->usbtll_p1_fck); | ||
832 | |||
833 | err_usbhost_p1_fck: | 625 | err_usbhost_p1_fck: |
834 | clk_put(omap->usbhost_p1_fck); | 626 | clk_put(omap->usbhost_p1_fck); |
835 | 627 | ||
@@ -865,12 +657,9 @@ static int __devexit usbhs_omap_remove(struct platform_device *pdev) | |||
865 | struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); | 657 | struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); |
866 | 658 | ||
867 | omap_usbhs_deinit(&pdev->dev); | 659 | omap_usbhs_deinit(&pdev->dev); |
868 | iounmap(omap->tll_base); | ||
869 | iounmap(omap->uhh_base); | 660 | iounmap(omap->uhh_base); |
870 | clk_put(omap->init_60m_fclk); | 661 | clk_put(omap->init_60m_fclk); |
871 | clk_put(omap->usbtll_p2_fck); | ||
872 | clk_put(omap->usbhost_p2_fck); | 662 | clk_put(omap->usbhost_p2_fck); |
873 | clk_put(omap->usbtll_p1_fck); | ||
874 | clk_put(omap->usbhost_p1_fck); | 663 | clk_put(omap->usbhost_p1_fck); |
875 | clk_put(omap->xclk60mhsp2_ck); | 664 | clk_put(omap->xclk60mhsp2_ck); |
876 | clk_put(omap->utmi_p2_fck); | 665 | clk_put(omap->utmi_p2_fck); |