diff options
Diffstat (limited to 'drivers/mfd/mcp-sa11x0.c')
-rw-r--r-- | drivers/mfd/mcp-sa11x0.c | 182 |
1 files changed, 116 insertions, 66 deletions
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c index 2dab02d9ac8b..9adc2eb69492 100644 --- a/drivers/mfd/mcp-sa11x0.c +++ b/drivers/mfd/mcp-sa11x0.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/spinlock.h> | 19 | #include <linux/spinlock.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/mfd/mcp.h> | 21 | #include <linux/mfd/mcp.h> |
22 | #include <linux/io.h> | ||
22 | 23 | ||
23 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
@@ -26,12 +27,19 @@ | |||
26 | #include <asm/system.h> | 27 | #include <asm/system.h> |
27 | #include <mach/mcp.h> | 28 | #include <mach/mcp.h> |
28 | 29 | ||
29 | #include <mach/assabet.h> | 30 | /* Register offsets */ |
30 | 31 | #define MCCR0 0x00 | |
32 | #define MCDR0 0x08 | ||
33 | #define MCDR1 0x0C | ||
34 | #define MCDR2 0x10 | ||
35 | #define MCSR 0x18 | ||
36 | #define MCCR1 0x00 | ||
31 | 37 | ||
32 | struct mcp_sa11x0 { | 38 | struct mcp_sa11x0 { |
33 | u32 mccr0; | 39 | u32 mccr0; |
34 | u32 mccr1; | 40 | u32 mccr1; |
41 | unsigned char *mccr0_base; | ||
42 | unsigned char *mccr1_base; | ||
35 | }; | 43 | }; |
36 | 44 | ||
37 | #define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp)) | 45 | #define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp)) |
@@ -39,25 +47,25 @@ struct mcp_sa11x0 { | |||
39 | static void | 47 | static void |
40 | mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) | 48 | mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) |
41 | { | 49 | { |
42 | unsigned int mccr0; | 50 | struct mcp_sa11x0 *priv = priv(mcp); |
43 | 51 | ||
44 | divisor /= 32; | 52 | divisor /= 32; |
45 | 53 | ||
46 | mccr0 = Ser4MCCR0 & ~0x00007f00; | 54 | priv->mccr0 &= ~0x00007f00; |
47 | mccr0 |= divisor << 8; | 55 | priv->mccr0 |= divisor << 8; |
48 | Ser4MCCR0 = mccr0; | 56 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); |
49 | } | 57 | } |
50 | 58 | ||
51 | static void | 59 | static void |
52 | mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) | 60 | mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) |
53 | { | 61 | { |
54 | unsigned int mccr0; | 62 | struct mcp_sa11x0 *priv = priv(mcp); |
55 | 63 | ||
56 | divisor /= 32; | 64 | divisor /= 32; |
57 | 65 | ||
58 | mccr0 = Ser4MCCR0 & ~0x0000007f; | 66 | priv->mccr0 &= ~0x0000007f; |
59 | mccr0 |= divisor; | 67 | priv->mccr0 |= divisor; |
60 | Ser4MCCR0 = mccr0; | 68 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); |
61 | } | 69 | } |
62 | 70 | ||
63 | /* | 71 | /* |
@@ -71,12 +79,16 @@ mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val) | |||
71 | { | 79 | { |
72 | int ret = -ETIME; | 80 | int ret = -ETIME; |
73 | int i; | 81 | int i; |
82 | u32 mcpreg; | ||
83 | struct mcp_sa11x0 *priv = priv(mcp); | ||
74 | 84 | ||
75 | Ser4MCDR2 = reg << 17 | MCDR2_Wr | (val & 0xffff); | 85 | mcpreg = reg << 17 | MCDR2_Wr | (val & 0xffff); |
86 | __raw_writel(mcpreg, priv->mccr0_base + MCDR2); | ||
76 | 87 | ||
77 | for (i = 0; i < 2; i++) { | 88 | for (i = 0; i < 2; i++) { |
78 | udelay(mcp->rw_timeout); | 89 | udelay(mcp->rw_timeout); |
79 | if (Ser4MCSR & MCSR_CWC) { | 90 | mcpreg = __raw_readl(priv->mccr0_base + MCSR); |
91 | if (mcpreg & MCSR_CWC) { | ||
80 | ret = 0; | 92 | ret = 0; |
81 | break; | 93 | break; |
82 | } | 94 | } |
@@ -97,13 +109,18 @@ mcp_sa11x0_read(struct mcp *mcp, unsigned int reg) | |||
97 | { | 109 | { |
98 | int ret = -ETIME; | 110 | int ret = -ETIME; |
99 | int i; | 111 | int i; |
112 | u32 mcpreg; | ||
113 | struct mcp_sa11x0 *priv = priv(mcp); | ||
100 | 114 | ||
101 | Ser4MCDR2 = reg << 17 | MCDR2_Rd; | 115 | mcpreg = reg << 17 | MCDR2_Rd; |
116 | __raw_writel(mcpreg, priv->mccr0_base + MCDR2); | ||
102 | 117 | ||
103 | for (i = 0; i < 2; i++) { | 118 | for (i = 0; i < 2; i++) { |
104 | udelay(mcp->rw_timeout); | 119 | udelay(mcp->rw_timeout); |
105 | if (Ser4MCSR & MCSR_CRC) { | 120 | mcpreg = __raw_readl(priv->mccr0_base + MCSR); |
106 | ret = Ser4MCDR2 & 0xffff; | 121 | if (mcpreg & MCSR_CRC) { |
122 | ret = __raw_readl(priv->mccr0_base + MCDR2) | ||
123 | & 0xffff; | ||
107 | break; | 124 | break; |
108 | } | 125 | } |
109 | } | 126 | } |
@@ -116,13 +133,19 @@ mcp_sa11x0_read(struct mcp *mcp, unsigned int reg) | |||
116 | 133 | ||
117 | static void mcp_sa11x0_enable(struct mcp *mcp) | 134 | static void mcp_sa11x0_enable(struct mcp *mcp) |
118 | { | 135 | { |
119 | Ser4MCSR = -1; | 136 | struct mcp_sa11x0 *priv = priv(mcp); |
120 | Ser4MCCR0 |= MCCR0_MCE; | 137 | |
138 | __raw_writel(-1, priv->mccr0_base + MCSR); | ||
139 | priv->mccr0 |= MCCR0_MCE; | ||
140 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); | ||
121 | } | 141 | } |
122 | 142 | ||
123 | static void mcp_sa11x0_disable(struct mcp *mcp) | 143 | static void mcp_sa11x0_disable(struct mcp *mcp) |
124 | { | 144 | { |
125 | Ser4MCCR0 &= ~MCCR0_MCE; | 145 | struct mcp_sa11x0 *priv = priv(mcp); |
146 | |||
147 | priv->mccr0 &= ~MCCR0_MCE; | ||
148 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); | ||
126 | } | 149 | } |
127 | 150 | ||
128 | /* | 151 | /* |
@@ -142,50 +165,69 @@ static int mcp_sa11x0_probe(struct platform_device *pdev) | |||
142 | struct mcp_plat_data *data = pdev->dev.platform_data; | 165 | struct mcp_plat_data *data = pdev->dev.platform_data; |
143 | struct mcp *mcp; | 166 | struct mcp *mcp; |
144 | int ret; | 167 | int ret; |
168 | struct mcp_sa11x0 *priv; | ||
169 | struct resource *res_mem0, *res_mem1; | ||
170 | u32 size0, size1; | ||
145 | 171 | ||
146 | if (!data) | 172 | if (!data) |
147 | return -ENODEV; | 173 | return -ENODEV; |
148 | 174 | ||
149 | if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp")) | 175 | if (!data->codec) |
176 | return -ENODEV; | ||
177 | |||
178 | res_mem0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
179 | if (!res_mem0) | ||
180 | return -ENODEV; | ||
181 | size0 = res_mem0->end - res_mem0->start + 1; | ||
182 | |||
183 | res_mem1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
184 | if (!res_mem1) | ||
185 | return -ENODEV; | ||
186 | size1 = res_mem1->end - res_mem1->start + 1; | ||
187 | |||
188 | if (!request_mem_region(res_mem0->start, size0, "sa11x0-mcp")) | ||
150 | return -EBUSY; | 189 | return -EBUSY; |
151 | 190 | ||
191 | if (!request_mem_region(res_mem1->start, size1, "sa11x0-mcp")) { | ||
192 | ret = -EBUSY; | ||
193 | goto release; | ||
194 | } | ||
195 | |||
152 | mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0)); | 196 | mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0)); |
153 | if (!mcp) { | 197 | if (!mcp) { |
154 | ret = -ENOMEM; | 198 | ret = -ENOMEM; |
155 | goto release; | 199 | goto release2; |
156 | } | 200 | } |
157 | 201 | ||
202 | priv = priv(mcp); | ||
203 | |||
158 | mcp->owner = THIS_MODULE; | 204 | mcp->owner = THIS_MODULE; |
159 | mcp->ops = &mcp_sa11x0; | 205 | mcp->ops = &mcp_sa11x0; |
160 | mcp->sclk_rate = data->sclk_rate; | 206 | mcp->sclk_rate = data->sclk_rate; |
161 | mcp->dma_audio_rd = DMA_Ser4MCP0Rd; | 207 | mcp->dma_audio_rd = DDAR_DevAdd(res_mem0->start + MCDR0) |
162 | mcp->dma_audio_wr = DMA_Ser4MCP0Wr; | 208 | + DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev; |
163 | mcp->dma_telco_rd = DMA_Ser4MCP1Rd; | 209 | mcp->dma_audio_wr = DDAR_DevAdd(res_mem0->start + MCDR0) |
164 | mcp->dma_telco_wr = DMA_Ser4MCP1Wr; | 210 | + DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev; |
165 | mcp->gpio_base = data->gpio_base; | 211 | mcp->dma_telco_rd = DDAR_DevAdd(res_mem0->start + MCDR1) |
212 | + DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev; | ||
213 | mcp->dma_telco_wr = DDAR_DevAdd(res_mem0->start + MCDR1) | ||
214 | + DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev; | ||
215 | mcp->codec = data->codec; | ||
166 | 216 | ||
167 | platform_set_drvdata(pdev, mcp); | 217 | platform_set_drvdata(pdev, mcp); |
168 | 218 | ||
169 | if (machine_is_assabet()) { | ||
170 | ASSABET_BCR_set(ASSABET_BCR_CODEC_RST); | ||
171 | } | ||
172 | |||
173 | /* | ||
174 | * Setup the PPC unit correctly. | ||
175 | */ | ||
176 | PPDR &= ~PPC_RXD4; | ||
177 | PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM; | ||
178 | PSDR |= PPC_RXD4; | ||
179 | PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
180 | PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM); | ||
181 | |||
182 | /* | 219 | /* |
183 | * Initialise device. Note that we initially | 220 | * Initialise device. Note that we initially |
184 | * set the sampling rate to minimum. | 221 | * set the sampling rate to minimum. |
185 | */ | 222 | */ |
186 | Ser4MCSR = -1; | 223 | priv->mccr0_base = ioremap(res_mem0->start, size0); |
187 | Ser4MCCR1 = data->mccr1; | 224 | priv->mccr1_base = ioremap(res_mem1->start, size1); |
188 | Ser4MCCR0 = data->mccr0 | 0x7f7f; | 225 | |
226 | __raw_writel(-1, priv->mccr0_base + MCSR); | ||
227 | priv->mccr1 = data->mccr1; | ||
228 | priv->mccr0 = data->mccr0 | 0x7f7f; | ||
229 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); | ||
230 | __raw_writel(priv->mccr1, priv->mccr1_base + MCCR1); | ||
189 | 231 | ||
190 | /* | 232 | /* |
191 | * Calculate the read/write timeout (us) from the bit clock | 233 | * Calculate the read/write timeout (us) from the bit clock |
@@ -195,36 +237,53 @@ static int mcp_sa11x0_probe(struct platform_device *pdev) | |||
195 | mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) / | 237 | mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) / |
196 | mcp->sclk_rate; | 238 | mcp->sclk_rate; |
197 | 239 | ||
198 | ret = mcp_host_register(mcp); | 240 | ret = mcp_host_register(mcp, data->codec_pdata); |
199 | if (ret == 0) | 241 | if (ret == 0) |
200 | goto out; | 242 | goto out; |
201 | 243 | ||
244 | release2: | ||
245 | release_mem_region(res_mem1->start, size1); | ||
202 | release: | 246 | release: |
203 | release_mem_region(0x80060000, 0x60); | 247 | release_mem_region(res_mem0->start, size0); |
204 | platform_set_drvdata(pdev, NULL); | 248 | platform_set_drvdata(pdev, NULL); |
205 | 249 | ||
206 | out: | 250 | out: |
207 | return ret; | 251 | return ret; |
208 | } | 252 | } |
209 | 253 | ||
210 | static int mcp_sa11x0_remove(struct platform_device *dev) | 254 | static int mcp_sa11x0_remove(struct platform_device *pdev) |
211 | { | 255 | { |
212 | struct mcp *mcp = platform_get_drvdata(dev); | 256 | struct mcp *mcp = platform_get_drvdata(pdev); |
257 | struct mcp_sa11x0 *priv = priv(mcp); | ||
258 | struct resource *res_mem; | ||
259 | u32 size; | ||
213 | 260 | ||
214 | platform_set_drvdata(dev, NULL); | 261 | platform_set_drvdata(pdev, NULL); |
215 | mcp_host_unregister(mcp); | 262 | mcp_host_unregister(mcp); |
216 | release_mem_region(0x80060000, 0x60); | ||
217 | 263 | ||
264 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
265 | if (res_mem) { | ||
266 | size = res_mem->end - res_mem->start + 1; | ||
267 | release_mem_region(res_mem->start, size); | ||
268 | } | ||
269 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
270 | if (res_mem) { | ||
271 | size = res_mem->end - res_mem->start + 1; | ||
272 | release_mem_region(res_mem->start, size); | ||
273 | } | ||
274 | iounmap(priv->mccr0_base); | ||
275 | iounmap(priv->mccr1_base); | ||
218 | return 0; | 276 | return 0; |
219 | } | 277 | } |
220 | 278 | ||
221 | static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state) | 279 | static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state) |
222 | { | 280 | { |
223 | struct mcp *mcp = platform_get_drvdata(dev); | 281 | struct mcp *mcp = platform_get_drvdata(dev); |
282 | struct mcp_sa11x0 *priv = priv(mcp); | ||
283 | u32 mccr0; | ||
224 | 284 | ||
225 | priv(mcp)->mccr0 = Ser4MCCR0; | 285 | mccr0 = priv->mccr0 & ~MCCR0_MCE; |
226 | priv(mcp)->mccr1 = Ser4MCCR1; | 286 | __raw_writel(mccr0, priv->mccr0_base + MCCR0); |
227 | Ser4MCCR0 &= ~MCCR0_MCE; | ||
228 | 287 | ||
229 | return 0; | 288 | return 0; |
230 | } | 289 | } |
@@ -232,9 +291,10 @@ static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state) | |||
232 | static int mcp_sa11x0_resume(struct platform_device *dev) | 291 | static int mcp_sa11x0_resume(struct platform_device *dev) |
233 | { | 292 | { |
234 | struct mcp *mcp = platform_get_drvdata(dev); | 293 | struct mcp *mcp = platform_get_drvdata(dev); |
294 | struct mcp_sa11x0 *priv = priv(mcp); | ||
235 | 295 | ||
236 | Ser4MCCR1 = priv(mcp)->mccr1; | 296 | __raw_writel(priv->mccr0, priv->mccr0_base + MCCR0); |
237 | Ser4MCCR0 = priv(mcp)->mccr0; | 297 | __raw_writel(priv->mccr1, priv->mccr1_base + MCCR1); |
238 | 298 | ||
239 | return 0; | 299 | return 0; |
240 | } | 300 | } |
@@ -251,24 +311,14 @@ static struct platform_driver mcp_sa11x0_driver = { | |||
251 | .resume = mcp_sa11x0_resume, | 311 | .resume = mcp_sa11x0_resume, |
252 | .driver = { | 312 | .driver = { |
253 | .name = "sa11x0-mcp", | 313 | .name = "sa11x0-mcp", |
314 | .owner = THIS_MODULE, | ||
254 | }, | 315 | }, |
255 | }; | 316 | }; |
256 | 317 | ||
257 | /* | 318 | /* |
258 | * This needs re-working | 319 | * This needs re-working |
259 | */ | 320 | */ |
260 | static int __init mcp_sa11x0_init(void) | 321 | module_platform_driver(mcp_sa11x0_driver); |
261 | { | ||
262 | return platform_driver_register(&mcp_sa11x0_driver); | ||
263 | } | ||
264 | |||
265 | static void __exit mcp_sa11x0_exit(void) | ||
266 | { | ||
267 | platform_driver_unregister(&mcp_sa11x0_driver); | ||
268 | } | ||
269 | |||
270 | module_init(mcp_sa11x0_init); | ||
271 | module_exit(mcp_sa11x0_exit); | ||
272 | 322 | ||
273 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | 323 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
274 | MODULE_DESCRIPTION("SA11x0 multimedia communications port driver"); | 324 | MODULE_DESCRIPTION("SA11x0 multimedia communications port driver"); |