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-rw-r--r--drivers/media/video/gspca/m5602/m5602_mt9m111.h2
-rw-r--r--drivers/media/video/gspca/m5602/m5602_ov9650.h17
2 files changed, 10 insertions, 9 deletions
diff --git a/drivers/media/video/gspca/m5602/m5602_mt9m111.h b/drivers/media/video/gspca/m5602/m5602_mt9m111.h
index c5f75aa59f54..e795ab7a36c9 100644
--- a/drivers/media/video/gspca/m5602/m5602_mt9m111.h
+++ b/drivers/media/video/gspca/m5602/m5602_mt9m111.h
@@ -993,7 +993,7 @@ static const unsigned char init_mt9m111[][4] =
993 {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00}, 993 {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
994 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00}, 994 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
995 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00}, 995 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
996 {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00}, 996 {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00}, /* 639*/
997 {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00}, 997 {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00},
998 {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00}, 998 {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
999 {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00}, 999 {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
diff --git a/drivers/media/video/gspca/m5602/m5602_ov9650.h b/drivers/media/video/gspca/m5602/m5602_ov9650.h
index 3435a05aba7d..b1aec70db959 100644
--- a/drivers/media/video/gspca/m5602/m5602_ov9650.h
+++ b/drivers/media/video/gspca/m5602/m5602_ov9650.h
@@ -344,7 +344,7 @@ static const unsigned char init_ov9650[][3] =
344 {SENSOR, OV9650_COM24, 0x00}, 344 {SENSOR, OV9650_COM24, 0x00},
345 /* Enable HREF and some out of spec things */ 345 /* Enable HREF and some out of spec things */
346 {SENSOR, OV9650_COM12, 0x73}, 346 {SENSOR, OV9650_COM12, 0x73},
347 /* Set all DBLC offset signs to positive and 347 /* Set all DBLC offset signs to positive and
348 do some out of spec stuff */ 348 do some out of spec stuff */
349 {SENSOR, OV9650_DBLC1, 0xdf}, 349 {SENSOR, OV9650_DBLC1, 0xdf},
350 {SENSOR, OV9650_COM21, 0x06}, 350 {SENSOR, OV9650_COM21, 0x06},
@@ -356,7 +356,7 @@ static const unsigned char init_ov9650[][3] =
356 {SENSOR, OV9650_RSVD96, 0x04}, 356 {SENSOR, OV9650_RSVD96, 0x04},
357 /* Enable full range output */ 357 /* Enable full range output */
358 {SENSOR, OV9650_COM15, 0x0}, 358 {SENSOR, OV9650_COM15, 0x0},
359 /* Enable HREF at optical black, enable ADBLC bias, 359 /* Enable HREF at optical black, enable ADBLC bias,
360 enable ADBLC, reset timings at format change */ 360 enable ADBLC, reset timings at format change */
361 {SENSOR, OV9650_COM6, 0x4b}, 361 {SENSOR, OV9650_COM6, 0x4b},
362 /* Subtract 32 from the B channel bias */ 362 /* Subtract 32 from the B channel bias */
@@ -377,7 +377,7 @@ static const unsigned char init_ov9650[][3] =
377 {SENSOR, OV9650_AEB, 0x5c}, 377 {SENSOR, OV9650_AEB, 0x5c},
378 /* Set the high and low limit nibbles to 3 */ 378 /* Set the high and low limit nibbles to 3 */
379 {SENSOR, OV9650_VPT, 0xc3}, 379 {SENSOR, OV9650_VPT, 0xc3},
380 /* Set the Automatic Gain Ceiling (AGC) to 128x, 380 /* Set the Automatic Gain Ceiling (AGC) to 128x,
381 drop VSYNC at frame drop, 381 drop VSYNC at frame drop,
382 limit exposure timing, 382 limit exposure timing,
383 drop frame when the AEC step is larger than the exposure gap */ 383 drop frame when the AEC step is larger than the exposure gap */
@@ -386,9 +386,9 @@ static const unsigned char init_ov9650[][3] =
386 and set PWDN to SLVS (slave mode vertical sync) */ 386 and set PWDN to SLVS (slave mode vertical sync) */
387 {SENSOR, OV9650_COM10, 0x42}, 387 {SENSOR, OV9650_COM10, 0x42},
388 /* Set horizontal column start high to default value */ 388 /* Set horizontal column start high to default value */
389 {SENSOR, OV9650_HSTART, 0x1a}, 389 {SENSOR, OV9650_HSTART, 0x1a}, /* 210 */
390 /* Set horizontal column end */ 390 /* Set horizontal column end */
391 {SENSOR, OV9650_HSTOP, 0xbf}, 391 {SENSOR, OV9650_HSTOP, 0xbf}, /* 1534 */
392 /* Complementing register to the two writes above */ 392 /* Complementing register to the two writes above */
393 {SENSOR, OV9650_HREF, 0xb2}, 393 {SENSOR, OV9650_HREF, 0xb2},
394 /* Set vertical row start high bits */ 394 /* Set vertical row start high bits */
@@ -428,11 +428,12 @@ static const unsigned char init_ov9650[][3] =
428 {BRIDGE, M5602_XB_VSYNC_PARA, 0x09}, 428 {BRIDGE, M5602_XB_VSYNC_PARA, 0x09},
429 {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, 429 {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
430 {BRIDGE, M5602_XB_VSYNC_PARA, 0x01}, 430 {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
431 {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, 431 {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, /* 480 */
432 {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
432 {BRIDGE, M5602_XB_VSYNC_PARA, 0x00}, 433 {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
433 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00}, 434 {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
434 {BRIDGE, M5602_XB_HSYNC_PARA, 0x5e}, 435 {BRIDGE, M5602_XB_HSYNC_PARA, 0x5e}, /* 94 */
435 {BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, 436 {BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, /* 734 */
436 {BRIDGE, M5602_XB_HSYNC_PARA, 0xde} 437 {BRIDGE, M5602_XB_HSYNC_PARA, 0xde}
437}; 438};
438 439