diff options
Diffstat (limited to 'drivers/media/video')
-rw-r--r-- | drivers/media/video/cx88/cx88-alsa.c | 42 | ||||
-rw-r--r-- | drivers/media/video/cx88/cx88-reg.h | 13 |
2 files changed, 33 insertions, 22 deletions
diff --git a/drivers/media/video/cx88/cx88-alsa.c b/drivers/media/video/cx88/cx88-alsa.c index 76a8c01208c1..ecb9a74ae03d 100644 --- a/drivers/media/video/cx88/cx88-alsa.c +++ b/drivers/media/video/cx88/cx88-alsa.c | |||
@@ -136,12 +136,11 @@ static int _cx88_start_audio_dma(snd_cx88_card_t *chip) | |||
136 | struct cx88_core *core=chip->core; | 136 | struct cx88_core *core=chip->core; |
137 | struct sram_channel *audio_ch = &cx88_sram_channels[SRAM_CH25]; | 137 | struct sram_channel *audio_ch = &cx88_sram_channels[SRAM_CH25]; |
138 | 138 | ||
139 | 139 | /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ | |
140 | dprintk(1, "Starting audio DMA for %i bytes/line and %i (%i) lines at address %08x\n",buf->bpl, chip->num_periods, audio_ch->fifo_size / buf->bpl, audio_ch->fifo_start); | 140 | cx_clear(MO_AUD_DMACNTRL, 0x11); |
141 | 141 | ||
142 | /* setup fifo + format - out channel */ | 142 | /* setup fifo + format - out channel */ |
143 | cx88_sram_channel_setup(chip->core, &cx88_sram_channels[SRAM_CH25], | 143 | cx88_sram_channel_setup(chip->core, audio_ch, buf->bpl, buf->risc.dma); |
144 | buf->bpl, buf->risc.dma); | ||
145 | 144 | ||
146 | /* sets bpl size */ | 145 | /* sets bpl size */ |
147 | cx_write(MO_AUDD_LNGTH, buf->bpl); | 146 | cx_write(MO_AUDD_LNGTH, buf->bpl); |
@@ -149,27 +148,30 @@ static int _cx88_start_audio_dma(snd_cx88_card_t *chip) | |||
149 | /* reset counter */ | 148 | /* reset counter */ |
150 | cx_write(MO_AUDD_GPCNTRL,GP_COUNT_CONTROL_RESET); | 149 | cx_write(MO_AUDD_GPCNTRL,GP_COUNT_CONTROL_RESET); |
151 | 150 | ||
151 | dprintk(1, "Start audio DMA, %d B/line, %d lines/FIFO, %d lines/irq, " | ||
152 | "%d B/irq\n", buf->bpl, cx_read(audio_ch->cmds_start + 8)>>1, | ||
153 | chip->num_periods, buf->bpl * chip->num_periods); | ||
154 | |||
152 | dprintk(1, "Enabling IRQ, setting mask from 0x%x to 0x%x\n", | 155 | dprintk(1, "Enabling IRQ, setting mask from 0x%x to 0x%x\n", |
153 | chip->core->pci_irqmask, | 156 | chip->core->pci_irqmask, |
154 | chip->core->pci_irqmask | PCI_INT_AUDINT); | 157 | chip->core->pci_irqmask | PCI_INT_AUDINT); |
155 | /* enable irqs */ | ||
156 | cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT); | ||
157 | |||
158 | 158 | ||
159 | /* Enables corresponding bits at AUD_INT_STAT */ | 159 | /* Enables corresponding bits at AUD_INT_STAT */ |
160 | cx_write(MO_AUD_INTMSK, | 160 | cx_write(MO_AUD_INTMSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | |
161 | (1<<16)| | 161 | AUD_INT_DN_RISCI2 | AUD_INT_DN_RISCI1); |
162 | (1<<12)| | 162 | |
163 | (1<<4)| | 163 | /* Clean any pending interrupt bits already set */ |
164 | (1<<0) | 164 | cx_write(MO_AUD_INTSTAT, ~0); |
165 | ); | 165 | |
166 | /* enable audio irqs */ | ||
167 | cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT); | ||
166 | 168 | ||
167 | /* start dma */ | 169 | /* start dma */ |
168 | cx_set(MO_DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ | 170 | cx_set(MO_DEV_CNTRL2, (1<<5)); /* Enables Risc Processor */ |
169 | cx_set(MO_AUD_DMACNTRL, 0x11); /* audio downstream FIFO and RISC enable */ | 171 | cx_set(MO_AUD_DMACNTRL, 0x11); /* audio downstream FIFO and RISC enable */ |
170 | 172 | ||
171 | if (debug) | 173 | if (debug) |
172 | cx88_sram_channel_dump(chip->core, &cx88_sram_channels[SRAM_CH25]); | 174 | cx88_sram_channel_dump(chip->core, audio_ch); |
173 | 175 | ||
174 | return 0; | 176 | return 0; |
175 | } | 177 | } |
@@ -187,12 +189,8 @@ static int _cx88_stop_audio_dma(snd_cx88_card_t *chip) | |||
187 | 189 | ||
188 | /* disable irqs */ | 190 | /* disable irqs */ |
189 | cx_clear(MO_PCI_INTMSK, PCI_INT_AUDINT); | 191 | cx_clear(MO_PCI_INTMSK, PCI_INT_AUDINT); |
190 | cx_clear(MO_AUD_INTMSK, | 192 | cx_clear(MO_AUD_INTMSK, AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | |
191 | (1<<16)| | 193 | AUD_INT_DN_RISCI2 | AUD_INT_DN_RISCI1); |
192 | (1<<12)| | ||
193 | (1<<4)| | ||
194 | (1<<0) | ||
195 | ); | ||
196 | 194 | ||
197 | if (debug) | 195 | if (debug) |
198 | cx88_sram_channel_dump(chip->core, &cx88_sram_channels[SRAM_CH25]); | 196 | cx88_sram_channel_dump(chip->core, &cx88_sram_channels[SRAM_CH25]); |
@@ -239,14 +237,14 @@ static void cx8801_aud_irq(snd_cx88_card_t *chip) | |||
239 | cx88_aud_irqs, ARRAY_SIZE(cx88_aud_irqs), | 237 | cx88_aud_irqs, ARRAY_SIZE(cx88_aud_irqs), |
240 | status, mask); | 238 | status, mask); |
241 | /* risc op code error */ | 239 | /* risc op code error */ |
242 | if (status & (1 << 16)) { | 240 | if (status & AUD_INT_OPC_ERR) { |
243 | printk(KERN_WARNING "%s/0: audio risc op code error\n",core->name); | 241 | printk(KERN_WARNING "%s/0: audio risc op code error\n",core->name); |
244 | cx_clear(MO_AUD_DMACNTRL, 0x11); | 242 | cx_clear(MO_AUD_DMACNTRL, 0x11); |
245 | cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH25]); | 243 | cx88_sram_channel_dump(core, &cx88_sram_channels[SRAM_CH25]); |
246 | } | 244 | } |
247 | 245 | ||
248 | /* risc1 downstream */ | 246 | /* risc1 downstream */ |
249 | if (status & 0x01) { | 247 | if (status & AUD_INT_DN_RISCI1) { |
250 | spin_lock(&chip->reg_lock); | 248 | spin_lock(&chip->reg_lock); |
251 | count = cx_read(MO_AUDD_GPCNT); | 249 | count = cx_read(MO_AUDD_GPCNT); |
252 | spin_unlock(&chip->reg_lock); | 250 | spin_unlock(&chip->reg_lock); |
diff --git a/drivers/media/video/cx88/cx88-reg.h b/drivers/media/video/cx88/cx88-reg.h index 2b1d102cd220..2ec52d1cdea0 100644 --- a/drivers/media/video/cx88/cx88-reg.h +++ b/drivers/media/video/cx88/cx88-reg.h | |||
@@ -612,6 +612,19 @@ | |||
612 | #define SEL_FMRADIO 0x20 | 612 | #define SEL_FMRADIO 0x20 |
613 | 613 | ||
614 | // AUD_CTL | 614 | // AUD_CTL |
615 | #define AUD_INT_DN_RISCI1 (1 << 0) | ||
616 | #define AUD_INT_UP_RISCI1 (1 << 1) | ||
617 | #define AUD_INT_RDS_DN_RISCI1 (1 << 2) | ||
618 | #define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */ | ||
619 | #define AUD_INT_UP_RISCI2 (1 << 5) | ||
620 | #define AUD_INT_RDS_DN_RISCI2 (1 << 6) | ||
621 | #define AUD_INT_DN_SYNC (1 << 12) | ||
622 | #define AUD_INT_UP_SYNC (1 << 13) | ||
623 | #define AUD_INT_RDS_DN_SYNC (1 << 14) | ||
624 | #define AUD_INT_OPC_ERR (1 << 16) | ||
625 | #define AUD_INT_BER_IRQ (1 << 20) | ||
626 | #define AUD_INT_MCHG_IRQ (1 << 21) | ||
627 | |||
615 | #define EN_BTSC_FORCE_MONO 0 | 628 | #define EN_BTSC_FORCE_MONO 0 |
616 | #define EN_BTSC_FORCE_STEREO 1 | 629 | #define EN_BTSC_FORCE_STEREO 1 |
617 | #define EN_BTSC_FORCE_SAP 2 | 630 | #define EN_BTSC_FORCE_SAP 2 |