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-rw-r--r--drivers/media/video/sr030pc30.c894
1 files changed, 894 insertions, 0 deletions
diff --git a/drivers/media/video/sr030pc30.c b/drivers/media/video/sr030pc30.c
new file mode 100644
index 000000000000..c9dc67aba980
--- /dev/null
+++ b/drivers/media/video/sr030pc30.c
@@ -0,0 +1,894 @@
1/*
2 * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd
5 * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
6 *
7 * Based on original driver authored by Dongsoo Nathaniel Kim
8 * and HeungJun Kim <riverful.kim@samsung.com>.
9 *
10 * Based on mt9v011 Micron Digital Image Sensor driver
11 * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#include <linux/i2c.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-subdev.h>
24#include <media/v4l2-mediabus.h>
25#include <media/sr030pc30.h>
26
27static int debug;
28module_param(debug, int, 0644);
29
30#define MODULE_NAME "SR030PC30"
31
32/*
33 * Register offsets within a page
34 * b15..b8 - page id, b7..b0 - register address
35 */
36#define POWER_CTRL_REG 0x0001
37#define PAGEMODE_REG 0x03
38#define DEVICE_ID_REG 0x0004
39#define NOON010PC30_ID 0x86
40#define SR030PC30_ID 0x8C
41#define VDO_CTL1_REG 0x0010
42#define SUBSAMPL_NONE_VGA 0
43#define SUBSAMPL_QVGA 0x10
44#define SUBSAMPL_QQVGA 0x20
45#define VDO_CTL2_REG 0x0011
46#define SYNC_CTL_REG 0x0012
47#define WIN_ROWH_REG 0x0020
48#define WIN_ROWL_REG 0x0021
49#define WIN_COLH_REG 0x0022
50#define WIN_COLL_REG 0x0023
51#define WIN_HEIGHTH_REG 0x0024
52#define WIN_HEIGHTL_REG 0x0025
53#define WIN_WIDTHH_REG 0x0026
54#define WIN_WIDTHL_REG 0x0027
55#define HBLANKH_REG 0x0040
56#define HBLANKL_REG 0x0041
57#define VSYNCH_REG 0x0042
58#define VSYNCL_REG 0x0043
59/* page 10 */
60#define ISP_CTL_REG(n) (0x1010 + (n))
61#define YOFS_REG 0x1040
62#define DARK_YOFS_REG 0x1041
63#define AG_ABRTH_REG 0x1050
64#define SAT_CTL_REG 0x1060
65#define BSAT_REG 0x1061
66#define RSAT_REG 0x1062
67#define AG_SAT_TH_REG 0x1063
68/* page 11 */
69#define ZLPF_CTRL_REG 0x1110
70#define ZLPF_CTRL2_REG 0x1112
71#define ZLPF_AGH_THR_REG 0x1121
72#define ZLPF_THR_REG 0x1160
73#define ZLPF_DYN_THR_REG 0x1160
74/* page 12 */
75#define YCLPF_CTL1_REG 0x1240
76#define YCLPF_CTL2_REG 0x1241
77#define YCLPF_THR_REG 0x1250
78#define BLPF_CTL_REG 0x1270
79#define BLPF_THR1_REG 0x1274
80#define BLPF_THR2_REG 0x1275
81/* page 14 - Lens Shading Compensation */
82#define LENS_CTRL_REG 0x1410
83#define LENS_XCEN_REG 0x1420
84#define LENS_YCEN_REG 0x1421
85#define LENS_R_COMP_REG 0x1422
86#define LENS_G_COMP_REG 0x1423
87#define LENS_B_COMP_REG 0x1424
88/* page 15 - Color correction */
89#define CMC_CTL_REG 0x1510
90#define CMC_OFSGH_REG 0x1514
91#define CMC_OFSGL_REG 0x1516
92#define CMC_SIGN_REG 0x1517
93/* Color correction coefficients */
94#define CMC_COEF_REG(n) (0x1530 + (n))
95/* Color correction offset coefficients */
96#define CMC_OFS_REG(n) (0x1540 + (n))
97/* page 16 - Gamma correction */
98#define GMA_CTL_REG 0x1610
99/* Gamma correction coefficients 0.14 */
100#define GMA_COEF_REG(n) (0x1630 + (n))
101/* page 20 - Auto Exposure */
102#define AE_CTL1_REG 0x2010
103#define AE_CTL2_REG 0x2011
104#define AE_FRM_CTL_REG 0x2020
105#define AE_FINE_CTL_REG(n) (0x2028 + (n))
106#define EXP_TIMEH_REG 0x2083
107#define EXP_TIMEM_REG 0x2084
108#define EXP_TIMEL_REG 0x2085
109#define EXP_MMINH_REG 0x2086
110#define EXP_MMINL_REG 0x2087
111#define EXP_MMAXH_REG 0x2088
112#define EXP_MMAXM_REG 0x2089
113#define EXP_MMAXL_REG 0x208A
114/* page 22 - Auto White Balance */
115#define AWB_CTL1_REG 0x2210
116#define AWB_ENABLE 0x80
117#define AWB_CTL2_REG 0x2211
118#define MWB_ENABLE 0x01
119/* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
120#define AWB_RGAIN_REG 0x2280
121#define AWB_GGAIN_REG 0x2281
122#define AWB_BGAIN_REG 0x2282
123#define AWB_RMAX_REG 0x2283
124#define AWB_RMIN_REG 0x2284
125#define AWB_BMAX_REG 0x2285
126#define AWB_BMIN_REG 0x2286
127/* R, B gain range in bright light conditions */
128#define AWB_RMAXB_REG 0x2287
129#define AWB_RMINB_REG 0x2288
130#define AWB_BMAXB_REG 0x2289
131#define AWB_BMINB_REG 0x228A
132/* manual white balance, when AWB_CTL2[0]=1 */
133#define MWB_RGAIN_REG 0x22B2
134#define MWB_BGAIN_REG 0x22B3
135/* the token to mark an array end */
136#define REG_TERM 0xFFFF
137
138/* Minimum and maximum exposure time in ms */
139#define EXPOS_MIN_MS 1
140#define EXPOS_MAX_MS 125
141
142struct sr030pc30_info {
143 struct v4l2_subdev sd;
144 const struct sr030pc30_platform_data *pdata;
145 const struct sr030pc30_format *curr_fmt;
146 const struct sr030pc30_frmsize *curr_win;
147 unsigned int auto_wb:1;
148 unsigned int auto_exp:1;
149 unsigned int hflip:1;
150 unsigned int vflip:1;
151 unsigned int sleep:1;
152 unsigned int exposure;
153 u8 blue_balance;
154 u8 red_balance;
155 u8 i2c_reg_page;
156};
157
158struct sr030pc30_format {
159 enum v4l2_mbus_pixelcode code;
160 enum v4l2_colorspace colorspace;
161 u16 ispctl1_reg;
162};
163
164struct sr030pc30_frmsize {
165 u16 width;
166 u16 height;
167 int vid_ctl1;
168};
169
170struct i2c_regval {
171 u16 addr;
172 u16 val;
173};
174
175static const struct v4l2_queryctrl sr030pc30_ctrl[] = {
176 {
177 .id = V4L2_CID_AUTO_WHITE_BALANCE,
178 .type = V4L2_CTRL_TYPE_BOOLEAN,
179 .name = "Auto White Balance",
180 .minimum = 0,
181 .maximum = 1,
182 .step = 1,
183 .default_value = 1,
184 }, {
185 .id = V4L2_CID_RED_BALANCE,
186 .type = V4L2_CTRL_TYPE_INTEGER,
187 .name = "Red Balance",
188 .minimum = 0,
189 .maximum = 127,
190 .step = 1,
191 .default_value = 64,
192 .flags = 0,
193 }, {
194 .id = V4L2_CID_BLUE_BALANCE,
195 .type = V4L2_CTRL_TYPE_INTEGER,
196 .name = "Blue Balance",
197 .minimum = 0,
198 .maximum = 127,
199 .step = 1,
200 .default_value = 64,
201 }, {
202 .id = V4L2_CID_EXPOSURE_AUTO,
203 .type = V4L2_CTRL_TYPE_INTEGER,
204 .name = "Auto Exposure",
205 .minimum = 0,
206 .maximum = 1,
207 .step = 1,
208 .default_value = 1,
209 }, {
210 .id = V4L2_CID_EXPOSURE,
211 .type = V4L2_CTRL_TYPE_INTEGER,
212 .name = "Exposure",
213 .minimum = EXPOS_MIN_MS,
214 .maximum = EXPOS_MAX_MS,
215 .step = 1,
216 .default_value = 1,
217 }, {
218 }
219};
220
221/* supported resolutions */
222static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
223 {
224 .width = 640,
225 .height = 480,
226 .vid_ctl1 = SUBSAMPL_NONE_VGA,
227 }, {
228 .width = 320,
229 .height = 240,
230 .vid_ctl1 = SUBSAMPL_QVGA,
231 }, {
232 .width = 160,
233 .height = 120,
234 .vid_ctl1 = SUBSAMPL_QQVGA,
235 },
236};
237
238/* supported pixel formats */
239static const struct sr030pc30_format sr030pc30_formats[] = {
240 {
241 .code = V4L2_MBUS_FMT_YUYV8_2X8,
242 .colorspace = V4L2_COLORSPACE_JPEG,
243 .ispctl1_reg = 0x03,
244 }, {
245 .code = V4L2_MBUS_FMT_YVYU8_2X8,
246 .colorspace = V4L2_COLORSPACE_JPEG,
247 .ispctl1_reg = 0x02,
248 }, {
249 .code = V4L2_MBUS_FMT_VYUY8_2X8,
250 .colorspace = V4L2_COLORSPACE_JPEG,
251 .ispctl1_reg = 0,
252 }, {
253 .code = V4L2_MBUS_FMT_UYVY8_2X8,
254 .colorspace = V4L2_COLORSPACE_JPEG,
255 .ispctl1_reg = 0x01,
256 }, {
257 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
258 .colorspace = V4L2_COLORSPACE_JPEG,
259 .ispctl1_reg = 0x40,
260 },
261};
262
263static const struct i2c_regval sr030pc30_base_regs[] = {
264 /* Window size and position within pixel matrix */
265 { WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
266 { WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
267 { WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
268 { WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
269 { HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
270 { VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
271 { SYNC_CTL_REG, 0 },
272 /* Color corection and saturation */
273 { ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
274 { DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
275 { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
276 { AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
277 { CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
278 { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
279 { CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
280 { CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
281 { CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
282 { CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
283 { CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
284 { CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
285 { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
286 { CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
287 { CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
288 /* Color corection coefficients */
289 { GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
290 { GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
291 { GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
292 { GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
293 { GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
294 { GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
295 { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
296 { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
297 /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
298 { ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
299 { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
300 { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
301 { YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
302 { BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
303 { BLPF_THR2_REG, 0x04 },
304 /* Automatic white balance */
305 { AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
306 { AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
307 { AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
308 { AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
309 { AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
310 /* Auto exposure */
311 { AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
312 { AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
313 { AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
314 /* Lens shading compensation */
315 { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
316 { LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
317 { LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
318 { REG_TERM, 0 },
319};
320
321static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
322{
323 return container_of(sd, struct sr030pc30_info, sd);
324}
325
326static inline int set_i2c_page(struct sr030pc30_info *info,
327 struct i2c_client *client, unsigned int reg)
328{
329 int ret = 0;
330 u32 page = reg >> 8 & 0xFF;
331
332 if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
333 ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
334 if (!ret)
335 info->i2c_reg_page = page;
336 }
337 return ret;
338}
339
340static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
341{
342 struct i2c_client *client = v4l2_get_subdevdata(sd);
343 struct sr030pc30_info *info = to_sr030pc30(sd);
344
345 int ret = set_i2c_page(info, client, reg_addr);
346 if (!ret)
347 ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
348 return ret;
349}
350
351static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
352{
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
354 struct sr030pc30_info *info = to_sr030pc30(sd);
355
356 int ret = set_i2c_page(info, client, reg_addr);
357 if (!ret)
358 ret = i2c_smbus_write_byte_data(
359 client, reg_addr & 0xFF, val);
360 return ret;
361}
362
363static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
364 const struct i2c_regval *msg)
365{
366 while (msg->addr != REG_TERM) {
367 int ret = cam_i2c_write(sd, msg->addr, msg->val);
368 if (ret)
369 return ret;
370 msg++;
371 }
372 return 0;
373}
374
375/* Device reset and sleep mode control */
376static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
377 bool reset, bool sleep)
378{
379 struct sr030pc30_info *info = to_sr030pc30(sd);
380 u8 reg = sleep ? 0xF1 : 0xF0;
381 int ret = 0;
382
383 if (reset)
384 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
385 if (!ret) {
386 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
387 if (!ret) {
388 info->sleep = sleep;
389 if (reset)
390 info->i2c_reg_page = -1;
391 }
392 }
393 return ret;
394}
395
396static inline int sr030pc30_enable_autoexposure(struct v4l2_subdev *sd, int on)
397{
398 struct sr030pc30_info *info = to_sr030pc30(sd);
399 /* auto anti-flicker is also enabled here */
400 int ret = cam_i2c_write(sd, AE_CTL1_REG, on ? 0xDC : 0x0C);
401 if (!ret)
402 info->auto_exp = on;
403 return ret;
404}
405
406static int sr030pc30_set_exposure(struct v4l2_subdev *sd, int value)
407{
408 struct sr030pc30_info *info = to_sr030pc30(sd);
409
410 unsigned long expos = value * info->pdata->clk_rate / (8 * 1000);
411
412 int ret = cam_i2c_write(sd, EXP_TIMEH_REG, expos >> 16 & 0xFF);
413 if (!ret)
414 ret = cam_i2c_write(sd, EXP_TIMEM_REG, expos >> 8 & 0xFF);
415 if (!ret)
416 ret = cam_i2c_write(sd, EXP_TIMEL_REG, expos & 0xFF);
417 if (!ret) { /* Turn off AE */
418 info->exposure = value;
419 ret = sr030pc30_enable_autoexposure(sd, 0);
420 }
421 return ret;
422}
423
424/* Automatic white balance control */
425static int sr030pc30_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
426{
427 struct sr030pc30_info *info = to_sr030pc30(sd);
428
429 int ret = cam_i2c_write(sd, AWB_CTL2_REG, on ? 0x2E : 0x2F);
430 if (!ret)
431 ret = cam_i2c_write(sd, AWB_CTL1_REG, on ? 0xFB : 0x7B);
432 if (!ret)
433 info->auto_wb = on;
434
435 return ret;
436}
437
438static int sr030pc30_set_flip(struct v4l2_subdev *sd)
439{
440 struct sr030pc30_info *info = to_sr030pc30(sd);
441
442 s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
443 if (reg < 0)
444 return reg;
445
446 reg &= 0x7C;
447 if (info->hflip)
448 reg |= 0x01;
449 if (info->vflip)
450 reg |= 0x02;
451 return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
452}
453
454/* Configure resolution, color format and image flip */
455static int sr030pc30_set_params(struct v4l2_subdev *sd)
456{
457 struct sr030pc30_info *info = to_sr030pc30(sd);
458 int ret;
459
460 if (!info->curr_win)
461 return -EINVAL;
462
463 /* Configure the resolution through subsampling */
464 ret = cam_i2c_write(sd, VDO_CTL1_REG,
465 info->curr_win->vid_ctl1);
466
467 if (!ret && info->curr_fmt)
468 ret = cam_i2c_write(sd, ISP_CTL_REG(0),
469 info->curr_fmt->ispctl1_reg);
470 if (!ret)
471 ret = sr030pc30_set_flip(sd);
472
473 return ret;
474}
475
476/* Find nearest matching image pixel size. */
477static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
478{
479 unsigned int min_err = ~0;
480 int i = ARRAY_SIZE(sr030pc30_sizes);
481 const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
482 *match = NULL;
483 while (i--) {
484 int err = abs(fsize->width - mf->width)
485 + abs(fsize->height - mf->height);
486 if (err < min_err) {
487 min_err = err;
488 match = fsize;
489 }
490 fsize++;
491 }
492 if (match) {
493 mf->width = match->width;
494 mf->height = match->height;
495 return 0;
496 }
497 return -EINVAL;
498}
499
500static int sr030pc30_queryctrl(struct v4l2_subdev *sd,
501 struct v4l2_queryctrl *qc)
502{
503 int i;
504
505 for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
506 if (qc->id == sr030pc30_ctrl[i].id) {
507 *qc = sr030pc30_ctrl[i];
508 v4l2_dbg(1, debug, sd, "%s id: %d\n",
509 __func__, qc->id);
510 return 0;
511 }
512
513 return -EINVAL;
514}
515
516static inline int sr030pc30_set_bluebalance(struct v4l2_subdev *sd, int value)
517{
518 int ret = cam_i2c_write(sd, MWB_BGAIN_REG, value);
519 if (!ret)
520 to_sr030pc30(sd)->blue_balance = value;
521 return ret;
522}
523
524static inline int sr030pc30_set_redbalance(struct v4l2_subdev *sd, int value)
525{
526 int ret = cam_i2c_write(sd, MWB_RGAIN_REG, value);
527 if (!ret)
528 to_sr030pc30(sd)->red_balance = value;
529 return ret;
530}
531
532static int sr030pc30_s_ctrl(struct v4l2_subdev *sd,
533 struct v4l2_control *ctrl)
534{
535 int i, ret = 0;
536
537 for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
538 if (ctrl->id == sr030pc30_ctrl[i].id)
539 break;
540
541 if (i == ARRAY_SIZE(sr030pc30_ctrl))
542 return -EINVAL;
543
544 if (ctrl->value < sr030pc30_ctrl[i].minimum ||
545 ctrl->value > sr030pc30_ctrl[i].maximum)
546 return -ERANGE;
547
548 v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
549 __func__, ctrl->id, ctrl->value);
550
551 switch (ctrl->id) {
552 case V4L2_CID_AUTO_WHITE_BALANCE:
553 sr030pc30_enable_autowhitebalance(sd, ctrl->value);
554 break;
555 case V4L2_CID_BLUE_BALANCE:
556 ret = sr030pc30_set_bluebalance(sd, ctrl->value);
557 break;
558 case V4L2_CID_RED_BALANCE:
559 ret = sr030pc30_set_redbalance(sd, ctrl->value);
560 break;
561 case V4L2_CID_EXPOSURE_AUTO:
562 sr030pc30_enable_autoexposure(sd,
563 ctrl->value == V4L2_EXPOSURE_AUTO);
564 break;
565 case V4L2_CID_EXPOSURE:
566 ret = sr030pc30_set_exposure(sd, ctrl->value);
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 return ret;
573}
574
575static int sr030pc30_g_ctrl(struct v4l2_subdev *sd,
576 struct v4l2_control *ctrl)
577{
578 struct sr030pc30_info *info = to_sr030pc30(sd);
579
580 v4l2_dbg(1, debug, sd, "%s: id: %d\n", __func__, ctrl->id);
581
582 switch (ctrl->id) {
583 case V4L2_CID_AUTO_WHITE_BALANCE:
584 ctrl->value = info->auto_wb;
585 break;
586 case V4L2_CID_BLUE_BALANCE:
587 ctrl->value = info->blue_balance;
588 break;
589 case V4L2_CID_RED_BALANCE:
590 ctrl->value = info->red_balance;
591 break;
592 case V4L2_CID_EXPOSURE_AUTO:
593 ctrl->value = info->auto_exp;
594 break;
595 case V4L2_CID_EXPOSURE:
596 ctrl->value = info->exposure;
597 break;
598 default:
599 return -EINVAL;
600 }
601 return 0;
602}
603
604static int sr030pc30_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
605 enum v4l2_mbus_pixelcode *code)
606{
607 if (!code || index >= ARRAY_SIZE(sr030pc30_formats))
608 return -EINVAL;
609
610 *code = sr030pc30_formats[index].code;
611 return 0;
612}
613
614static int sr030pc30_g_fmt(struct v4l2_subdev *sd,
615 struct v4l2_mbus_framefmt *mf)
616{
617 struct sr030pc30_info *info = to_sr030pc30(sd);
618 int ret;
619
620 if (!mf)
621 return -EINVAL;
622
623 if (!info->curr_win || !info->curr_fmt) {
624 ret = sr030pc30_set_params(sd);
625 if (ret)
626 return ret;
627 }
628
629 mf->width = info->curr_win->width;
630 mf->height = info->curr_win->height;
631 mf->code = info->curr_fmt->code;
632 mf->colorspace = info->curr_fmt->colorspace;
633 mf->field = V4L2_FIELD_NONE;
634
635 return 0;
636}
637
638/* Return nearest media bus frame format. */
639static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
640 struct v4l2_mbus_framefmt *mf)
641{
642 int i = ARRAY_SIZE(sr030pc30_formats);
643
644 sr030pc30_try_frame_size(mf);
645
646 while (i--)
647 if (mf->code == sr030pc30_formats[i].code)
648 break;
649
650 mf->code = sr030pc30_formats[i].code;
651
652 return &sr030pc30_formats[i];
653}
654
655/* Return nearest media bus frame format. */
656static int sr030pc30_try_fmt(struct v4l2_subdev *sd,
657 struct v4l2_mbus_framefmt *mf)
658{
659 if (!sd || !mf)
660 return -EINVAL;
661
662 try_fmt(sd, mf);
663 return 0;
664}
665
666static int sr030pc30_s_fmt(struct v4l2_subdev *sd,
667 struct v4l2_mbus_framefmt *mf)
668{
669 struct sr030pc30_info *info = to_sr030pc30(sd);
670
671 if (!sd || !mf)
672 return -EINVAL;
673
674 info->curr_fmt = try_fmt(sd, mf);
675
676 return sr030pc30_set_params(sd);
677}
678
679static int sr030pc30_base_config(struct v4l2_subdev *sd)
680{
681 struct sr030pc30_info *info = to_sr030pc30(sd);
682 int ret;
683 unsigned long expmin, expmax;
684
685 ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
686 if (!ret) {
687 info->curr_fmt = &sr030pc30_formats[0];
688 info->curr_win = &sr030pc30_sizes[0];
689 ret = sr030pc30_set_params(sd);
690 }
691 if (!ret)
692 ret = sr030pc30_pwr_ctrl(sd, false, false);
693
694 if (!ret && !info->pdata)
695 return ret;
696
697 expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
698 expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
699
700 v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
701 expmin, expmax);
702
703 /* Setting up manual exposure time range */
704 ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
705 if (!ret)
706 ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
707 if (!ret)
708 ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
709 if (!ret)
710 ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
711 if (!ret)
712 ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
713
714 return ret;
715}
716
717static int sr030pc30_s_config(struct v4l2_subdev *sd,
718 int irq, void *platform_data)
719{
720 struct sr030pc30_info *info = to_sr030pc30(sd);
721
722 info->pdata = platform_data;
723 return 0;
724}
725
726static int sr030pc30_s_stream(struct v4l2_subdev *sd, int enable)
727{
728 return 0;
729}
730
731static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
732{
733 struct i2c_client *client = v4l2_get_subdevdata(sd);
734 struct sr030pc30_info *info = to_sr030pc30(sd);
735 const struct sr030pc30_platform_data *pdata = info->pdata;
736 int ret;
737
738 if (WARN(pdata == NULL, "No platform data!"))
739 return -ENOMEM;
740
741 /*
742 * Put sensor into power sleep mode before switching off
743 * power and disabling MCLK.
744 */
745 if (!on)
746 sr030pc30_pwr_ctrl(sd, false, true);
747
748 /* set_power controls sensor's power and clock */
749 if (pdata->set_power) {
750 ret = pdata->set_power(&client->dev, on);
751 if (ret)
752 return ret;
753 }
754
755 if (on) {
756 ret = sr030pc30_base_config(sd);
757 } else {
758 info->curr_win = NULL;
759 info->curr_fmt = NULL;
760 }
761
762 return ret;
763}
764
765static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
766 .s_config = sr030pc30_s_config,
767 .s_power = sr030pc30_s_power,
768 .queryctrl = sr030pc30_queryctrl,
769 .s_ctrl = sr030pc30_s_ctrl,
770 .g_ctrl = sr030pc30_g_ctrl,
771};
772
773static const struct v4l2_subdev_video_ops sr030pc30_video_ops = {
774 .s_stream = sr030pc30_s_stream,
775 .g_mbus_fmt = sr030pc30_g_fmt,
776 .s_mbus_fmt = sr030pc30_s_fmt,
777 .try_mbus_fmt = sr030pc30_try_fmt,
778 .enum_mbus_fmt = sr030pc30_enum_fmt,
779};
780
781static const struct v4l2_subdev_ops sr030pc30_ops = {
782 .core = &sr030pc30_core_ops,
783 .video = &sr030pc30_video_ops,
784};
785
786/*
787 * Detect sensor type. Return 0 if SR030PC30 was detected
788 * or -ENODEV otherwise.
789 */
790static int sr030pc30_detect(struct i2c_client *client)
791{
792 const struct sr030pc30_platform_data *pdata
793 = client->dev.platform_data;
794 int ret;
795
796 /* Enable sensor's power and clock */
797 if (pdata->set_power) {
798 ret = pdata->set_power(&client->dev, 1);
799 if (ret)
800 return ret;
801 }
802
803 ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
804
805 if (pdata->set_power)
806 pdata->set_power(&client->dev, 0);
807
808 if (ret < 0) {
809 dev_err(&client->dev, "%s: I2C read failed\n", __func__);
810 return ret;
811 }
812
813 return ret == SR030PC30_ID ? 0 : -ENODEV;
814}
815
816
817static int sr030pc30_probe(struct i2c_client *client,
818 const struct i2c_device_id *id)
819{
820 struct sr030pc30_info *info;
821 struct v4l2_subdev *sd;
822 const struct sr030pc30_platform_data *pdata
823 = client->dev.platform_data;
824 int ret;
825
826 if (!pdata) {
827 dev_err(&client->dev, "No platform data!");
828 return -EIO;
829 }
830
831 ret = sr030pc30_detect(client);
832 if (ret)
833 return ret;
834
835 info = kzalloc(sizeof(*info), GFP_KERNEL);
836 if (!info)
837 return -ENOMEM;
838
839 sd = &info->sd;
840 strcpy(sd->name, MODULE_NAME);
841 info->pdata = client->dev.platform_data;
842
843 v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
844
845 info->i2c_reg_page = -1;
846 info->hflip = 1;
847 info->auto_exp = 1;
848 info->exposure = 30;
849
850 return 0;
851}
852
853static int sr030pc30_remove(struct i2c_client *client)
854{
855 struct v4l2_subdev *sd = i2c_get_clientdata(client);
856 struct sr030pc30_info *info = to_sr030pc30(sd);
857
858 v4l2_device_unregister_subdev(sd);
859 kfree(info);
860 return 0;
861}
862
863static const struct i2c_device_id sr030pc30_id[] = {
864 { MODULE_NAME, 0 },
865 { },
866};
867MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
868
869
870static struct i2c_driver sr030pc30_i2c_driver = {
871 .driver = {
872 .name = MODULE_NAME
873 },
874 .probe = sr030pc30_probe,
875 .remove = sr030pc30_remove,
876 .id_table = sr030pc30_id,
877};
878
879static int __init sr030pc30_init(void)
880{
881 return i2c_add_driver(&sr030pc30_i2c_driver);
882}
883
884static void __exit sr030pc30_exit(void)
885{
886 i2c_del_driver(&sr030pc30_i2c_driver);
887}
888
889module_init(sr030pc30_init);
890module_exit(sr030pc30_exit);
891
892MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
893MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
894MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 18:45:18 -0500