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-rw-r--r--drivers/media/video/s5p-fimc/Makefile3
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.c1586
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.h471
-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.c527
-rw-r--r--drivers/media/video/s5p-fimc/regs-fimc.h293
5 files changed, 2880 insertions, 0 deletions
diff --git a/drivers/media/video/s5p-fimc/Makefile b/drivers/media/video/s5p-fimc/Makefile
new file mode 100644
index 000000000000..0d9d54132ecc
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/Makefile
@@ -0,0 +1,3 @@
1
2obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) := s5p-fimc.o
3s5p-fimc-y := fimc-core.o fimc-reg.o
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
new file mode 100644
index 000000000000..b151c7be8a50
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -0,0 +1,1586 @@
1/*
2 * S5P camera interface (video postprocessor) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/version.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/bug.h>
20#include <linux/interrupt.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/list.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf-dma-contig.h>
29
30#include "fimc-core.h"
31
32static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
33
34static struct fimc_fmt fimc_formats[] = {
35 {
36 .name = "RGB565",
37 .fourcc = V4L2_PIX_FMT_RGB565X,
38 .depth = 16,
39 .color = S5P_FIMC_RGB565,
40 .buff_cnt = 1,
41 .planes_cnt = 1
42 }, {
43 .name = "BGR666",
44 .fourcc = V4L2_PIX_FMT_BGR666,
45 .depth = 32,
46 .color = S5P_FIMC_RGB666,
47 .buff_cnt = 1,
48 .planes_cnt = 1
49 }, {
50 .name = "XRGB-8-8-8-8, 24 bpp",
51 .fourcc = V4L2_PIX_FMT_RGB24,
52 .depth = 32,
53 .color = S5P_FIMC_RGB888,
54 .buff_cnt = 1,
55 .planes_cnt = 1
56 }, {
57 .name = "YUV 4:2:2 packed, YCbYCr",
58 .fourcc = V4L2_PIX_FMT_YUYV,
59 .depth = 16,
60 .color = S5P_FIMC_YCBYCR422,
61 .buff_cnt = 1,
62 .planes_cnt = 1
63 }, {
64 .name = "YUV 4:2:2 packed, CbYCrY",
65 .fourcc = V4L2_PIX_FMT_UYVY,
66 .depth = 16,
67 .color = S5P_FIMC_CBYCRY422,
68 .buff_cnt = 1,
69 .planes_cnt = 1
70 }, {
71 .name = "YUV 4:2:2 packed, CrYCbY",
72 .fourcc = V4L2_PIX_FMT_VYUY,
73 .depth = 16,
74 .color = S5P_FIMC_CRYCBY422,
75 .buff_cnt = 1,
76 .planes_cnt = 1
77 }, {
78 .name = "YUV 4:2:2 packed, YCrYCb",
79 .fourcc = V4L2_PIX_FMT_YVYU,
80 .depth = 16,
81 .color = S5P_FIMC_YCRYCB422,
82 .buff_cnt = 1,
83 .planes_cnt = 1
84 }, {
85 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
86 .fourcc = V4L2_PIX_FMT_YUV422P,
87 .depth = 12,
88 .color = S5P_FIMC_YCBCR422,
89 .buff_cnt = 1,
90 .planes_cnt = 3
91 }, {
92 .name = "YUV 4:2:2 planar, Y/CbCr",
93 .fourcc = V4L2_PIX_FMT_NV16,
94 .depth = 16,
95 .color = S5P_FIMC_YCBCR422,
96 .buff_cnt = 1,
97 .planes_cnt = 2
98 }, {
99 .name = "YUV 4:2:2 planar, Y/CrCb",
100 .fourcc = V4L2_PIX_FMT_NV61,
101 .depth = 16,
102 .color = S5P_FIMC_RGB565,
103 .buff_cnt = 1,
104 .planes_cnt = 2
105 }, {
106 .name = "YUV 4:2:0 planar, YCbCr",
107 .fourcc = V4L2_PIX_FMT_YUV420,
108 .depth = 12,
109 .color = S5P_FIMC_YCBCR420,
110 .buff_cnt = 1,
111 .planes_cnt = 3
112 }, {
113 .name = "YUV 4:2:0 planar, Y/CbCr",
114 .fourcc = V4L2_PIX_FMT_NV12,
115 .depth = 12,
116 .color = S5P_FIMC_YCBCR420,
117 .buff_cnt = 1,
118 .planes_cnt = 2
119 }
120 };
121
122static struct v4l2_queryctrl fimc_ctrls[] = {
123 {
124 .id = V4L2_CID_HFLIP,
125 .type = V4L2_CTRL_TYPE_BOOLEAN,
126 .name = "Horizontal flip",
127 .minimum = 0,
128 .maximum = 1,
129 .default_value = 0,
130 },
131 {
132 .id = V4L2_CID_VFLIP,
133 .type = V4L2_CTRL_TYPE_BOOLEAN,
134 .name = "Vertical flip",
135 .minimum = 0,
136 .maximum = 1,
137 .default_value = 0,
138 },
139 {
140 .id = V4L2_CID_ROTATE,
141 .type = V4L2_CTRL_TYPE_INTEGER,
142 .name = "Rotation (CCW)",
143 .minimum = 0,
144 .maximum = 270,
145 .step = 90,
146 .default_value = 0,
147 },
148};
149
150
151static struct v4l2_queryctrl *get_ctrl(int id)
152{
153 int i;
154
155 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
156 if (id == fimc_ctrls[i].id)
157 return &fimc_ctrls[i];
158 return NULL;
159}
160
161static int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
162{
163 if (r->width > f->width) {
164 if (f->width > (r->width * SCALER_MAX_HRATIO))
165 return -EINVAL;
166 } else {
167 if ((f->width * SCALER_MAX_HRATIO) < r->width)
168 return -EINVAL;
169 }
170
171 if (r->height > f->height) {
172 if (f->height > (r->height * SCALER_MAX_VRATIO))
173 return -EINVAL;
174 } else {
175 if ((f->height * SCALER_MAX_VRATIO) < r->height)
176 return -EINVAL;
177 }
178
179 return 0;
180}
181
182static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
183{
184 if (src >= tar * 64) {
185 return -EINVAL;
186 } else if (src >= tar * 32) {
187 *ratio = 32;
188 *shift = 5;
189 } else if (src >= tar * 16) {
190 *ratio = 16;
191 *shift = 4;
192 } else if (src >= tar * 8) {
193 *ratio = 8;
194 *shift = 3;
195 } else if (src >= tar * 4) {
196 *ratio = 4;
197 *shift = 2;
198 } else if (src >= tar * 2) {
199 *ratio = 2;
200 *shift = 1;
201 } else {
202 *ratio = 1;
203 *shift = 0;
204 }
205
206 return 0;
207}
208
209static int fimc_set_scaler_info(struct fimc_ctx *ctx)
210{
211 struct fimc_scaler *sc = &ctx->scaler;
212 struct fimc_frame *s_frame = &ctx->s_frame;
213 struct fimc_frame *d_frame = &ctx->d_frame;
214 int tx, ty, sx, sy;
215 int ret;
216
217 tx = d_frame->width;
218 ty = d_frame->height;
219 if (tx <= 0 || ty <= 0) {
220 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
221 "invalid target size: %d x %d", tx, ty);
222 return -EINVAL;
223 }
224
225 sx = s_frame->width;
226 sy = s_frame->height;
227 if (sx <= 0 || sy <= 0) {
228 err("invalid source size: %d x %d", sx, sy);
229 return -EINVAL;
230 }
231
232 sc->real_width = sx;
233 sc->real_height = sy;
234 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
235
236 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
237 if (ret)
238 return ret;
239
240 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
241 if (ret)
242 return ret;
243
244 sc->pre_dst_width = sx / sc->pre_hratio;
245 sc->pre_dst_height = sy / sc->pre_vratio;
246
247 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
248 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
249
250 sc->scaleup_h = (tx >= sx) ? 1 : 0;
251 sc->scaleup_v = (ty >= sy) ? 1 : 0;
252
253 /* check to see if input and output size/format differ */
254 if (s_frame->fmt->color == d_frame->fmt->color
255 && s_frame->width == d_frame->width
256 && s_frame->height == d_frame->height)
257 sc->copy_mode = 1;
258 else
259 sc->copy_mode = 0;
260
261 return 0;
262}
263
264
265static irqreturn_t fimc_isr(int irq, void *priv)
266{
267 struct fimc_vid_buffer *src_buf, *dst_buf;
268 struct fimc_dev *fimc = (struct fimc_dev *)priv;
269 struct fimc_ctx *ctx;
270
271 BUG_ON(!fimc);
272 fimc_hw_clear_irq(fimc);
273
274 spin_lock(&fimc->slock);
275
276 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
277 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
278 if (!ctx || !ctx->m2m_ctx)
279 goto isr_unlock;
280 src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
281 dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
282 if (src_buf && dst_buf) {
283 spin_lock(&fimc->irqlock);
284 src_buf->vb.state = dst_buf->vb.state = VIDEOBUF_DONE;
285 wake_up(&src_buf->vb.done);
286 wake_up(&dst_buf->vb.done);
287 spin_unlock(&fimc->irqlock);
288 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
289 }
290 }
291
292isr_unlock:
293 spin_unlock(&fimc->slock);
294 return IRQ_HANDLED;
295}
296
297/* The color format (planes_cnt, buff_cnt) must be already configured. */
298static int fimc_prepare_addr(struct fimc_ctx *ctx,
299 struct fimc_vid_buffer *buf, enum v4l2_buf_type type)
300{
301 struct fimc_frame *frame;
302 struct fimc_addr *paddr;
303 u32 pix_size;
304 int ret = 0;
305
306 frame = ctx_m2m_get_frame(ctx, type);
307 if (IS_ERR(frame))
308 return PTR_ERR(frame);
309 paddr = &frame->paddr;
310
311 if (!buf)
312 return -EINVAL;
313
314 pix_size = frame->width * frame->height;
315
316 dbg("buff_cnt= %d, planes_cnt= %d, frame->size= %d, pix_size= %d",
317 frame->fmt->buff_cnt, frame->fmt->planes_cnt,
318 frame->size, pix_size);
319
320 if (frame->fmt->buff_cnt == 1) {
321 paddr->y = videobuf_to_dma_contig(&buf->vb);
322 switch (frame->fmt->planes_cnt) {
323 case 1:
324 paddr->cb = 0;
325 paddr->cr = 0;
326 break;
327 case 2:
328 /* decompose Y into Y/Cb */
329 paddr->cb = (u32)(paddr->y + pix_size);
330 paddr->cr = 0;
331 break;
332 case 3:
333 paddr->cb = (u32)(paddr->y + pix_size);
334 /* decompose Y into Y/Cb/Cr */
335 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
336 paddr->cr = (u32)(paddr->cb
337 + (pix_size >> 2));
338 else /* 422 */
339 paddr->cr = (u32)(paddr->cb
340 + (pix_size >> 1));
341 break;
342 default:
343 return -EINVAL;
344 }
345 }
346
347 dbg("PHYS_ADDR: type= %d, y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
348 type, paddr->y, paddr->cb, paddr->cr, ret);
349
350 return ret;
351}
352
353/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
354static void fimc_set_yuv_order(struct fimc_ctx *ctx)
355{
356 /* The one only mode supported in SoC. */
357 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
358 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
359
360 /* Set order for 1 plane input formats. */
361 switch (ctx->s_frame.fmt->color) {
362 case S5P_FIMC_YCRYCB422:
363 ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
364 break;
365 case S5P_FIMC_CBYCRY422:
366 ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
367 break;
368 case S5P_FIMC_CRYCBY422:
369 ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
370 break;
371 case S5P_FIMC_YCBYCR422:
372 default:
373 ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
374 break;
375 }
376 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
377
378 switch (ctx->d_frame.fmt->color) {
379 case S5P_FIMC_YCRYCB422:
380 ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
381 break;
382 case S5P_FIMC_CBYCRY422:
383 ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
384 break;
385 case S5P_FIMC_CRYCBY422:
386 ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
387 break;
388 case S5P_FIMC_YCBYCR422:
389 default:
390 ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
391 break;
392 }
393 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
394}
395
396/**
397 * fimc_prepare_config - check dimensions, operation and color mode
398 * and pre-calculate offset and the scaling coefficients.
399 *
400 * @ctx: hardware context information
401 * @flags: flags indicating which parameters to check/update
402 *
403 * Return: 0 if dimensions are valid or non zero otherwise.
404 */
405static int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
406{
407 struct fimc_frame *s_frame, *d_frame;
408 struct fimc_vid_buffer *buf = NULL;
409 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
410 int ret = 0;
411
412 s_frame = &ctx->s_frame;
413 d_frame = &ctx->d_frame;
414
415 if (flags & FIMC_PARAMS) {
416 if ((ctx->out_path == FIMC_DMA) &&
417 (ctx->rotation == 90 || ctx->rotation == 270)) {
418 swap(d_frame->f_width, d_frame->f_height);
419 swap(d_frame->width, d_frame->height);
420 }
421
422 /* Prepare the output offset ratios for scaler. */
423 d_frame->dma_offset.y_h = d_frame->offs_h;
424 if (!variant->pix_hoff)
425 d_frame->dma_offset.y_h *= (d_frame->fmt->depth >> 3);
426
427 d_frame->dma_offset.y_v = d_frame->offs_v;
428
429 d_frame->dma_offset.cb_h = d_frame->offs_h;
430 d_frame->dma_offset.cb_v = d_frame->offs_v;
431
432 d_frame->dma_offset.cr_h = d_frame->offs_h;
433 d_frame->dma_offset.cr_v = d_frame->offs_v;
434
435 if (!variant->pix_hoff && d_frame->fmt->planes_cnt == 3) {
436 d_frame->dma_offset.cb_h >>= 1;
437 d_frame->dma_offset.cb_v >>= 1;
438 d_frame->dma_offset.cr_h >>= 1;
439 d_frame->dma_offset.cr_v >>= 1;
440 }
441
442 dbg("out offset: color= %d, y_h= %d, y_v= %d",
443 d_frame->fmt->color,
444 d_frame->dma_offset.y_h, d_frame->dma_offset.y_v);
445
446 /* Prepare the input offset ratios for scaler. */
447 s_frame->dma_offset.y_h = s_frame->offs_h;
448 if (!variant->pix_hoff)
449 s_frame->dma_offset.y_h *= (s_frame->fmt->depth >> 3);
450 s_frame->dma_offset.y_v = s_frame->offs_v;
451
452 s_frame->dma_offset.cb_h = s_frame->offs_h;
453 s_frame->dma_offset.cb_v = s_frame->offs_v;
454
455 s_frame->dma_offset.cr_h = s_frame->offs_h;
456 s_frame->dma_offset.cr_v = s_frame->offs_v;
457
458 if (!variant->pix_hoff && s_frame->fmt->planes_cnt == 3) {
459 s_frame->dma_offset.cb_h >>= 1;
460 s_frame->dma_offset.cb_v >>= 1;
461 s_frame->dma_offset.cr_h >>= 1;
462 s_frame->dma_offset.cr_v >>= 1;
463 }
464
465 dbg("in offset: color= %d, y_h= %d, y_v= %d",
466 s_frame->fmt->color, s_frame->dma_offset.y_h,
467 s_frame->dma_offset.y_v);
468
469 fimc_set_yuv_order(ctx);
470
471 /* Check against the scaler ratio. */
472 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
473 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
474 err("out of scaler range");
475 return -EINVAL;
476 }
477 }
478
479 /* Input DMA mode is not allowed when the scaler is disabled. */
480 ctx->scaler.enabled = 1;
481
482 if (flags & FIMC_SRC_ADDR) {
483 buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
484 ret = fimc_prepare_addr(ctx, buf,
485 V4L2_BUF_TYPE_VIDEO_OUTPUT);
486 if (ret)
487 return ret;
488 }
489
490 if (flags & FIMC_DST_ADDR) {
491 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
492 ret = fimc_prepare_addr(ctx, buf,
493 V4L2_BUF_TYPE_VIDEO_CAPTURE);
494 }
495
496 return ret;
497}
498
499static void fimc_dma_run(void *priv)
500{
501 struct fimc_ctx *ctx = priv;
502 struct fimc_dev *fimc;
503 unsigned long flags;
504 u32 ret;
505
506 if (WARN(!ctx, "null hardware context"))
507 return;
508
509 fimc = ctx->fimc_dev;
510
511 spin_lock_irqsave(&ctx->slock, flags);
512 set_bit(ST_M2M_PEND, &fimc->state);
513
514 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
515 ret = fimc_prepare_config(ctx, ctx->state);
516 if (ret) {
517 err("general configuration error");
518 goto dma_unlock;
519 }
520
521 if (fimc->m2m.ctx != ctx)
522 ctx->state |= FIMC_PARAMS;
523
524 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
525
526 if (ctx->state & FIMC_PARAMS) {
527 fimc_hw_set_input_path(ctx);
528 fimc_hw_set_in_dma(ctx);
529 if (fimc_set_scaler_info(ctx)) {
530 err("scaler configuration error");
531 goto dma_unlock;
532 }
533 fimc_hw_set_prescaler(ctx);
534 fimc_hw_set_scaler(ctx);
535 fimc_hw_set_target_format(ctx);
536 fimc_hw_set_rotation(ctx);
537 fimc_hw_set_effect(ctx);
538 }
539
540 fimc_hw_set_output_path(ctx);
541 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
542 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr);
543
544 if (ctx->state & FIMC_PARAMS)
545 fimc_hw_set_out_dma(ctx);
546
547 if (ctx->scaler.enabled)
548 fimc_hw_start_scaler(fimc);
549 fimc_hw_en_capture(ctx);
550
551 ctx->state = 0;
552 fimc_hw_start_in_dma(fimc);
553
554 fimc->m2m.ctx = ctx;
555
556dma_unlock:
557 spin_unlock_irqrestore(&ctx->slock, flags);
558}
559
560static void fimc_job_abort(void *priv)
561{
562 /* Nothing done in job_abort. */
563}
564
565static void fimc_buf_release(struct videobuf_queue *vq,
566 struct videobuf_buffer *vb)
567{
568 videobuf_dma_contig_free(vq, vb);
569 vb->state = VIDEOBUF_NEEDS_INIT;
570}
571
572static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
573 unsigned int *size)
574{
575 struct fimc_ctx *ctx = vq->priv_data;
576 struct fimc_frame *frame;
577
578 frame = ctx_m2m_get_frame(ctx, vq->type);
579 if (IS_ERR(frame))
580 return PTR_ERR(frame);
581
582 *size = (frame->width * frame->height * frame->fmt->depth) >> 3;
583 if (0 == *count)
584 *count = 1;
585 return 0;
586}
587
588static int fimc_buf_prepare(struct videobuf_queue *vq,
589 struct videobuf_buffer *vb, enum v4l2_field field)
590{
591 struct fimc_ctx *ctx = vq->priv_data;
592 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
593 struct fimc_frame *frame;
594 int ret;
595
596 frame = ctx_m2m_get_frame(ctx, vq->type);
597 if (IS_ERR(frame))
598 return PTR_ERR(frame);
599
600 if (vb->baddr) {
601 if (vb->bsize < frame->size) {
602 v4l2_err(v4l2_dev,
603 "User-provided buffer too small (%d < %d)\n",
604 vb->bsize, frame->size);
605 WARN_ON(1);
606 return -EINVAL;
607 }
608 } else if (vb->state != VIDEOBUF_NEEDS_INIT
609 && vb->bsize < frame->size) {
610 return -EINVAL;
611 }
612
613 vb->width = frame->width;
614 vb->height = frame->height;
615 vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
616 vb->size = frame->size;
617 vb->field = field;
618
619 if (VIDEOBUF_NEEDS_INIT == vb->state) {
620 ret = videobuf_iolock(vq, vb, NULL);
621 if (ret) {
622 v4l2_err(v4l2_dev, "Iolock failed\n");
623 fimc_buf_release(vq, vb);
624 return ret;
625 }
626 }
627 vb->state = VIDEOBUF_PREPARED;
628
629 return 0;
630}
631
632static void fimc_buf_queue(struct videobuf_queue *vq,
633 struct videobuf_buffer *vb)
634{
635 struct fimc_ctx *ctx = vq->priv_data;
636 v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
637}
638
639static struct videobuf_queue_ops fimc_qops = {
640 .buf_setup = fimc_buf_setup,
641 .buf_prepare = fimc_buf_prepare,
642 .buf_queue = fimc_buf_queue,
643 .buf_release = fimc_buf_release,
644};
645
646static int fimc_m2m_querycap(struct file *file, void *priv,
647 struct v4l2_capability *cap)
648{
649 struct fimc_ctx *ctx = file->private_data;
650 struct fimc_dev *fimc = ctx->fimc_dev;
651
652 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
653 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
654 cap->bus_info[0] = 0;
655 cap->version = KERNEL_VERSION(1, 0, 0);
656 cap->capabilities = V4L2_CAP_STREAMING |
657 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
658
659 return 0;
660}
661
662static int fimc_m2m_enum_fmt(struct file *file, void *priv,
663 struct v4l2_fmtdesc *f)
664{
665 struct fimc_fmt *fmt;
666
667 if (f->index >= ARRAY_SIZE(fimc_formats))
668 return -EINVAL;
669
670 fmt = &fimc_formats[f->index];
671 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
672 f->pixelformat = fmt->fourcc;
673 return 0;
674}
675
676static int fimc_m2m_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
677{
678 struct fimc_ctx *ctx = priv;
679 struct fimc_frame *frame;
680
681 frame = ctx_m2m_get_frame(ctx, f->type);
682 if (IS_ERR(frame))
683 return PTR_ERR(frame);
684
685 f->fmt.pix.width = frame->width;
686 f->fmt.pix.height = frame->height;
687 f->fmt.pix.field = V4L2_FIELD_NONE;
688 f->fmt.pix.pixelformat = frame->fmt->fourcc;
689
690 return 0;
691}
692
693static struct fimc_fmt *find_format(struct v4l2_format *f)
694{
695 struct fimc_fmt *fmt;
696 unsigned int i;
697
698 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
699 fmt = &fimc_formats[i];
700 if (fmt->fourcc == f->fmt.pix.pixelformat)
701 break;
702 }
703 if (i == ARRAY_SIZE(fimc_formats))
704 return NULL;
705
706 return fmt;
707}
708
709static int fimc_m2m_try_fmt(struct file *file, void *priv,
710 struct v4l2_format *f)
711{
712 struct fimc_fmt *fmt;
713 u32 max_width, max_height, mod_x, mod_y;
714 struct fimc_ctx *ctx = priv;
715 struct fimc_dev *fimc = ctx->fimc_dev;
716 struct v4l2_pix_format *pix = &f->fmt.pix;
717 struct samsung_fimc_variant *variant = fimc->variant;
718
719 fmt = find_format(f);
720 if (!fmt) {
721 v4l2_err(&fimc->m2m.v4l2_dev,
722 "Fourcc format (0x%X) invalid.\n", pix->pixelformat);
723 return -EINVAL;
724 }
725
726 if (pix->field == V4L2_FIELD_ANY)
727 pix->field = V4L2_FIELD_NONE;
728 else if (V4L2_FIELD_NONE != pix->field)
729 return -EINVAL;
730
731 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
732 max_width = variant->scaler_dis_w;
733 max_height = variant->scaler_dis_w;
734 mod_x = variant->min_inp_pixsize;
735 mod_y = variant->min_inp_pixsize;
736 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
737 max_width = variant->out_rot_dis_w;
738 max_height = variant->out_rot_dis_w;
739 mod_x = variant->min_out_pixsize;
740 mod_y = variant->min_out_pixsize;
741 } else {
742 err("Wrong stream type (%d)", f->type);
743 return -EINVAL;
744 }
745
746 dbg("max_w= %d, max_h= %d", max_width, max_height);
747
748 if (pix->height > max_height)
749 pix->height = max_height;
750 if (pix->width > max_width)
751 pix->width = max_width;
752
753 if (tiled_fmt(fmt)) {
754 mod_x = 64; /* 64x32 tile */
755 mod_y = 32;
756 }
757
758 dbg("mod_x= 0x%X, mod_y= 0x%X", mod_x, mod_y);
759
760 pix->width = (pix->width == 0) ? mod_x : ALIGN(pix->width, mod_x);
761 pix->height = (pix->height == 0) ? mod_y : ALIGN(pix->height, mod_y);
762
763 if (pix->bytesperline == 0 ||
764 pix->bytesperline * 8 / fmt->depth > pix->width)
765 pix->bytesperline = (pix->width * fmt->depth) >> 3;
766
767 if (pix->sizeimage == 0)
768 pix->sizeimage = pix->height * pix->bytesperline;
769
770 dbg("pix->bytesperline= %d, fmt->depth= %d",
771 pix->bytesperline, fmt->depth);
772
773 return 0;
774}
775
776
777static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
778{
779 struct fimc_ctx *ctx = priv;
780 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
781 struct videobuf_queue *src_vq, *dst_vq;
782 struct fimc_frame *frame;
783 struct v4l2_pix_format *pix;
784 unsigned long flags;
785 int ret = 0;
786
787 BUG_ON(!ctx);
788
789 ret = fimc_m2m_try_fmt(file, priv, f);
790 if (ret)
791 return ret;
792
793 mutex_lock(&ctx->fimc_dev->lock);
794
795 src_vq = v4l2_m2m_get_src_vq(ctx->m2m_ctx);
796 dst_vq = v4l2_m2m_get_dst_vq(ctx->m2m_ctx);
797
798 mutex_lock(&src_vq->vb_lock);
799 mutex_lock(&dst_vq->vb_lock);
800
801 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
802 if (videobuf_queue_is_busy(src_vq)) {
803 v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
804 ret = -EBUSY;
805 goto s_fmt_out;
806 }
807 frame = &ctx->s_frame;
808 spin_lock_irqsave(&ctx->slock, flags);
809 ctx->state |= FIMC_SRC_FMT;
810 spin_unlock_irqrestore(&ctx->slock, flags);
811
812 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
813 if (videobuf_queue_is_busy(dst_vq)) {
814 v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
815 ret = -EBUSY;
816 goto s_fmt_out;
817 }
818 frame = &ctx->d_frame;
819 spin_lock_irqsave(&ctx->slock, flags);
820 ctx->state |= FIMC_DST_FMT;
821 spin_unlock_irqrestore(&ctx->slock, flags);
822 } else {
823 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
824 "Wrong buffer/video queue type (%d)\n", f->type);
825 return -EINVAL;
826 }
827
828 pix = &f->fmt.pix;
829 frame->fmt = find_format(f);
830 if (!frame->fmt) {
831 ret = -EINVAL;
832 goto s_fmt_out;
833 }
834
835 frame->f_width = pix->bytesperline * 8 / frame->fmt->depth;
836 frame->f_height = pix->sizeimage/pix->bytesperline;
837 frame->width = pix->width;
838 frame->height = pix->height;
839 frame->o_width = pix->width;
840 frame->o_height = pix->height;
841 frame->offs_h = 0;
842 frame->offs_v = 0;
843 frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
844 src_vq->field = dst_vq->field = pix->field;
845 spin_lock_irqsave(&ctx->slock, flags);
846 ctx->state |= FIMC_PARAMS;
847 spin_unlock_irqrestore(&ctx->slock, flags);
848
849 dbg("f_width= %d, f_height= %d", frame->f_width, frame->f_height);
850
851s_fmt_out:
852 mutex_unlock(&dst_vq->vb_lock);
853 mutex_unlock(&src_vq->vb_lock);
854 mutex_unlock(&ctx->fimc_dev->lock);
855 return ret;
856}
857
858static int fimc_m2m_reqbufs(struct file *file, void *priv,
859 struct v4l2_requestbuffers *reqbufs)
860{
861 struct fimc_ctx *ctx = priv;
862 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
863}
864
865static int fimc_m2m_querybuf(struct file *file, void *priv,
866 struct v4l2_buffer *buf)
867{
868 struct fimc_ctx *ctx = priv;
869 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
870}
871
872static int fimc_m2m_qbuf(struct file *file, void *priv,
873 struct v4l2_buffer *buf)
874{
875 struct fimc_ctx *ctx = priv;
876
877 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
878}
879
880static int fimc_m2m_dqbuf(struct file *file, void *priv,
881 struct v4l2_buffer *buf)
882{
883 struct fimc_ctx *ctx = priv;
884 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
885}
886
887static int fimc_m2m_streamon(struct file *file, void *priv,
888 enum v4l2_buf_type type)
889{
890 struct fimc_ctx *ctx = priv;
891 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
892}
893
894static int fimc_m2m_streamoff(struct file *file, void *priv,
895 enum v4l2_buf_type type)
896{
897 struct fimc_ctx *ctx = priv;
898 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
899}
900
901int fimc_m2m_queryctrl(struct file *file, void *priv,
902 struct v4l2_queryctrl *qc)
903{
904 struct v4l2_queryctrl *c;
905 c = get_ctrl(qc->id);
906 if (!c)
907 return -EINVAL;
908 *qc = *c;
909 return 0;
910}
911
912int fimc_m2m_g_ctrl(struct file *file, void *priv,
913 struct v4l2_control *ctrl)
914{
915 struct fimc_ctx *ctx = priv;
916
917 switch (ctrl->id) {
918 case V4L2_CID_HFLIP:
919 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
920 break;
921 case V4L2_CID_VFLIP:
922 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
923 break;
924 case V4L2_CID_ROTATE:
925 ctrl->value = ctx->rotation;
926 break;
927 default:
928 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
929 return -EINVAL;
930 }
931 dbg("ctrl->value= %d", ctrl->value);
932 return 0;
933}
934
935static int check_ctrl_val(struct fimc_ctx *ctx,
936 struct v4l2_control *ctrl)
937{
938 struct v4l2_queryctrl *c;
939 c = get_ctrl(ctrl->id);
940 if (!c)
941 return -EINVAL;
942
943 if (ctrl->value < c->minimum || ctrl->value > c->maximum
944 || (c->step != 0 && ctrl->value % c->step != 0)) {
945 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
946 "Invalid control value\n");
947 return -ERANGE;
948 }
949
950 return 0;
951}
952
953int fimc_m2m_s_ctrl(struct file *file, void *priv,
954 struct v4l2_control *ctrl)
955{
956 struct fimc_ctx *ctx = priv;
957 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
958 unsigned long flags;
959 int ret = 0;
960
961 ret = check_ctrl_val(ctx, ctrl);
962 if (ret)
963 return ret;
964
965 switch (ctrl->id) {
966 case V4L2_CID_HFLIP:
967 if (ctx->rotation != 0)
968 return 0;
969 if (ctrl->value)
970 ctx->flip |= FLIP_X_AXIS;
971 else
972 ctx->flip &= ~FLIP_X_AXIS;
973 break;
974
975 case V4L2_CID_VFLIP:
976 if (ctx->rotation != 0)
977 return 0;
978 if (ctrl->value)
979 ctx->flip |= FLIP_Y_AXIS;
980 else
981 ctx->flip &= ~FLIP_Y_AXIS;
982 break;
983
984 case V4L2_CID_ROTATE:
985 if (ctrl->value == 90 || ctrl->value == 270) {
986 if (ctx->out_path == FIMC_LCDFIFO &&
987 !variant->has_inp_rot) {
988 return -EINVAL;
989 } else if (ctx->in_path == FIMC_DMA &&
990 !variant->has_out_rot) {
991 return -EINVAL;
992 }
993 }
994 ctx->rotation = ctrl->value;
995 if (ctrl->value == 180)
996 ctx->flip = FLIP_XY_AXIS;
997 break;
998
999 default:
1000 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
1001 return -EINVAL;
1002 }
1003 spin_lock_irqsave(&ctx->slock, flags);
1004 ctx->state |= FIMC_PARAMS;
1005 spin_unlock_irqrestore(&ctx->slock, flags);
1006 return 0;
1007}
1008
1009
1010static int fimc_m2m_cropcap(struct file *file, void *fh,
1011 struct v4l2_cropcap *cr)
1012{
1013 struct fimc_frame *frame;
1014 struct fimc_ctx *ctx = fh;
1015
1016 frame = ctx_m2m_get_frame(ctx, cr->type);
1017 if (IS_ERR(frame))
1018 return PTR_ERR(frame);
1019
1020 cr->bounds.left = 0;
1021 cr->bounds.top = 0;
1022 cr->bounds.width = frame->f_width;
1023 cr->bounds.height = frame->f_height;
1024 cr->defrect.left = frame->offs_h;
1025 cr->defrect.top = frame->offs_v;
1026 cr->defrect.width = frame->o_width;
1027 cr->defrect.height = frame->o_height;
1028 return 0;
1029}
1030
1031static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1032{
1033 struct fimc_frame *frame;
1034 struct fimc_ctx *ctx = file->private_data;
1035
1036 frame = ctx_m2m_get_frame(ctx, cr->type);
1037 if (IS_ERR(frame))
1038 return PTR_ERR(frame);
1039
1040 cr->c.left = frame->offs_h;
1041 cr->c.top = frame->offs_v;
1042 cr->c.width = frame->width;
1043 cr->c.height = frame->height;
1044
1045 return 0;
1046}
1047
1048static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1049{
1050 struct fimc_ctx *ctx = file->private_data;
1051 struct fimc_dev *fimc = ctx->fimc_dev;
1052 unsigned long flags;
1053 struct fimc_frame *f;
1054 u32 min_size;
1055 int ret = 0;
1056
1057 if (cr->c.top < 0 || cr->c.left < 0) {
1058 v4l2_err(&fimc->m2m.v4l2_dev,
1059 "doesn't support negative values for top & left\n");
1060 return -EINVAL;
1061 }
1062
1063 if (cr->c.width <= 0 || cr->c.height <= 0) {
1064 v4l2_err(&fimc->m2m.v4l2_dev,
1065 "crop width and height must be greater than 0\n");
1066 return -EINVAL;
1067 }
1068
1069 f = ctx_m2m_get_frame(ctx, cr->type);
1070 if (IS_ERR(f))
1071 return PTR_ERR(f);
1072
1073 /* Adjust to required pixel boundary. */
1074 min_size = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
1075 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1076
1077 cr->c.width = round_down(cr->c.width, min_size);
1078 cr->c.height = round_down(cr->c.height, min_size);
1079 cr->c.left = round_down(cr->c.left + 1, min_size);
1080 cr->c.top = round_down(cr->c.top + 1, min_size);
1081
1082 if ((cr->c.left + cr->c.width > f->o_width)
1083 || (cr->c.top + cr->c.height > f->o_height)) {
1084 v4l2_err(&fimc->m2m.v4l2_dev, "Error in S_CROP params\n");
1085 return -EINVAL;
1086 }
1087
1088 spin_lock_irqsave(&ctx->slock, flags);
1089 if ((ctx->state & FIMC_SRC_FMT) && (ctx->state & FIMC_DST_FMT)) {
1090 /* Check for the pixel scaling ratio when cropping input img. */
1091 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1092 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
1093 else if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1094 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
1095
1096 if (ret) {
1097 spin_unlock_irqrestore(&ctx->slock, flags);
1098 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
1099 return -EINVAL;
1100 }
1101 }
1102 ctx->state |= FIMC_PARAMS;
1103 spin_unlock_irqrestore(&ctx->slock, flags);
1104
1105 f->offs_h = cr->c.left;
1106 f->offs_v = cr->c.top;
1107 f->width = cr->c.width;
1108 f->height = cr->c.height;
1109 return 0;
1110}
1111
1112static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1113 .vidioc_querycap = fimc_m2m_querycap,
1114
1115 .vidioc_enum_fmt_vid_cap = fimc_m2m_enum_fmt,
1116 .vidioc_enum_fmt_vid_out = fimc_m2m_enum_fmt,
1117
1118 .vidioc_g_fmt_vid_cap = fimc_m2m_g_fmt,
1119 .vidioc_g_fmt_vid_out = fimc_m2m_g_fmt,
1120
1121 .vidioc_try_fmt_vid_cap = fimc_m2m_try_fmt,
1122 .vidioc_try_fmt_vid_out = fimc_m2m_try_fmt,
1123
1124 .vidioc_s_fmt_vid_cap = fimc_m2m_s_fmt,
1125 .vidioc_s_fmt_vid_out = fimc_m2m_s_fmt,
1126
1127 .vidioc_reqbufs = fimc_m2m_reqbufs,
1128 .vidioc_querybuf = fimc_m2m_querybuf,
1129
1130 .vidioc_qbuf = fimc_m2m_qbuf,
1131 .vidioc_dqbuf = fimc_m2m_dqbuf,
1132
1133 .vidioc_streamon = fimc_m2m_streamon,
1134 .vidioc_streamoff = fimc_m2m_streamoff,
1135
1136 .vidioc_queryctrl = fimc_m2m_queryctrl,
1137 .vidioc_g_ctrl = fimc_m2m_g_ctrl,
1138 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1139
1140 .vidioc_g_crop = fimc_m2m_g_crop,
1141 .vidioc_s_crop = fimc_m2m_s_crop,
1142 .vidioc_cropcap = fimc_m2m_cropcap
1143
1144};
1145
1146static void queue_init(void *priv, struct videobuf_queue *vq,
1147 enum v4l2_buf_type type)
1148{
1149 struct fimc_ctx *ctx = priv;
1150 struct fimc_dev *fimc = ctx->fimc_dev;
1151
1152 videobuf_queue_dma_contig_init(vq, &fimc_qops,
1153 fimc->m2m.v4l2_dev.dev,
1154 &fimc->irqlock, type, V4L2_FIELD_NONE,
1155 sizeof(struct fimc_vid_buffer), priv);
1156}
1157
1158static int fimc_m2m_open(struct file *file)
1159{
1160 struct fimc_dev *fimc = video_drvdata(file);
1161 struct fimc_ctx *ctx = NULL;
1162 int err = 0;
1163
1164 mutex_lock(&fimc->lock);
1165 fimc->m2m.refcnt++;
1166 set_bit(ST_OUTDMA_RUN, &fimc->state);
1167 mutex_unlock(&fimc->lock);
1168
1169
1170 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1171 if (!ctx)
1172 return -ENOMEM;
1173
1174 file->private_data = ctx;
1175 ctx->fimc_dev = fimc;
1176 /* default format */
1177 ctx->s_frame.fmt = &fimc_formats[0];
1178 ctx->d_frame.fmt = &fimc_formats[0];
1179 /* per user process device context initialization */
1180 ctx->state = 0;
1181 ctx->flags = 0;
1182 ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
1183 ctx->in_path = FIMC_DMA;
1184 ctx->out_path = FIMC_DMA;
1185 spin_lock_init(&ctx->slock);
1186
1187 ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, fimc->m2m.m2m_dev, queue_init);
1188 if (IS_ERR(ctx->m2m_ctx)) {
1189 err = PTR_ERR(ctx->m2m_ctx);
1190 kfree(ctx);
1191 }
1192 return err;
1193}
1194
1195static int fimc_m2m_release(struct file *file)
1196{
1197 struct fimc_ctx *ctx = file->private_data;
1198 struct fimc_dev *fimc = ctx->fimc_dev;
1199
1200 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1201 kfree(ctx);
1202 mutex_lock(&fimc->lock);
1203 if (--fimc->m2m.refcnt <= 0)
1204 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1205 mutex_unlock(&fimc->lock);
1206 return 0;
1207}
1208
1209static unsigned int fimc_m2m_poll(struct file *file,
1210 struct poll_table_struct *wait)
1211{
1212 struct fimc_ctx *ctx = file->private_data;
1213 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1214}
1215
1216
1217static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1218{
1219 struct fimc_ctx *ctx = file->private_data;
1220 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1221}
1222
1223static const struct v4l2_file_operations fimc_m2m_fops = {
1224 .owner = THIS_MODULE,
1225 .open = fimc_m2m_open,
1226 .release = fimc_m2m_release,
1227 .poll = fimc_m2m_poll,
1228 .ioctl = video_ioctl2,
1229 .mmap = fimc_m2m_mmap,
1230};
1231
1232static struct v4l2_m2m_ops m2m_ops = {
1233 .device_run = fimc_dma_run,
1234 .job_abort = fimc_job_abort,
1235};
1236
1237
1238static int fimc_register_m2m_device(struct fimc_dev *fimc)
1239{
1240 struct video_device *vfd;
1241 struct platform_device *pdev;
1242 struct v4l2_device *v4l2_dev;
1243 int ret = 0;
1244
1245 if (!fimc)
1246 return -ENODEV;
1247
1248 pdev = fimc->pdev;
1249 v4l2_dev = &fimc->m2m.v4l2_dev;
1250
1251 /* set name if it is empty */
1252 if (!v4l2_dev->name[0])
1253 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1254 "%s.m2m", dev_name(&pdev->dev));
1255
1256 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1257 if (ret)
1258 return ret;;
1259
1260 vfd = video_device_alloc();
1261 if (!vfd) {
1262 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1263 goto err_m2m_r1;
1264 }
1265
1266 vfd->fops = &fimc_m2m_fops;
1267 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1268 vfd->minor = -1;
1269 vfd->release = video_device_release;
1270
1271 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1272
1273 video_set_drvdata(vfd, fimc);
1274 platform_set_drvdata(pdev, fimc);
1275
1276 fimc->m2m.vfd = vfd;
1277 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1278 if (IS_ERR(fimc->m2m.m2m_dev)) {
1279 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1280 ret = PTR_ERR(fimc->m2m.m2m_dev);
1281 goto err_m2m_r2;
1282 }
1283
1284 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1285 if (ret) {
1286 v4l2_err(v4l2_dev,
1287 "%s(): failed to register video device\n", __func__);
1288 goto err_m2m_r3;
1289 }
1290 v4l2_info(v4l2_dev,
1291 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1292
1293 return 0;
1294
1295err_m2m_r3:
1296 v4l2_m2m_release(fimc->m2m.m2m_dev);
1297err_m2m_r2:
1298 video_device_release(fimc->m2m.vfd);
1299err_m2m_r1:
1300 v4l2_device_unregister(v4l2_dev);
1301
1302 return ret;
1303}
1304
1305static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1306{
1307 if (fimc) {
1308 v4l2_m2m_release(fimc->m2m.m2m_dev);
1309 video_unregister_device(fimc->m2m.vfd);
1310 video_device_release(fimc->m2m.vfd);
1311 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1312 }
1313}
1314
1315static void fimc_clk_release(struct fimc_dev *fimc)
1316{
1317 int i;
1318 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1319 if (fimc->clock[i]) {
1320 clk_disable(fimc->clock[i]);
1321 clk_put(fimc->clock[i]);
1322 }
1323 }
1324}
1325
1326static int fimc_clk_get(struct fimc_dev *fimc)
1327{
1328 int i;
1329 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1330 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
1331 if (IS_ERR(fimc->clock[i])) {
1332 dev_err(&fimc->pdev->dev,
1333 "failed to get fimc clock: %s\n",
1334 fimc_clock_name[i]);
1335 return -ENXIO;
1336 }
1337 clk_enable(fimc->clock[i]);
1338 }
1339 return 0;
1340}
1341
1342static int fimc_probe(struct platform_device *pdev)
1343{
1344 struct fimc_dev *fimc;
1345 struct resource *res;
1346 struct samsung_fimc_driverdata *drv_data;
1347 int ret = 0;
1348
1349 dev_dbg(&pdev->dev, "%s():\n", __func__);
1350
1351 drv_data = (struct samsung_fimc_driverdata *)
1352 platform_get_device_id(pdev)->driver_data;
1353
1354 if (pdev->id >= drv_data->devs_cnt) {
1355 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1356 pdev->id);
1357 return -EINVAL;
1358 }
1359
1360 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1361 if (!fimc)
1362 return -ENOMEM;
1363
1364 fimc->id = pdev->id;
1365 fimc->variant = drv_data->variant[fimc->id];
1366 fimc->pdev = pdev;
1367 fimc->state = ST_IDLE;
1368
1369 spin_lock_init(&fimc->irqlock);
1370 spin_lock_init(&fimc->slock);
1371
1372 mutex_init(&fimc->lock);
1373
1374 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1375 if (!res) {
1376 dev_err(&pdev->dev, "failed to find the registers\n");
1377 ret = -ENOENT;
1378 goto err_info;
1379 }
1380
1381 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1382 dev_name(&pdev->dev));
1383 if (!fimc->regs_res) {
1384 dev_err(&pdev->dev, "failed to obtain register region\n");
1385 ret = -ENOENT;
1386 goto err_info;
1387 }
1388
1389 fimc->regs = ioremap(res->start, resource_size(res));
1390 if (!fimc->regs) {
1391 dev_err(&pdev->dev, "failed to map registers\n");
1392 ret = -ENXIO;
1393 goto err_req_region;
1394 }
1395
1396 ret = fimc_clk_get(fimc);
1397 if (ret)
1398 goto err_regs_unmap;
1399
1400 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1401 if (!res) {
1402 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1403 ret = -ENXIO;
1404 goto err_clk;
1405 }
1406 fimc->irq = res->start;
1407
1408 fimc_hw_reset(fimc);
1409
1410 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1411 if (ret) {
1412 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1413 goto err_clk;
1414 }
1415
1416 fimc->work_queue = create_workqueue(dev_name(&fimc->pdev->dev));
1417 if (!fimc->work_queue)
1418 goto err_irq;
1419
1420 ret = fimc_register_m2m_device(fimc);
1421 if (ret)
1422 goto err_wq;
1423
1424 fimc_hw_en_lastirq(fimc, true);
1425
1426 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1427 __func__, fimc->id);
1428
1429 return 0;
1430
1431err_wq:
1432 destroy_workqueue(fimc->work_queue);
1433err_irq:
1434 free_irq(fimc->irq, fimc);
1435err_clk:
1436 fimc_clk_release(fimc);
1437err_regs_unmap:
1438 iounmap(fimc->regs);
1439err_req_region:
1440 release_resource(fimc->regs_res);
1441 kfree(fimc->regs_res);
1442err_info:
1443 kfree(fimc);
1444 dev_err(&pdev->dev, "failed to install\n");
1445 return ret;
1446}
1447
1448static int __devexit fimc_remove(struct platform_device *pdev)
1449{
1450 struct fimc_dev *fimc =
1451 (struct fimc_dev *)platform_get_drvdata(pdev);
1452
1453 v4l2_info(&fimc->m2m.v4l2_dev, "Removing %s\n", pdev->name);
1454
1455 free_irq(fimc->irq, fimc);
1456
1457 fimc_hw_reset(fimc);
1458
1459 fimc_unregister_m2m_device(fimc);
1460 fimc_clk_release(fimc);
1461 iounmap(fimc->regs);
1462 release_resource(fimc->regs_res);
1463 kfree(fimc->regs_res);
1464 kfree(fimc);
1465 return 0;
1466}
1467
1468static struct samsung_fimc_variant fimc01_variant_s5p = {
1469 .has_inp_rot = 1,
1470 .has_out_rot = 1,
1471 .min_inp_pixsize = 16,
1472 .min_out_pixsize = 16,
1473
1474 .scaler_en_w = 3264,
1475 .scaler_dis_w = 8192,
1476 .in_rot_en_h = 1920,
1477 .in_rot_dis_w = 8192,
1478 .out_rot_en_w = 1920,
1479 .out_rot_dis_w = 4224,
1480};
1481
1482static struct samsung_fimc_variant fimc2_variant_s5p = {
1483 .min_inp_pixsize = 16,
1484 .min_out_pixsize = 16,
1485
1486 .scaler_en_w = 4224,
1487 .scaler_dis_w = 8192,
1488 .in_rot_en_h = 1920,
1489 .in_rot_dis_w = 8192,
1490 .out_rot_en_w = 1920,
1491 .out_rot_dis_w = 4224,
1492};
1493
1494static struct samsung_fimc_variant fimc01_variant_s5pv210 = {
1495 .has_inp_rot = 1,
1496 .has_out_rot = 1,
1497 .min_inp_pixsize = 16,
1498 .min_out_pixsize = 32,
1499
1500 .scaler_en_w = 4224,
1501 .scaler_dis_w = 8192,
1502 .in_rot_en_h = 1920,
1503 .in_rot_dis_w = 8192,
1504 .out_rot_en_w = 1920,
1505 .out_rot_dis_w = 4224,
1506};
1507
1508static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1509 .min_inp_pixsize = 16,
1510 .min_out_pixsize = 32,
1511
1512 .scaler_en_w = 1920,
1513 .scaler_dis_w = 8192,
1514 .in_rot_en_h = 1280,
1515 .in_rot_dis_w = 8192,
1516 .out_rot_en_w = 1280,
1517 .out_rot_dis_w = 1920,
1518};
1519
1520static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1521 .variant = {
1522 [0] = &fimc01_variant_s5p,
1523 [1] = &fimc01_variant_s5p,
1524 [2] = &fimc2_variant_s5p,
1525 },
1526 .devs_cnt = 3
1527};
1528
1529static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1530 .variant = {
1531 [0] = &fimc01_variant_s5pv210,
1532 [1] = &fimc01_variant_s5pv210,
1533 [2] = &fimc2_variant_s5pv210,
1534 },
1535 .devs_cnt = 3
1536};
1537
1538static struct platform_device_id fimc_driver_ids[] = {
1539 {
1540 .name = "s5p-fimc",
1541 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1542 }, {
1543 .name = "s5pv210-fimc",
1544 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1545 },
1546 {},
1547};
1548MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1549
1550static struct platform_driver fimc_driver = {
1551 .probe = fimc_probe,
1552 .remove = __devexit_p(fimc_remove),
1553 .id_table = fimc_driver_ids,
1554 .driver = {
1555 .name = MODULE_NAME,
1556 .owner = THIS_MODULE,
1557 }
1558};
1559
1560static char banner[] __initdata = KERN_INFO
1561 "S5PC Camera Interface V4L2 Driver, (c) 2010 Samsung Electronics\n";
1562
1563static int __init fimc_init(void)
1564{
1565 u32 ret;
1566 printk(banner);
1567
1568 ret = platform_driver_register(&fimc_driver);
1569 if (ret) {
1570 printk(KERN_ERR "FIMC platform driver register failed\n");
1571 return -1;
1572 }
1573 return 0;
1574}
1575
1576static void __exit fimc_exit(void)
1577{
1578 platform_driver_unregister(&fimc_driver);
1579}
1580
1581module_init(fimc_init);
1582module_exit(fimc_exit);
1583
1584MODULE_AUTHOR("Sylwester Nawrocki, s.nawrocki@samsung.com");
1585MODULE_DESCRIPTION("S3C/S5P FIMC (video postprocessor) driver");
1586MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
new file mode 100644
index 000000000000..6b3e0cd73cdd
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -0,0 +1,471 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics
3 *
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef FIMC_CORE_H_
12#define FIMC_CORE_H_
13
14#include <linux/types.h>
15#include <media/videobuf-core.h>
16#include <media/v4l2-device.h>
17#include <media/v4l2-mem2mem.h>
18#include <linux/videodev2.h>
19#include "regs-fimc.h"
20
21#define err(fmt, args...) \
22 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
23
24#ifdef DEBUG
25#define dbg(fmt, args...) \
26 printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
27#else
28#define dbg(fmt, args...)
29#endif
30
31#define NUM_FIMC_CLOCKS 2
32#define MODULE_NAME "s5p-fimc"
33#define FIMC_MAX_DEVS 3
34#define FIMC_MAX_OUT_BUFS 4
35#define SCALER_MAX_HRATIO 64
36#define SCALER_MAX_VRATIO 64
37
38enum {
39 ST_IDLE,
40 ST_OUTDMA_RUN,
41 ST_M2M_PEND,
42};
43
44#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
45#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
46
47enum fimc_datapath {
48 FIMC_ITU_CAM_A,
49 FIMC_ITU_CAM_B,
50 FIMC_MIPI_CAM,
51 FIMC_DMA,
52 FIMC_LCDFIFO,
53 FIMC_WRITEBACK
54};
55
56enum fimc_color_fmt {
57 S5P_FIMC_RGB565,
58 S5P_FIMC_RGB666,
59 S5P_FIMC_RGB888,
60 S5P_FIMC_YCBCR420,
61 S5P_FIMC_YCBCR422,
62 S5P_FIMC_YCBYCR422,
63 S5P_FIMC_YCRYCB422,
64 S5P_FIMC_CBYCRY422,
65 S5P_FIMC_CRYCBY422,
66 S5P_FIMC_RGB30_LOCAL,
67 S5P_FIMC_YCBCR444_LOCAL,
68 S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
69 S5P_FIMC_COLOR_MASK = 0x0F,
70};
71
72/* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
73#define S5P_FIMC_OUT_CRYCBY S5P_CIOCTRL_ORDER422_CRYCBY
74#define S5P_FIMC_OUT_CBYCRY S5P_CIOCTRL_ORDER422_YCRYCB
75#define S5P_FIMC_OUT_YCRYCB S5P_CIOCTRL_ORDER422_CBYCRY
76#define S5P_FIMC_OUT_YCBYCR S5P_CIOCTRL_ORDER422_YCBYCR
77
78/* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
79#define S5P_FIMC_IN_CRYCBY S5P_MSCTRL_ORDER422_CRYCBY
80#define S5P_FIMC_IN_CBYCRY S5P_MSCTRL_ORDER422_YCRYCB
81#define S5P_FIMC_IN_YCRYCB S5P_MSCTRL_ORDER422_CBYCRY
82#define S5P_FIMC_IN_YCBYCR S5P_MSCTRL_ORDER422_YCBYCR
83
84/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
85#define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
86
87/* The embedded image effect selection */
88#define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
89#define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
90#define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
91#define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
92#define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
93#define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
94
95/* The hardware context state. */
96#define FIMC_PARAMS (1 << 0)
97#define FIMC_SRC_ADDR (1 << 1)
98#define FIMC_DST_ADDR (1 << 2)
99#define FIMC_SRC_FMT (1 << 3)
100#define FIMC_DST_FMT (1 << 4)
101
102/* Image conversion flags */
103#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
104#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
105#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
106#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
107#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
108#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
109/* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
110#define FIMC_COLOR_RANGE_WIDE (0 << 3)
111/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
112#define FIMC_COLOR_RANGE_NARROW (1 << 3)
113
114#define FLIP_NONE 0
115#define FLIP_X_AXIS 1
116#define FLIP_Y_AXIS 2
117#define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
118
119/**
120 * struct fimc_fmt - the driver's internal color format data
121 * @name: format description
122 * @fourcc: the fourcc code for this format
123 * @color: the corresponding fimc_color_fmt
124 * @depth: number of bits per pixel
125 * @buff_cnt: number of physically non-contiguous data planes
126 * @planes_cnt: number of physically contiguous data planes
127 */
128struct fimc_fmt {
129 char *name;
130 u32 fourcc;
131 u32 color;
132 u32 depth;
133 u16 buff_cnt;
134 u16 planes_cnt;
135};
136
137/**
138 * struct fimc_dma_offset - pixel offset information for DMA
139 * @y_h: y value horizontal offset
140 * @y_v: y value vertical offset
141 * @cb_h: cb value horizontal offset
142 * @cb_v: cb value vertical offset
143 * @cr_h: cr value horizontal offset
144 * @cr_v: cr value vertical offset
145 */
146struct fimc_dma_offset {
147 int y_h;
148 int y_v;
149 int cb_h;
150 int cb_v;
151 int cr_h;
152 int cr_v;
153};
154
155/**
156 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
157 * @type: effect type
158 * @pat_cb: cr value when type is "arbitrary"
159 * @pat_cr: cr value when type is "arbitrary"
160 */
161struct fimc_effect {
162 u32 type;
163 u8 pat_cb;
164 u8 pat_cr;
165};
166
167/**
168 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
169 *
170 * @enabled: the flag set when the scaler is used
171 * @hfactor: horizontal shift factor
172 * @vfactor: vertical shift factor
173 * @pre_hratio: horizontal ratio of the prescaler
174 * @pre_vratio: vertical ratio of the prescaler
175 * @pre_dst_width: the prescaler's destination width
176 * @pre_dst_height: the prescaler's destination height
177 * @scaleup_h: flag indicating scaling up horizontally
178 * @scaleup_v: flag indicating scaling up vertically
179 * @main_hratio: the main scaler's horizontal ratio
180 * @main_vratio: the main scaler's vertical ratio
181 * @real_width: source width - offset
182 * @real_height: source height - offset
183 * @copy_mode: flag set if one-to-one mode is used, i.e. no scaling
184 * and color format conversion
185 */
186struct fimc_scaler {
187 u32 enabled;
188 u32 hfactor;
189 u32 vfactor;
190 u32 pre_hratio;
191 u32 pre_vratio;
192 u32 pre_dst_width;
193 u32 pre_dst_height;
194 u32 scaleup_h;
195 u32 scaleup_v;
196 u32 main_hratio;
197 u32 main_vratio;
198 u32 real_width;
199 u32 real_height;
200 u32 copy_mode;
201};
202
203/**
204 * struct fimc_addr - the FIMC physical address set for DMA
205 *
206 * @y: luminance plane physical address
207 * @cb: Cb plane physical address
208 * @cr: Cr plane physical address
209 */
210struct fimc_addr {
211 u32 y;
212 u32 cb;
213 u32 cr;
214};
215
216/**
217 * struct fimc_vid_buffer - the driver's video buffer
218 * @vb: v4l videobuf buffer
219 */
220struct fimc_vid_buffer {
221 struct videobuf_buffer vb;
222};
223
224/**
225 * struct fimc_frame - input/output frame format properties
226 *
227 * @f_width: image full width (virtual screen size)
228 * @f_height: image full height (virtual screen size)
229 * @o_width: original image width as set by S_FMT
230 * @o_height: original image height as set by S_FMT
231 * @offs_h: image horizontal pixel offset
232 * @offs_v: image vertical pixel offset
233 * @width: image pixel width
234 * @height: image pixel weight
235 * @paddr: image frame buffer physical addresses
236 * @buf_cnt: number of buffers depending on a color format
237 * @size: image size in bytes
238 * @color: color format
239 * @dma_offset: DMA offset in bytes
240 */
241struct fimc_frame {
242 u32 f_width;
243 u32 f_height;
244 u32 o_width;
245 u32 o_height;
246 u32 offs_h;
247 u32 offs_v;
248 u32 width;
249 u32 height;
250 u32 size;
251 struct fimc_addr paddr;
252 struct fimc_dma_offset dma_offset;
253 struct fimc_fmt *fmt;
254};
255
256/**
257 * struct fimc_m2m_device - v4l2 memory-to-memory device data
258 * @vfd: the video device node for v4l2 m2m mode
259 * @v4l2_dev: v4l2 device for m2m mode
260 * @m2m_dev: v4l2 memory-to-memory device data
261 * @ctx: hardware context data
262 * @refcnt: the reference counter
263 */
264struct fimc_m2m_device {
265 struct video_device *vfd;
266 struct v4l2_device v4l2_dev;
267 struct v4l2_m2m_dev *m2m_dev;
268 struct fimc_ctx *ctx;
269 int refcnt;
270};
271
272/**
273 * struct samsung_fimc_variant - camera interface variant information
274 *
275 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
276 * @has_inp_rot: set if has input rotator
277 * @has_out_rot: set if has output rotator
278 * @min_inp_pixsize: minimum input pixel size
279 * @min_out_pixsize: minimum output pixel size
280 * @scaler_en_w: maximum input pixel width when the scaler is enabled
281 * @scaler_dis_w: maximum input pixel width when the scaler is disabled
282 * @in_rot_en_h: maximum input width when the input rotator is used
283 * @in_rot_dis_w: maximum input width when the input rotator is used
284 * @out_rot_en_w: maximum output width for the output rotator enabled
285 * @out_rot_dis_w: maximum output width for the output rotator enabled
286 */
287struct samsung_fimc_variant {
288 unsigned int pix_hoff:1;
289 unsigned int has_inp_rot:1;
290 unsigned int has_out_rot:1;
291
292 u16 min_inp_pixsize;
293 u16 min_out_pixsize;
294 u16 scaler_en_w;
295 u16 scaler_dis_w;
296 u16 in_rot_en_h;
297 u16 in_rot_dis_w;
298 u16 out_rot_en_w;
299 u16 out_rot_dis_w;
300};
301
302/**
303 * struct samsung_fimc_driverdata - per-device type driver data for init time.
304 *
305 * @variant: the variant information for this driver.
306 * @dev_cnt: number of fimc sub-devices available in SoC
307 */
308struct samsung_fimc_driverdata {
309 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
310 int devs_cnt;
311};
312
313struct fimc_ctx;
314
315/**
316 * struct fimc_subdev - abstraction for a FIMC entity
317 *
318 * @slock: the spinlock protecting this data structure
319 * @lock: the mutex protecting this data structure
320 * @pdev: pointer to the FIMC platform device
321 * @id: FIMC device index (0..2)
322 * @clock[]: the clocks required for FIMC operation
323 * @regs: the mapped hardware registers
324 * @regs_res: the resource claimed for IO registers
325 * @irq: interrupt number of the FIMC subdevice
326 * @irqlock: spinlock protecting videbuffer queue
327 * @m2m: memory-to-memory V4L2 device information
328 * @state: the FIMC device state flags
329 */
330struct fimc_dev {
331 spinlock_t slock;
332 struct mutex lock;
333 struct platform_device *pdev;
334 struct samsung_fimc_variant *variant;
335 int id;
336 struct clk *clock[NUM_FIMC_CLOCKS];
337 void __iomem *regs;
338 struct resource *regs_res;
339 int irq;
340 spinlock_t irqlock;
341 struct workqueue_struct *work_queue;
342 struct fimc_m2m_device m2m;
343 unsigned long state;
344};
345
346/**
347 * fimc_ctx - the device context data
348 *
349 * @lock: mutex protecting this data structure
350 * @s_frame: source frame properties
351 * @d_frame: destination frame properties
352 * @out_order_1p: output 1-plane YCBCR order
353 * @out_order_2p: output 2-plane YCBCR order
354 * @in_order_1p input 1-plane YCBCR order
355 * @in_order_2p: input 2-plane YCBCR order
356 * @in_path: input mode (DMA or camera)
357 * @out_path: output mode (DMA or FIFO)
358 * @scaler: image scaler properties
359 * @effect: image effect
360 * @rotation: image clockwise rotation in degrees
361 * @flip: image flip mode
362 * @flags: an additional flags for image conversion
363 * @state: flags to keep track of user configuration
364 * @fimc_dev: the FIMC device this context applies to
365 * @m2m_ctx: memory-to-memory device context
366 */
367struct fimc_ctx {
368 spinlock_t slock;
369 struct fimc_frame s_frame;
370 struct fimc_frame d_frame;
371 u32 out_order_1p;
372 u32 out_order_2p;
373 u32 in_order_1p;
374 u32 in_order_2p;
375 enum fimc_datapath in_path;
376 enum fimc_datapath out_path;
377 struct fimc_scaler scaler;
378 struct fimc_effect effect;
379 int rotation;
380 u32 flip;
381 u32 flags;
382 u32 state;
383 struct fimc_dev *fimc_dev;
384 struct v4l2_m2m_ctx *m2m_ctx;
385};
386
387
388static inline int tiled_fmt(struct fimc_fmt *fmt)
389{
390 return 0;
391}
392
393static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
394{
395 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
396 cfg |= S5P_CIGCTRL_IRQ_CLR;
397 writel(cfg, dev->regs + S5P_CIGCTRL);
398}
399
400static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
401{
402 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
403 cfg |= S5P_CISCCTRL_SCALERSTART;
404 writel(cfg, dev->regs + S5P_CISCCTRL);
405}
406
407static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
408{
409 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
410 cfg &= ~S5P_CISCCTRL_SCALERSTART;
411 writel(cfg, dev->regs + S5P_CISCCTRL);
412}
413
414static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
415{
416 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
417 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
418 writel(cfg, dev->regs + S5P_CIIMGCPT);
419}
420
421static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
422{
423 u32 cfg = readl(dev->regs + S5P_MSCTRL);
424 cfg |= S5P_MSCTRL_ENVID;
425 writel(cfg, dev->regs + S5P_MSCTRL);
426}
427
428static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
429{
430 u32 cfg = readl(dev->regs + S5P_MSCTRL);
431 cfg &= ~S5P_MSCTRL_ENVID;
432 writel(cfg, dev->regs + S5P_MSCTRL);
433}
434
435static inline struct fimc_frame *ctx_m2m_get_frame(struct fimc_ctx *ctx,
436 enum v4l2_buf_type type)
437{
438 struct fimc_frame *frame;
439
440 if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
441 frame = &ctx->s_frame;
442 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
443 frame = &ctx->d_frame;
444 } else {
445 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
446 "Wrong buffer/video queue type (%d)\n", type);
447 return ERR_PTR(-EINVAL);
448 }
449
450 return frame;
451}
452
453/* -----------------------------------------------------*/
454/* fimc-reg.c */
455void fimc_hw_reset(struct fimc_dev *dev);
456void fimc_hw_set_rotation(struct fimc_ctx *ctx);
457void fimc_hw_set_target_format(struct fimc_ctx *ctx);
458void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
459void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
460void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
461void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
462void fimc_hw_set_scaler(struct fimc_ctx *ctx);
463void fimc_hw_en_capture(struct fimc_ctx *ctx);
464void fimc_hw_set_effect(struct fimc_ctx *ctx);
465void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
466void fimc_hw_set_input_path(struct fimc_ctx *ctx);
467void fimc_hw_set_output_path(struct fimc_ctx *ctx);
468void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
469void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
470
471#endif /* FIMC_CORE_H_ */
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
new file mode 100644
index 000000000000..5570f1ce0c9c
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -0,0 +1,527 @@
1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
16
17#include "fimc-core.h"
18
19
20void fimc_hw_reset(struct fimc_dev *dev)
21{
22 u32 cfg;
23
24 cfg = readl(dev->regs + S5P_CISRCFMT);
25 cfg |= S5P_CISRCFMT_ITU601_8BIT;
26 writel(cfg, dev->regs + S5P_CISRCFMT);
27
28 /* Software reset. */
29 cfg = readl(dev->regs + S5P_CIGCTRL);
30 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
31 writel(cfg, dev->regs + S5P_CIGCTRL);
32 msleep(1);
33
34 cfg = readl(dev->regs + S5P_CIGCTRL);
35 cfg &= ~S5P_CIGCTRL_SWRST;
36 writel(cfg, dev->regs + S5P_CIGCTRL);
37
38}
39
40void fimc_hw_set_rotation(struct fimc_ctx *ctx)
41{
42 u32 cfg, flip;
43 struct fimc_dev *dev = ctx->fimc_dev;
44
45 cfg = readl(dev->regs + S5P_CITRGFMT);
46 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90);
47
48 flip = readl(dev->regs + S5P_MSCTRL);
49 flip &= ~S5P_MSCTRL_FLIP_MASK;
50
51 /*
52 * The input and output rotator cannot work simultaneously.
53 * Use the output rotator in output DMA mode or the input rotator
54 * in direct fifo output mode.
55 */
56 if (ctx->rotation == 90 || ctx->rotation == 270) {
57 if (ctx->out_path == FIMC_LCDFIFO) {
58 cfg |= S5P_CITRGFMT_INROT90;
59 if (ctx->rotation == 270)
60 flip |= S5P_MSCTRL_FLIP_180;
61 } else {
62 cfg |= S5P_CITRGFMT_OUTROT90;
63 if (ctx->rotation == 270)
64 cfg |= S5P_CITRGFMT_FLIP_180;
65 }
66 } else if (ctx->rotation == 180) {
67 if (ctx->out_path == FIMC_LCDFIFO)
68 flip |= S5P_MSCTRL_FLIP_180;
69 else
70 cfg |= S5P_CITRGFMT_FLIP_180;
71 }
72 if (ctx->rotation == 180 || ctx->rotation == 270)
73 writel(flip, dev->regs + S5P_MSCTRL);
74 writel(cfg, dev->regs + S5P_CITRGFMT);
75}
76
77static u32 fimc_hw_get_in_flip(u32 ctx_flip)
78{
79 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
80
81 switch (ctx_flip) {
82 case FLIP_X_AXIS:
83 flip = S5P_MSCTRL_FLIP_X_MIRROR;
84 break;
85 case FLIP_Y_AXIS:
86 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
87 break;
88 case FLIP_XY_AXIS:
89 flip = S5P_MSCTRL_FLIP_180;
90 break;
91 }
92
93 return flip;
94}
95
96static u32 fimc_hw_get_target_flip(u32 ctx_flip)
97{
98 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
99
100 switch (ctx_flip) {
101 case FLIP_X_AXIS:
102 flip = S5P_CITRGFMT_FLIP_X_MIRROR;
103 break;
104 case FLIP_Y_AXIS:
105 flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
106 break;
107 case FLIP_XY_AXIS:
108 flip = S5P_CITRGFMT_FLIP_180;
109 break;
110 case FLIP_NONE:
111 break;
112
113 }
114 return flip;
115}
116
117void fimc_hw_set_target_format(struct fimc_ctx *ctx)
118{
119 u32 cfg;
120 struct fimc_dev *dev = ctx->fimc_dev;
121 struct fimc_frame *frame = &ctx->d_frame;
122
123 dbg("w= %d, h= %d color: %d", frame->width,
124 frame->height, frame->fmt->color);
125
126 cfg = readl(dev->regs + S5P_CITRGFMT);
127 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
128 S5P_CITRGFMT_VSIZE_MASK);
129
130 switch (frame->fmt->color) {
131 case S5P_FIMC_RGB565:
132 case S5P_FIMC_RGB666:
133 case S5P_FIMC_RGB888:
134 cfg |= S5P_CITRGFMT_RGB;
135 break;
136 case S5P_FIMC_YCBCR420:
137 cfg |= S5P_CITRGFMT_YCBCR420;
138 break;
139 case S5P_FIMC_YCBYCR422:
140 case S5P_FIMC_YCRYCB422:
141 case S5P_FIMC_CBYCRY422:
142 case S5P_FIMC_CRYCBY422:
143 if (frame->fmt->planes_cnt == 1)
144 cfg |= S5P_CITRGFMT_YCBCR422_1P;
145 else
146 cfg |= S5P_CITRGFMT_YCBCR422;
147 break;
148 default:
149 break;
150 }
151
152 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
153 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
154
155 if (ctx->rotation == 0) {
156 cfg &= ~S5P_CITRGFMT_FLIP_MASK;
157 cfg |= fimc_hw_get_target_flip(ctx->flip);
158 }
159 writel(cfg, dev->regs + S5P_CITRGFMT);
160
161 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
162 cfg |= (frame->width * frame->height);
163 writel(cfg, dev->regs + S5P_CITAREA);
164}
165
166static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
167{
168 struct fimc_dev *dev = ctx->fimc_dev;
169 struct fimc_frame *frame = &ctx->d_frame;
170 u32 cfg = 0;
171
172 if (ctx->rotation == 90 || ctx->rotation == 270) {
173 cfg |= S5P_ORIG_SIZE_HOR(frame->f_height);
174 cfg |= S5P_ORIG_SIZE_VER(frame->f_width);
175 } else {
176 cfg |= S5P_ORIG_SIZE_HOR(frame->f_width);
177 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
178 }
179 writel(cfg, dev->regs + S5P_ORGOSIZE);
180}
181
182void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
183{
184 u32 cfg;
185 struct fimc_dev *dev = ctx->fimc_dev;
186 struct fimc_frame *frame = &ctx->d_frame;
187 struct fimc_dma_offset *offset = &frame->dma_offset;
188
189 /* Set the input dma offsets. */
190 cfg = 0;
191 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
192 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
193 writel(cfg, dev->regs + S5P_CIOYOFF);
194
195 cfg = 0;
196 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
197 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
198 writel(cfg, dev->regs + S5P_CIOCBOFF);
199
200 cfg = 0;
201 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
202 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
203 writel(cfg, dev->regs + S5P_CIOCROFF);
204
205 fimc_hw_set_out_dma_size(ctx);
206
207 /* Configure chroma components order. */
208 cfg = readl(dev->regs + S5P_CIOCTRL);
209
210 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
211 S5P_CIOCTRL_YCBCR_PLANE_MASK);
212
213 if (frame->fmt->planes_cnt == 1)
214 cfg |= ctx->out_order_1p;
215 else if (frame->fmt->planes_cnt == 2)
216 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
217 else if (frame->fmt->planes_cnt == 3)
218 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
219
220 writel(cfg, dev->regs + S5P_CIOCTRL);
221}
222
223static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
224{
225 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
226 if (enable)
227 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
228 else
229 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
230 writel(cfg, dev->regs + S5P_ORGISIZE);
231}
232
233void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
234{
235 unsigned long flags;
236 u32 cfg;
237
238 spin_lock_irqsave(&dev->slock, flags);
239
240 cfg = readl(dev->regs + S5P_CIOCTRL);
241 if (enable)
242 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
243 else
244 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
245 writel(cfg, dev->regs + S5P_CIOCTRL);
246
247 spin_unlock_irqrestore(&dev->slock, flags);
248}
249
250void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
251{
252 struct fimc_dev *dev = ctx->fimc_dev;
253 struct fimc_scaler *sc = &ctx->scaler;
254 u32 cfg = 0, shfactor;
255
256 shfactor = 10 - (sc->hfactor + sc->vfactor);
257
258 cfg |= S5P_CISCPRERATIO_SHFACTOR(shfactor);
259 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
260 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
261 writel(cfg, dev->regs + S5P_CISCPRERATIO);
262
263 cfg = 0;
264 cfg |= S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
265 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
266 writel(cfg, dev->regs + S5P_CISCPREDST);
267}
268
269void fimc_hw_set_scaler(struct fimc_ctx *ctx)
270{
271 struct fimc_dev *dev = ctx->fimc_dev;
272 struct fimc_scaler *sc = &ctx->scaler;
273 struct fimc_frame *src_frame = &ctx->s_frame;
274 struct fimc_frame *dst_frame = &ctx->d_frame;
275 u32 cfg = 0;
276
277 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
278 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
279
280 if (!sc->enabled)
281 cfg |= S5P_CISCCTRL_SCALERBYPASS;
282
283 if (sc->scaleup_h)
284 cfg |= S5P_CISCCTRL_SCALEUP_H;
285
286 if (sc->scaleup_v)
287 cfg |= S5P_CISCCTRL_SCALEUP_V;
288
289 if (sc->copy_mode)
290 cfg |= S5P_CISCCTRL_ONE2ONE;
291
292
293 if (ctx->in_path == FIMC_DMA) {
294 if (src_frame->fmt->color == S5P_FIMC_RGB565)
295 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
296 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
297 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
298 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
299 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
300 }
301
302 if (ctx->out_path == FIMC_DMA) {
303 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
304 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
305 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
306 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
307 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
308 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
309 } else {
310 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
311
312 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
313 cfg |= S5P_CISCCTRL_INTERLACE;
314 }
315
316 dbg("main_hratio= 0x%X main_vratio= 0x%X",
317 sc->main_hratio, sc->main_vratio);
318
319 cfg |= S5P_CISCCTRL_SC_HORRATIO(sc->main_hratio);
320 cfg |= S5P_CISCCTRL_SC_VERRATIO(sc->main_vratio);
321
322 writel(cfg, dev->regs + S5P_CISCCTRL);
323}
324
325void fimc_hw_en_capture(struct fimc_ctx *ctx)
326{
327 struct fimc_dev *dev = ctx->fimc_dev;
328 u32 cfg;
329
330 cfg = readl(dev->regs + S5P_CIIMGCPT);
331 /* One shot mode for output DMA or freerun for FIFO. */
332 if (ctx->out_path == FIMC_DMA)
333 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE;
334 else
335 cfg &= ~S5P_CIIMGCPT_CPT_FREN_ENABLE;
336
337 if (ctx->scaler.enabled)
338 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
339
340 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
341}
342
343void fimc_hw_set_effect(struct fimc_ctx *ctx)
344{
345 struct fimc_dev *dev = ctx->fimc_dev;
346 struct fimc_effect *effect = &ctx->effect;
347 u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
348
349 cfg |= effect->type;
350
351 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
352 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
353 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
354 }
355
356 writel(cfg, dev->regs + S5P_CIIMGEFF);
357}
358
359static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
360{
361 struct fimc_dev *dev = ctx->fimc_dev;
362 struct fimc_frame *frame = &ctx->s_frame;
363 u32 cfg_o = 0;
364 u32 cfg_r = 0;
365
366 if (FIMC_LCDFIFO == ctx->out_path)
367 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
368
369 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
370 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
371 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
372 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
373
374 writel(cfg_o, dev->regs + S5P_ORGISIZE);
375 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
376}
377
378void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
379{
380 struct fimc_dev *dev = ctx->fimc_dev;
381 struct fimc_frame *frame = &ctx->s_frame;
382 struct fimc_dma_offset *offset = &frame->dma_offset;
383 u32 cfg = 0;
384
385 /* Set the pixel offsets. */
386 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
387 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
388 writel(cfg, dev->regs + S5P_CIIYOFF);
389
390 cfg = 0;
391 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
392 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
393 writel(cfg, dev->regs + S5P_CIICBOFF);
394
395 cfg = 0;
396 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
397 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
398 writel(cfg, dev->regs + S5P_CIICROFF);
399
400 /* Input original and real size. */
401 fimc_hw_set_in_dma_size(ctx);
402
403 /* Autoload is used currently only in FIFO mode. */
404 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
405
406 /* Set the input DMA to process single frame only. */
407 cfg = readl(dev->regs + S5P_MSCTRL);
408 cfg &= ~(S5P_MSCTRL_FLIP_MASK
409 | S5P_MSCTRL_INFORMAT_MASK
410 | S5P_MSCTRL_IN_BURST_COUNT_MASK
411 | S5P_MSCTRL_INPUT_MASK
412 | S5P_MSCTRL_C_INT_IN_MASK
413 | S5P_MSCTRL_2P_IN_ORDER_MASK);
414
415 cfg |= (S5P_MSCTRL_FRAME_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY);
416
417 switch (frame->fmt->color) {
418 case S5P_FIMC_RGB565:
419 case S5P_FIMC_RGB666:
420 case S5P_FIMC_RGB888:
421 cfg |= S5P_MSCTRL_INFORMAT_RGB;
422 break;
423 case S5P_FIMC_YCBCR420:
424 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
425
426 if (frame->fmt->planes_cnt == 2)
427 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
428 else
429 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
430
431 break;
432 case S5P_FIMC_YCBYCR422:
433 case S5P_FIMC_YCRYCB422:
434 case S5P_FIMC_CBYCRY422:
435 case S5P_FIMC_CRYCBY422:
436 if (frame->fmt->planes_cnt == 1) {
437 cfg |= ctx->in_order_1p
438 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
439 } else {
440 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
441
442 if (frame->fmt->planes_cnt == 2)
443 cfg |= ctx->in_order_2p
444 | S5P_MSCTRL_C_INT_IN_2PLANE;
445 else
446 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
447 }
448 break;
449 default:
450 break;
451 }
452
453 /*
454 * Input DMA flip mode (and rotation).
455 * Do not allow simultaneous rotation and flipping.
456 */
457 if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
458 cfg |= fimc_hw_get_in_flip(ctx->flip);
459
460 writel(cfg, dev->regs + S5P_MSCTRL);
461
462 /* Input/output DMA linear/tiled mode. */
463 cfg = readl(dev->regs + S5P_CIDMAPARAM);
464 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
465
466 if (tiled_fmt(ctx->s_frame.fmt))
467 cfg |= S5P_CIDMAPARAM_R_64X32;
468
469 if (tiled_fmt(ctx->d_frame.fmt))
470 cfg |= S5P_CIDMAPARAM_W_64X32;
471
472 writel(cfg, dev->regs + S5P_CIDMAPARAM);
473}
474
475
476void fimc_hw_set_input_path(struct fimc_ctx *ctx)
477{
478 struct fimc_dev *dev = ctx->fimc_dev;
479
480 u32 cfg = readl(dev->regs + S5P_MSCTRL);
481 cfg &= ~S5P_MSCTRL_INPUT_MASK;
482
483 if (ctx->in_path == FIMC_DMA)
484 cfg |= S5P_MSCTRL_INPUT_MEMORY;
485 else
486 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
487
488 writel(cfg, dev->regs + S5P_MSCTRL);
489}
490
491void fimc_hw_set_output_path(struct fimc_ctx *ctx)
492{
493 struct fimc_dev *dev = ctx->fimc_dev;
494
495 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
496 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
497 if (ctx->out_path == FIMC_LCDFIFO)
498 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
499 writel(cfg, dev->regs + S5P_CISCCTRL);
500}
501
502void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
503{
504 u32 cfg = 0;
505
506 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
507 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
508 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
509
510 writel(paddr->y, dev->regs + S5P_CIIYSA0);
511 writel(paddr->cb, dev->regs + S5P_CIICBSA0);
512 writel(paddr->cr, dev->regs + S5P_CIICRSA0);
513
514 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
515 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
516}
517
518void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
519{
520 int i;
521 /* Set all the output register sets to point to single video buffer. */
522 for (i = 0; i < FIMC_MAX_OUT_BUFS; i++) {
523 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
524 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
525 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
526 }
527}
diff --git a/drivers/media/video/s5p-fimc/regs-fimc.h b/drivers/media/video/s5p-fimc/regs-fimc.h
new file mode 100644
index 000000000000..a3cfe824db00
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/regs-fimc.h
@@ -0,0 +1,293 @@
1/*
2 * Register definition file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef REGS_FIMC_H_
12#define REGS_FIMC_H_
13
14#define S5P_CIOYSA(__x) (0x18 + (__x) * 4)
15#define S5P_CIOCBSA(__x) (0x28 + (__x) * 4)
16#define S5P_CIOCRSA(__x) (0x38 + (__x) * 4)
17
18/* Input source format */
19#define S5P_CISRCFMT 0x00
20#define S5P_CISRCFMT_ITU601_8BIT (1 << 31)
21#define S5P_CISRCFMT_ITU601_16BIT (1 << 29)
22#define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14)
23#define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14)
24#define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14)
25#define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14)
26#define S5P_CISRCFMT_HSIZE(x) ((x) << 16)
27#define S5P_CISRCFMT_VSIZE(x) ((x) << 0)
28
29/* Window offset */
30#define S5P_CIWDOFST 0x04
31#define S5P_CIWDOFST_WINOFSEN (1 << 31)
32#define S5P_CIWDOFST_CLROVFIY (1 << 30)
33#define S5P_CIWDOFST_CLROVRLB (1 << 29)
34#define S5P_CIWDOFST_WINHOROFST_MASK (0x7ff << 16)
35#define S5P_CIWDOFST_CLROVFICB (1 << 15)
36#define S5P_CIWDOFST_CLROVFICR (1 << 14)
37#define S5P_CIWDOFST_WINHOROFST(x) ((x) << 16)
38#define S5P_CIWDOFST_WINVEROFST(x) ((x) << 0)
39#define S5P_CIWDOFST_WINVEROFST_MASK (0xfff << 0)
40
41/* Global control */
42#define S5P_CIGCTRL 0x08
43#define S5P_CIGCTRL_SWRST (1 << 31)
44#define S5P_CIGCTRL_CAMRST_A (1 << 30)
45#define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29)
46#define S5P_CIGCTRL_SELCAM_ITU_MASK (1 << 29)
47#define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27)
48#define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
49#define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
50#define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27)
51#define S5P_CIGCTRL_TESTPAT_MASK (3 << 27)
52#define S5P_CIGCTRL_TESTPAT_SHIFT (27)
53#define S5P_CIGCTRL_INVPOLPCLK (1 << 26)
54#define S5P_CIGCTRL_INVPOLVSYNC (1 << 25)
55#define S5P_CIGCTRL_INVPOLHREF (1 << 24)
56#define S5P_CIGCTRL_IRQ_OVFEN (1 << 22)
57#define S5P_CIGCTRL_HREF_MASK (1 << 21)
58#define S5P_CIGCTRL_IRQ_LEVEL (1 << 20)
59#define S5P_CIGCTRL_IRQ_CLR (1 << 19)
60#define S5P_CIGCTRL_IRQ_ENABLE (1 << 16)
61#define S5P_CIGCTRL_SHDW_DISABLE (1 << 12)
62#define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7)
63#define S5P_CIGCTRL_CAMIF_SELWB (1 << 6)
64#define S5P_CIGCTRL_INVPOLHSYNC (1 << 4)
65#define S5P_CIGCTRL_SELCAM_MIPI (1 << 3)
66#define S5P_CIGCTRL_INTERLACE (1 << 0)
67
68/* Window offset 2 */
69#define S5P_CIWDOFST2 0x14
70#define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16)
71#define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0)
72#define S5P_CIWDOFST2_HOROFF(x) ((x) << 16)
73#define S5P_CIWDOFST2_VEROFF(x) ((x) << 0)
74
75/* Output DMA Y plane start address */
76#define S5P_CIOYSA1 0x18
77#define S5P_CIOYSA2 0x1c
78#define S5P_CIOYSA3 0x20
79#define S5P_CIOYSA4 0x24
80
81/* Output DMA Cb plane start address */
82#define S5P_CIOCBSA1 0x28
83#define S5P_CIOCBSA2 0x2c
84#define S5P_CIOCBSA3 0x30
85#define S5P_CIOCBSA4 0x34
86
87/* Output DMA Cr plane start address */
88#define S5P_CIOCRSA1 0x38
89#define S5P_CIOCRSA2 0x3c
90#define S5P_CIOCRSA3 0x40
91#define S5P_CIOCRSA4 0x44
92
93/* Target image format */
94#define S5P_CITRGFMT 0x48
95#define S5P_CITRGFMT_INROT90 (1 << 31)
96#define S5P_CITRGFMT_YCBCR420 (0 << 29)
97#define S5P_CITRGFMT_YCBCR422 (1 << 29)
98#define S5P_CITRGFMT_YCBCR422_1P (2 << 29)
99#define S5P_CITRGFMT_RGB (3 << 29)
100#define S5P_CITRGFMT_FMT_MASK (3 << 29)
101#define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16)
102#define S5P_CITRGFMT_FLIP_SHIFT (14)
103#define S5P_CITRGFMT_FLIP_NORMAL (0 << 14)
104#define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14)
105#define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
106#define S5P_CITRGFMT_FLIP_180 (3 << 14)
107#define S5P_CITRGFMT_FLIP_MASK (3 << 14)
108#define S5P_CITRGFMT_OUTROT90 (1 << 13)
109#define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0)
110#define S5P_CITRGFMT_HSIZE(x) ((x) << 16)
111#define S5P_CITRGFMT_VSIZE(x) ((x) << 0)
112
113/* Output DMA control */
114#define S5P_CIOCTRL 0x4c
115#define S5P_CIOCTRL_ORDER422_MASK (3 << 0)
116#define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0)
117#define S5P_CIOCTRL_ORDER422_YCRYCB (1 << 0)
118#define S5P_CIOCTRL_ORDER422_CBYCRY (2 << 0)
119#define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0)
120#define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
121#define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3)
122#define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3)
123#define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
124#define S5P_CIOCTRL_ORDER2P_SHIFT (24)
125#define S5P_CIOCTRL_ORDER2P_MASK (3 << 24)
126#define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
127
128/* Pre-scaler control 1 */
129#define S5P_CISCPRERATIO 0x50
130#define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
131#define S5P_CISCPRERATIO_HOR(x) ((x) << 16)
132#define S5P_CISCPRERATIO_VER(x) ((x) << 0)
133
134#define S5P_CISCPREDST 0x54
135#define S5P_CISCPREDST_WIDTH(x) ((x) << 16)
136#define S5P_CISCPREDST_HEIGHT(x) ((x) << 0)
137
138/* Main scaler control */
139#define S5P_CISCCTRL 0x58
140#define S5P_CISCCTRL_SCALERBYPASS (1 << 31)
141#define S5P_CISCCTRL_SCALEUP_H (1 << 30)
142#define S5P_CISCCTRL_SCALEUP_V (1 << 29)
143#define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28)
144#define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27)
145#define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
146#define S5P_CISCCTRL_INTERLACE (1 << 25)
147#define S5P_CISCCTRL_SCALERSTART (1 << 15)
148#define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
149#define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
150#define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
151#define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13)
152#define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
153#define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
154#define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
155#define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
156#define S5P_CISCCTRL_RGB_EXT (1 << 10)
157#define S5P_CISCCTRL_ONE2ONE (1 << 9)
158#define S5P_CISCCTRL_SC_HORRATIO(x) ((x) << 16)
159#define S5P_CISCCTRL_SC_VERRATIO(x) ((x) << 0)
160
161/* Target area */
162#define S5P_CITAREA 0x5c
163#define S5P_CITAREA_MASK 0x0fffffff
164
165/* General status */
166#define S5P_CISTATUS 0x64
167#define S5P_CISTATUS_OVFIY (1 << 31)
168#define S5P_CISTATUS_OVFICB (1 << 30)
169#define S5P_CISTATUS_OVFICR (1 << 29)
170#define S5P_CISTATUS_VSYNC (1 << 28)
171#define S5P_CISTATUS_WINOFF_EN (1 << 25)
172#define S5P_CISTATUS_IMGCPT_EN (1 << 22)
173#define S5P_CISTATUS_IMGCPT_SCEN (1 << 21)
174#define S5P_CISTATUS_VSYNC_A (1 << 20)
175#define S5P_CISTATUS_VSYNC_B (1 << 19)
176#define S5P_CISTATUS_OVRLB (1 << 18)
177#define S5P_CISTATUS_FRAME_END (1 << 17)
178#define S5P_CISTATUS_LASTCAPT_END (1 << 16)
179#define S5P_CISTATUS_VVALID_A (1 << 15)
180#define S5P_CISTATUS_VVALID_B (1 << 14)
181
182/* Image capture control */
183#define S5P_CIIMGCPT 0xc0
184#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
185#define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30)
186#define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
187#define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
188
189/* Frame capture sequence */
190#define S5P_CICPTSEQ 0xc4
191
192/* Image effect */
193#define S5P_CIIMGEFF 0xd0
194#define S5P_CIIMGEFF_IE_DISABLE (0 << 30)
195#define S5P_CIIMGEFF_IE_ENABLE (1 << 30)
196#define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29)
197#define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29)
198#define S5P_CIIMGEFF_FIN_BYPASS (0 << 26)
199#define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26)
200#define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26)
201#define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
202#define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26)
203#define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
204#define S5P_CIIMGEFF_FIN_MASK (7 << 26)
205#define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
206#define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13)
207#define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0)
208
209/* Input DMA Y/Cb/Cr plane start address 0 */
210#define S5P_CIIYSA0 0xd4
211#define S5P_CIICBSA0 0xd8
212#define S5P_CIICRSA0 0xdc
213
214/* Real input DMA image size */
215#define S5P_CIREAL_ISIZE 0xf8
216#define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
217#define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
218#define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
219#define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
220
221
222/* Input DMA control */
223#define S5P_MSCTRL 0xfc
224#define S5P_MSCTRL_IN_BURST_COUNT_MASK (3 << 24)
225#define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
226#define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16
227#define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15)
228#define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15)
229#define S5P_MSCTRL_C_INT_IN_MASK (1 << 15)
230#define S5P_MSCTRL_FLIP_SHIFT 13
231#define S5P_MSCTRL_FLIP_MASK (3 << 13)
232#define S5P_MSCTRL_FLIP_NORMAL (0 << 13)
233#define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
234#define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
235#define S5P_MSCTRL_FLIP_180 (3 << 13)
236#define S5P_MSCTRL_ORDER422_SHIFT 4
237#define S5P_MSCTRL_ORDER422_CRYCBY (0 << 4)
238#define S5P_MSCTRL_ORDER422_YCRYCB (1 << 4)
239#define S5P_MSCTRL_ORDER422_CBYCRY (2 << 4)
240#define S5P_MSCTRL_ORDER422_YCBYCR (3 << 4)
241#define S5P_MSCTRL_ORDER422_MASK (3 << 4)
242#define S5P_MSCTRL_INPUT_EXTCAM (0 << 3)
243#define S5P_MSCTRL_INPUT_MEMORY (1 << 3)
244#define S5P_MSCTRL_INPUT_MASK (1 << 3)
245#define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
246#define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
247#define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
248#define S5P_MSCTRL_INFORMAT_RGB (3 << 1)
249#define S5P_MSCTRL_INFORMAT_MASK (3 << 1)
250#define S5P_MSCTRL_ENVID (1 << 0)
251#define S5P_MSCTRL_FRAME_COUNT(x) ((x) << 24)
252
253/* Input DMA Y/Cb/Cr plane start address 1 */
254#define S5P_CIIYSA1 0x144
255#define S5P_CIICBSA1 0x148
256#define S5P_CIICRSA1 0x14c
257
258/* Output DMA Y/Cb/Cr offset */
259#define S5P_CIOYOFF 0x168
260#define S5P_CIOCBOFF 0x16c
261#define S5P_CIOCROFF 0x170
262
263/* Input DMA Y/Cb/Cr offset */
264#define S5P_CIIYOFF 0x174
265#define S5P_CIICBOFF 0x178
266#define S5P_CIICROFF 0x17c
267
268#define S5P_CIO_OFFS_VER(x) ((x) << 16)
269#define S5P_CIO_OFFS_HOR(x) ((x) << 0)
270
271/* Input DMA original image size */
272#define S5P_ORGISIZE 0x180
273
274/* Output DMA original image size */
275#define S5P_ORGOSIZE 0x184
276
277#define S5P_ORIG_SIZE_VER(x) ((x) << 16)
278#define S5P_ORIG_SIZE_HOR(x) ((x) << 0)
279
280/* Real output DMA image size (extension register) */
281#define S5P_CIEXTEN 0x188
282
283#define S5P_CIDMAPARAM 0x18c
284#define S5P_CIDMAPARAM_R_LINEAR (0 << 29)
285#define S5P_CIDMAPARAM_R_64X32 (3 << 29)
286#define S5P_CIDMAPARAM_W_LINEAR (0 << 13)
287#define S5P_CIDMAPARAM_W_64X32 (3 << 13)
288#define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
289
290/* MIPI CSI image format */
291#define S5P_CSIIMGFMT 0x194
292
293#endif /* REGS_FIMC_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 11:10:26 -0500