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path: root/drivers/media/video/s5p-fimc/fimc-reg.c
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Diffstat (limited to 'drivers/media/video/s5p-fimc/fimc-reg.c')
-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.c616
1 files changed, 333 insertions, 283 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
index 15466d0529c1..1fc4ce8446f5 100644
--- a/drivers/media/video/s5p-fimc/fimc-reg.c
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -1,9 +1,8 @@
1/* 1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver 2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics 4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * 5 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -12,9 +11,9 @@
12 11
13#include <linux/io.h> 12#include <linux/io.h>
14#include <linux/delay.h> 13#include <linux/delay.h>
15#include <mach/map.h>
16#include <media/s5p_fimc.h> 14#include <media/s5p_fimc.h>
17 15
16#include "fimc-reg.h"
18#include "fimc-core.h" 17#include "fimc-core.h"
19 18
20 19
@@ -22,19 +21,19 @@ void fimc_hw_reset(struct fimc_dev *dev)
22{ 21{
23 u32 cfg; 22 u32 cfg;
24 23
25 cfg = readl(dev->regs + S5P_CISRCFMT); 24 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
26 cfg |= S5P_CISRCFMT_ITU601_8BIT; 25 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + S5P_CISRCFMT); 26 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
28 27
29 /* Software reset. */ 28 /* Software reset. */
30 cfg = readl(dev->regs + S5P_CIGCTRL); 29 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
31 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL); 30 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + S5P_CIGCTRL); 31 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
33 udelay(10); 32 udelay(10);
34 33
35 cfg = readl(dev->regs + S5P_CIGCTRL); 34 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
36 cfg &= ~S5P_CIGCTRL_SWRST; 35 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + S5P_CIGCTRL); 36 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
38 37
39 if (dev->variant->out_buf_count > 4) 38 if (dev->variant->out_buf_count > 4)
40 fimc_hw_set_dma_seq(dev, 0xF); 39 fimc_hw_set_dma_seq(dev, 0xF);
@@ -42,32 +41,32 @@ void fimc_hw_reset(struct fimc_dev *dev)
42 41
43static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx) 42static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
44{ 43{
45 u32 flip = S5P_MSCTRL_FLIP_NORMAL; 44 u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL;
46 45
47 if (ctx->hflip) 46 if (ctx->hflip)
48 flip = S5P_MSCTRL_FLIP_X_MIRROR; 47 flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR;
49 if (ctx->vflip) 48 if (ctx->vflip)
50 flip = S5P_MSCTRL_FLIP_Y_MIRROR; 49 flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR;
51 50
52 if (ctx->rotation <= 90) 51 if (ctx->rotation <= 90)
53 return flip; 52 return flip;
54 53
55 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180; 54 return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180;
56} 55}
57 56
58static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx) 57static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
59{ 58{
60 u32 flip = S5P_CITRGFMT_FLIP_NORMAL; 59 u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL;
61 60
62 if (ctx->hflip) 61 if (ctx->hflip)
63 flip |= S5P_CITRGFMT_FLIP_X_MIRROR; 62 flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR;
64 if (ctx->vflip) 63 if (ctx->vflip)
65 flip |= S5P_CITRGFMT_FLIP_Y_MIRROR; 64 flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR;
66 65
67 if (ctx->rotation <= 90) 66 if (ctx->rotation <= 90)
68 return flip; 67 return flip;
69 68
70 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180; 69 return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180;
71} 70}
72 71
73void fimc_hw_set_rotation(struct fimc_ctx *ctx) 72void fimc_hw_set_rotation(struct fimc_ctx *ctx)
@@ -75,9 +74,9 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
75 u32 cfg, flip; 74 u32 cfg, flip;
76 struct fimc_dev *dev = ctx->fimc_dev; 75 struct fimc_dev *dev = ctx->fimc_dev;
77 76
78 cfg = readl(dev->regs + S5P_CITRGFMT); 77 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
79 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 | 78 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
80 S5P_CITRGFMT_FLIP_180); 79 FIMC_REG_CITRGFMT_FLIP_180);
81 80
82 /* 81 /*
83 * The input and output rotator cannot work simultaneously. 82 * The input and output rotator cannot work simultaneously.
@@ -85,21 +84,21 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
85 * in direct fifo output mode. 84 * in direct fifo output mode.
86 */ 85 */
87 if (ctx->rotation == 90 || ctx->rotation == 270) { 86 if (ctx->rotation == 90 || ctx->rotation == 270) {
88 if (ctx->out_path == FIMC_LCDFIFO) 87 if (ctx->out_path == FIMC_IO_LCDFIFO)
89 cfg |= S5P_CITRGFMT_INROT90; 88 cfg |= FIMC_REG_CITRGFMT_INROT90;
90 else 89 else
91 cfg |= S5P_CITRGFMT_OUTROT90; 90 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
92 } 91 }
93 92
94 if (ctx->out_path == FIMC_DMA) { 93 if (ctx->out_path == FIMC_IO_DMA) {
95 cfg |= fimc_hw_get_target_flip(ctx); 94 cfg |= fimc_hw_get_target_flip(ctx);
96 writel(cfg, dev->regs + S5P_CITRGFMT); 95 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
97 } else { 96 } else {
98 /* LCD FIFO path */ 97 /* LCD FIFO path */
99 flip = readl(dev->regs + S5P_MSCTRL); 98 flip = readl(dev->regs + FIMC_REG_MSCTRL);
100 flip &= ~S5P_MSCTRL_FLIP_MASK; 99 flip &= ~FIMC_REG_MSCTRL_FLIP_MASK;
101 flip |= fimc_hw_get_in_flip(ctx); 100 flip |= fimc_hw_get_in_flip(ctx);
102 writel(flip, dev->regs + S5P_MSCTRL); 101 writel(flip, dev->regs + FIMC_REG_MSCTRL);
103 } 102 }
104} 103}
105 104
@@ -110,43 +109,40 @@ void fimc_hw_set_target_format(struct fimc_ctx *ctx)
110 struct fimc_frame *frame = &ctx->d_frame; 109 struct fimc_frame *frame = &ctx->d_frame;
111 110
112 dbg("w= %d, h= %d color: %d", frame->width, 111 dbg("w= %d, h= %d color: %d", frame->width,
113 frame->height, frame->fmt->color); 112 frame->height, frame->fmt->color);
114 113
115 cfg = readl(dev->regs + S5P_CITRGFMT); 114 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
116 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK | 115 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
117 S5P_CITRGFMT_VSIZE_MASK); 116 FIMC_REG_CITRGFMT_VSIZE_MASK);
118 117
119 switch (frame->fmt->color) { 118 switch (frame->fmt->color) {
120 case S5P_FIMC_RGB444...S5P_FIMC_RGB888: 119 case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
121 cfg |= S5P_CITRGFMT_RGB; 120 cfg |= FIMC_REG_CITRGFMT_RGB;
122 break; 121 break;
123 case S5P_FIMC_YCBCR420: 122 case FIMC_FMT_YCBCR420:
124 cfg |= S5P_CITRGFMT_YCBCR420; 123 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
125 break; 124 break;
126 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: 125 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
127 if (frame->fmt->colplanes == 1) 126 if (frame->fmt->colplanes == 1)
128 cfg |= S5P_CITRGFMT_YCBCR422_1P; 127 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
129 else 128 else
130 cfg |= S5P_CITRGFMT_YCBCR422; 129 cfg |= FIMC_REG_CITRGFMT_YCBCR422;
131 break; 130 break;
132 default: 131 default:
133 break; 132 break;
134 } 133 }
135 134
136 if (ctx->rotation == 90 || ctx->rotation == 270) { 135 if (ctx->rotation == 90 || ctx->rotation == 270)
137 cfg |= S5P_CITRGFMT_HSIZE(frame->height); 136 cfg |= (frame->height << 16) | frame->width;
138 cfg |= S5P_CITRGFMT_VSIZE(frame->width); 137 else
139 } else { 138 cfg |= (frame->width << 16) | frame->height;
140
141 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
142 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
143 }
144 139
145 writel(cfg, dev->regs + S5P_CITRGFMT); 140 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
146 141
147 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK; 142 cfg = readl(dev->regs + FIMC_REG_CITAREA);
143 cfg &= ~FIMC_REG_CITAREA_MASK;
148 cfg |= (frame->width * frame->height); 144 cfg |= (frame->width * frame->height);
149 writel(cfg, dev->regs + S5P_CITAREA); 145 writel(cfg, dev->regs + FIMC_REG_CITAREA);
150} 146}
151 147
152static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx) 148static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
@@ -155,87 +151,82 @@ static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
155 struct fimc_frame *frame = &ctx->d_frame; 151 struct fimc_frame *frame = &ctx->d_frame;
156 u32 cfg; 152 u32 cfg;
157 153
158 cfg = S5P_ORIG_SIZE_HOR(frame->f_width); 154 cfg = (frame->f_height << 16) | frame->f_width;
159 cfg |= S5P_ORIG_SIZE_VER(frame->f_height); 155 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
160 writel(cfg, dev->regs + S5P_ORGOSIZE);
161 156
162 /* Select color space conversion equation (HD/SD size).*/ 157 /* Select color space conversion equation (HD/SD size).*/
163 cfg = readl(dev->regs + S5P_CIGCTRL); 158 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
164 if (frame->f_width >= 1280) /* HD */ 159 if (frame->f_width >= 1280) /* HD */
165 cfg |= S5P_CIGCTRL_CSC_ITU601_709; 160 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
166 else /* SD */ 161 else /* SD */
167 cfg &= ~S5P_CIGCTRL_CSC_ITU601_709; 162 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
168 writel(cfg, dev->regs + S5P_CIGCTRL); 163 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
169 164
170} 165}
171 166
172void fimc_hw_set_out_dma(struct fimc_ctx *ctx) 167void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
173{ 168{
174 u32 cfg;
175 struct fimc_dev *dev = ctx->fimc_dev; 169 struct fimc_dev *dev = ctx->fimc_dev;
176 struct fimc_frame *frame = &ctx->d_frame; 170 struct fimc_frame *frame = &ctx->d_frame;
177 struct fimc_dma_offset *offset = &frame->dma_offset; 171 struct fimc_dma_offset *offset = &frame->dma_offset;
178 struct fimc_fmt *fmt = frame->fmt; 172 struct fimc_fmt *fmt = frame->fmt;
173 u32 cfg;
179 174
180 /* Set the input dma offsets. */ 175 /* Set the input dma offsets. */
181 cfg = 0; 176 cfg = (offset->y_v << 16) | offset->y_h;
182 cfg |= S5P_CIO_OFFS_HOR(offset->y_h); 177 writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
183 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
184 writel(cfg, dev->regs + S5P_CIOYOFF);
185 178
186 cfg = 0; 179 cfg = (offset->cb_v << 16) | offset->cb_h;
187 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h); 180 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
188 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
189 writel(cfg, dev->regs + S5P_CIOCBOFF);
190 181
191 cfg = 0; 182 cfg = (offset->cr_v << 16) | offset->cr_h;
192 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h); 183 writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
193 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
194 writel(cfg, dev->regs + S5P_CIOCROFF);
195 184
196 fimc_hw_set_out_dma_size(ctx); 185 fimc_hw_set_out_dma_size(ctx);
197 186
198 /* Configure chroma components order. */ 187 /* Configure chroma components order. */
199 cfg = readl(dev->regs + S5P_CIOCTRL); 188 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
200 189
201 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK | 190 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
202 S5P_CIOCTRL_YCBCR_PLANE_MASK | S5P_CIOCTRL_RGB16FMT_MASK); 191 FIMC_REG_CIOCTRL_ORDER422_MASK |
192 FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK |
193 FIMC_REG_CIOCTRL_RGB16FMT_MASK);
203 194
204 if (fmt->colplanes == 1) 195 if (fmt->colplanes == 1)
205 cfg |= ctx->out_order_1p; 196 cfg |= ctx->out_order_1p;
206 else if (fmt->colplanes == 2) 197 else if (fmt->colplanes == 2)
207 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE; 198 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
208 else if (fmt->colplanes == 3) 199 else if (fmt->colplanes == 3)
209 cfg |= S5P_CIOCTRL_YCBCR_3PLANE; 200 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
210 201
211 if (fmt->color == S5P_FIMC_RGB565) 202 if (fmt->color == FIMC_FMT_RGB565)
212 cfg |= S5P_CIOCTRL_RGB565; 203 cfg |= FIMC_REG_CIOCTRL_RGB565;
213 else if (fmt->color == S5P_FIMC_RGB555) 204 else if (fmt->color == FIMC_FMT_RGB555)
214 cfg |= S5P_CIOCTRL_ARGB1555; 205 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
215 else if (fmt->color == S5P_FIMC_RGB444) 206 else if (fmt->color == FIMC_FMT_RGB444)
216 cfg |= S5P_CIOCTRL_ARGB4444; 207 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
217 208
218 writel(cfg, dev->regs + S5P_CIOCTRL); 209 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
219} 210}
220 211
221static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable) 212static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
222{ 213{
223 u32 cfg = readl(dev->regs + S5P_ORGISIZE); 214 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
224 if (enable) 215 if (enable)
225 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN; 216 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
226 else 217 else
227 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN; 218 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
228 writel(cfg, dev->regs + S5P_ORGISIZE); 219 writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
229} 220}
230 221
231void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable) 222void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
232{ 223{
233 u32 cfg = readl(dev->regs + S5P_CIOCTRL); 224 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
234 if (enable) 225 if (enable)
235 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE; 226 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
236 else 227 else
237 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE; 228 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
238 writel(cfg, dev->regs + S5P_CIOCTRL); 229 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
239} 230}
240 231
241void fimc_hw_set_prescaler(struct fimc_ctx *ctx) 232void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
@@ -245,15 +236,13 @@ void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
245 u32 cfg, shfactor; 236 u32 cfg, shfactor;
246 237
247 shfactor = 10 - (sc->hfactor + sc->vfactor); 238 shfactor = 10 - (sc->hfactor + sc->vfactor);
239 cfg = shfactor << 28;
248 240
249 cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor); 241 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
250 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio); 242 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
251 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
252 writel(cfg, dev->regs + S5P_CISCPRERATIO);
253 243
254 cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width); 244 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
255 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height); 245 writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
256 writel(cfg, dev->regs + S5P_CISCPREDST);
257} 246}
258 247
259static void fimc_hw_set_scaler(struct fimc_ctx *ctx) 248static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
@@ -263,93 +252,95 @@ static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
263 struct fimc_frame *src_frame = &ctx->s_frame; 252 struct fimc_frame *src_frame = &ctx->s_frame;
264 struct fimc_frame *dst_frame = &ctx->d_frame; 253 struct fimc_frame *dst_frame = &ctx->d_frame;
265 254
266 u32 cfg = readl(dev->regs + S5P_CISCCTRL); 255 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
267 256
268 cfg &= ~(S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE | 257 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
269 S5P_CISCCTRL_SCALEUP_H | S5P_CISCCTRL_SCALEUP_V | 258 FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V |
270 S5P_CISCCTRL_SCALERBYPASS | S5P_CISCCTRL_ONE2ONE | 259 FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE |
271 S5P_CISCCTRL_INRGB_FMT_MASK | S5P_CISCCTRL_OUTRGB_FMT_MASK | 260 FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK |
272 S5P_CISCCTRL_INTERLACE | S5P_CISCCTRL_RGB_EXT); 261 FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT);
273 262
274 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW)) 263 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
275 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE); 264 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
265 FIMC_REG_CISCCTRL_CSCY2R_WIDE);
276 266
277 if (!sc->enabled) 267 if (!sc->enabled)
278 cfg |= S5P_CISCCTRL_SCALERBYPASS; 268 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
279 269
280 if (sc->scaleup_h) 270 if (sc->scaleup_h)
281 cfg |= S5P_CISCCTRL_SCALEUP_H; 271 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
282 272
283 if (sc->scaleup_v) 273 if (sc->scaleup_v)
284 cfg |= S5P_CISCCTRL_SCALEUP_V; 274 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
285 275
286 if (sc->copy_mode) 276 if (sc->copy_mode)
287 cfg |= S5P_CISCCTRL_ONE2ONE; 277 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
288 278
289 if (ctx->in_path == FIMC_DMA) { 279 if (ctx->in_path == FIMC_IO_DMA) {
290 switch (src_frame->fmt->color) { 280 switch (src_frame->fmt->color) {
291 case S5P_FIMC_RGB565: 281 case FIMC_FMT_RGB565:
292 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565; 282 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
293 break; 283 break;
294 case S5P_FIMC_RGB666: 284 case FIMC_FMT_RGB666:
295 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666; 285 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
296 break; 286 break;
297 case S5P_FIMC_RGB888: 287 case FIMC_FMT_RGB888:
298 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888; 288 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
299 break; 289 break;
300 } 290 }
301 } 291 }
302 292
303 if (ctx->out_path == FIMC_DMA) { 293 if (ctx->out_path == FIMC_IO_DMA) {
304 u32 color = dst_frame->fmt->color; 294 u32 color = dst_frame->fmt->color;
305 295
306 if (color >= S5P_FIMC_RGB444 && color <= S5P_FIMC_RGB565) 296 if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
307 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565; 297 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
308 else if (color == S5P_FIMC_RGB666) 298 else if (color == FIMC_FMT_RGB666)
309 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666; 299 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
310 else if (color == S5P_FIMC_RGB888) 300 else if (color == FIMC_FMT_RGB888)
311 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888; 301 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
312 } else { 302 } else {
313 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888; 303 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
314 304
315 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED) 305 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
316 cfg |= S5P_CISCCTRL_INTERLACE; 306 cfg |= FIMC_REG_CISCCTRL_INTERLACE;
317 } 307 }
318 308
319 writel(cfg, dev->regs + S5P_CISCCTRL); 309 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
320} 310}
321 311
322void fimc_hw_set_mainscaler(struct fimc_ctx *ctx) 312void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
323{ 313{
324 struct fimc_dev *dev = ctx->fimc_dev; 314 struct fimc_dev *dev = ctx->fimc_dev;
325 struct samsung_fimc_variant *variant = dev->variant; 315 struct fimc_variant *variant = dev->variant;
326 struct fimc_scaler *sc = &ctx->scaler; 316 struct fimc_scaler *sc = &ctx->scaler;
327 u32 cfg; 317 u32 cfg;
328 318
329 dbg("main_hratio= 0x%X main_vratio= 0x%X", 319 dbg("main_hratio= 0x%X main_vratio= 0x%X",
330 sc->main_hratio, sc->main_vratio); 320 sc->main_hratio, sc->main_vratio);
331 321
332 fimc_hw_set_scaler(ctx); 322 fimc_hw_set_scaler(ctx);
333 323
334 cfg = readl(dev->regs + S5P_CISCCTRL); 324 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
335 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK); 325 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
326 FIMC_REG_CISCCTRL_MVRATIO_MASK);
336 327
337 if (variant->has_mainscaler_ext) { 328 if (variant->has_mainscaler_ext) {
338 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio); 329 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
339 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio); 330 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
340 writel(cfg, dev->regs + S5P_CISCCTRL); 331 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
341 332
342 cfg = readl(dev->regs + S5P_CIEXTEN); 333 cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
343 334
344 cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK | 335 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
345 S5P_CIEXTEN_MHRATIO_EXT_MASK); 336 FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK);
346 cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio); 337 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
347 cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio); 338 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
348 writel(cfg, dev->regs + S5P_CIEXTEN); 339 writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
349 } else { 340 } else {
350 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio); 341 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
351 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio); 342 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
352 writel(cfg, dev->regs + S5P_CISCCTRL); 343 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
353 } 344 }
354} 345}
355 346
@@ -357,40 +348,41 @@ void fimc_hw_en_capture(struct fimc_ctx *ctx)
357{ 348{
358 struct fimc_dev *dev = ctx->fimc_dev; 349 struct fimc_dev *dev = ctx->fimc_dev;
359 350
360 u32 cfg = readl(dev->regs + S5P_CIIMGCPT); 351 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
361 352
362 if (ctx->out_path == FIMC_DMA) { 353 if (ctx->out_path == FIMC_IO_DMA) {
363 /* one shot mode */ 354 /* one shot mode */
364 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN; 355 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE |
356 FIMC_REG_CIIMGCPT_IMGCPTEN;
365 } else { 357 } else {
366 /* Continuous frame capture mode (freerun). */ 358 /* Continuous frame capture mode (freerun). */
367 cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE | 359 cfg &= ~(FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE |
368 S5P_CIIMGCPT_CPT_FRMOD_CNT); 360 FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT);
369 cfg |= S5P_CIIMGCPT_IMGCPTEN; 361 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
370 } 362 }
371 363
372 if (ctx->scaler.enabled) 364 if (ctx->scaler.enabled)
373 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC; 365 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
374 366
375 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT); 367 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
368 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
376} 369}
377 370
378void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active) 371void fimc_hw_set_effect(struct fimc_ctx *ctx)
379{ 372{
380 struct fimc_dev *dev = ctx->fimc_dev; 373 struct fimc_dev *dev = ctx->fimc_dev;
381 struct fimc_effect *effect = &ctx->effect; 374 struct fimc_effect *effect = &ctx->effect;
382 u32 cfg = 0; 375 u32 cfg = 0;
383 376
384 if (active) { 377 if (effect->type != FIMC_REG_CIIMGEFF_FIN_BYPASS) {
385 cfg |= S5P_CIIMGEFF_IE_SC_AFTER | S5P_CIIMGEFF_IE_ENABLE; 378 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
379 FIMC_REG_CIIMGEFF_IE_ENABLE;
386 cfg |= effect->type; 380 cfg |= effect->type;
387 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) { 381 if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY)
388 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb); 382 cfg |= (effect->pat_cb << 13) | effect->pat_cr;
389 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
390 }
391 } 383 }
392 384
393 writel(cfg, dev->regs + S5P_CIIMGEFF); 385 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
394} 386}
395 387
396void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx) 388void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
@@ -402,10 +394,10 @@ void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
402 if (!(frame->fmt->flags & FMT_HAS_ALPHA)) 394 if (!(frame->fmt->flags & FMT_HAS_ALPHA))
403 return; 395 return;
404 396
405 cfg = readl(dev->regs + S5P_CIOCTRL); 397 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
406 cfg &= ~S5P_CIOCTRL_ALPHA_OUT_MASK; 398 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
407 cfg |= (frame->alpha << 4); 399 cfg |= (frame->alpha << 4);
408 writel(cfg, dev->regs + S5P_CIOCTRL); 400 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
409} 401}
410 402
411static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx) 403static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
@@ -415,16 +407,14 @@ static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
415 u32 cfg_o = 0; 407 u32 cfg_o = 0;
416 u32 cfg_r = 0; 408 u32 cfg_r = 0;
417 409
418 if (FIMC_LCDFIFO == ctx->out_path) 410 if (FIMC_IO_LCDFIFO == ctx->out_path)
419 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN; 411 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
420 412
421 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width); 413 cfg_o |= (frame->f_height << 16) | frame->f_width;
422 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height); 414 cfg_r |= (frame->height << 16) | frame->width;
423 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
424 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
425 415
426 writel(cfg_o, dev->regs + S5P_ORGISIZE); 416 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
427 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE); 417 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
428} 418}
429 419
430void fimc_hw_set_in_dma(struct fimc_ctx *ctx) 420void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
@@ -435,80 +425,77 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
435 u32 cfg; 425 u32 cfg;
436 426
437 /* Set the pixel offsets. */ 427 /* Set the pixel offsets. */
438 cfg = S5P_CIO_OFFS_HOR(offset->y_h); 428 cfg = (offset->y_v << 16) | offset->y_h;
439 cfg |= S5P_CIO_OFFS_VER(offset->y_v); 429 writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
440 writel(cfg, dev->regs + S5P_CIIYOFF);
441 430
442 cfg = S5P_CIO_OFFS_HOR(offset->cb_h); 431 cfg = (offset->cb_v << 16) | offset->cb_h;
443 cfg |= S5P_CIO_OFFS_VER(offset->cb_v); 432 writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
444 writel(cfg, dev->regs + S5P_CIICBOFF);
445 433
446 cfg = S5P_CIO_OFFS_HOR(offset->cr_h); 434 cfg = (offset->cr_v << 16) | offset->cr_h;
447 cfg |= S5P_CIO_OFFS_VER(offset->cr_v); 435 writel(cfg, dev->regs + FIMC_REG_CIICROFF);
448 writel(cfg, dev->regs + S5P_CIICROFF);
449 436
450 /* Input original and real size. */ 437 /* Input original and real size. */
451 fimc_hw_set_in_dma_size(ctx); 438 fimc_hw_set_in_dma_size(ctx);
452 439
453 /* Use DMA autoload only in FIFO mode. */ 440 /* Use DMA autoload only in FIFO mode. */
454 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO); 441 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
455 442
456 /* Set the input DMA to process single frame only. */ 443 /* Set the input DMA to process single frame only. */
457 cfg = readl(dev->regs + S5P_MSCTRL); 444 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
458 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK 445 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
459 | S5P_MSCTRL_IN_BURST_COUNT_MASK 446 | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
460 | S5P_MSCTRL_INPUT_MASK 447 | FIMC_REG_MSCTRL_INPUT_MASK
461 | S5P_MSCTRL_C_INT_IN_MASK 448 | FIMC_REG_MSCTRL_C_INT_IN_MASK
462 | S5P_MSCTRL_2P_IN_ORDER_MASK); 449 | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK);
463 450
464 cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4) 451 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
465 | S5P_MSCTRL_INPUT_MEMORY 452 | FIMC_REG_MSCTRL_INPUT_MEMORY
466 | S5P_MSCTRL_FIFO_CTRL_FULL); 453 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
467 454
468 switch (frame->fmt->color) { 455 switch (frame->fmt->color) {
469 case S5P_FIMC_RGB565...S5P_FIMC_RGB888: 456 case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
470 cfg |= S5P_MSCTRL_INFORMAT_RGB; 457 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
471 break; 458 break;
472 case S5P_FIMC_YCBCR420: 459 case FIMC_FMT_YCBCR420:
473 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420; 460 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
474 461
475 if (frame->fmt->colplanes == 2) 462 if (frame->fmt->colplanes == 2)
476 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE; 463 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
477 else 464 else
478 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE; 465 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
479 466
480 break; 467 break;
481 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: 468 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
482 if (frame->fmt->colplanes == 1) { 469 if (frame->fmt->colplanes == 1) {
483 cfg |= ctx->in_order_1p 470 cfg |= ctx->in_order_1p
484 | S5P_MSCTRL_INFORMAT_YCBCR422_1P; 471 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
485 } else { 472 } else {
486 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422; 473 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
487 474
488 if (frame->fmt->colplanes == 2) 475 if (frame->fmt->colplanes == 2)
489 cfg |= ctx->in_order_2p 476 cfg |= ctx->in_order_2p
490 | S5P_MSCTRL_C_INT_IN_2PLANE; 477 | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
491 else 478 else
492 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE; 479 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
493 } 480 }
494 break; 481 break;
495 default: 482 default:
496 break; 483 break;
497 } 484 }
498 485
499 writel(cfg, dev->regs + S5P_MSCTRL); 486 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
500 487
501 /* Input/output DMA linear/tiled mode. */ 488 /* Input/output DMA linear/tiled mode. */
502 cfg = readl(dev->regs + S5P_CIDMAPARAM); 489 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
503 cfg &= ~S5P_CIDMAPARAM_TILE_MASK; 490 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
504 491
505 if (tiled_fmt(ctx->s_frame.fmt)) 492 if (tiled_fmt(ctx->s_frame.fmt))
506 cfg |= S5P_CIDMAPARAM_R_64X32; 493 cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
507 494
508 if (tiled_fmt(ctx->d_frame.fmt)) 495 if (tiled_fmt(ctx->d_frame.fmt))
509 cfg |= S5P_CIDMAPARAM_W_64X32; 496 cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
510 497
511 writel(cfg, dev->regs + S5P_CIDMAPARAM); 498 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
512} 499}
513 500
514 501
@@ -516,40 +503,40 @@ void fimc_hw_set_input_path(struct fimc_ctx *ctx)
516{ 503{
517 struct fimc_dev *dev = ctx->fimc_dev; 504 struct fimc_dev *dev = ctx->fimc_dev;
518 505
519 u32 cfg = readl(dev->regs + S5P_MSCTRL); 506 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
520 cfg &= ~S5P_MSCTRL_INPUT_MASK; 507 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
521 508
522 if (ctx->in_path == FIMC_DMA) 509 if (ctx->in_path == FIMC_IO_DMA)
523 cfg |= S5P_MSCTRL_INPUT_MEMORY; 510 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
524 else 511 else
525 cfg |= S5P_MSCTRL_INPUT_EXTCAM; 512 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
526 513
527 writel(cfg, dev->regs + S5P_MSCTRL); 514 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
528} 515}
529 516
530void fimc_hw_set_output_path(struct fimc_ctx *ctx) 517void fimc_hw_set_output_path(struct fimc_ctx *ctx)
531{ 518{
532 struct fimc_dev *dev = ctx->fimc_dev; 519 struct fimc_dev *dev = ctx->fimc_dev;
533 520
534 u32 cfg = readl(dev->regs + S5P_CISCCTRL); 521 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
535 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO; 522 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
536 if (ctx->out_path == FIMC_LCDFIFO) 523 if (ctx->out_path == FIMC_IO_LCDFIFO)
537 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO; 524 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
538 writel(cfg, dev->regs + S5P_CISCCTRL); 525 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
539} 526}
540 527
541void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr) 528void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
542{ 529{
543 u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE); 530 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
544 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS; 531 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
545 writel(cfg, dev->regs + S5P_CIREAL_ISIZE); 532 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
546 533
547 writel(paddr->y, dev->regs + S5P_CIIYSA(0)); 534 writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
548 writel(paddr->cb, dev->regs + S5P_CIICBSA(0)); 535 writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
549 writel(paddr->cr, dev->regs + S5P_CIICRSA(0)); 536 writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
550 537
551 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS; 538 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
552 writel(cfg, dev->regs + S5P_CIREAL_ISIZE); 539 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
553} 540}
554 541
555void fimc_hw_set_output_addr(struct fimc_dev *dev, 542void fimc_hw_set_output_addr(struct fimc_dev *dev,
@@ -557,9 +544,9 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev,
557{ 544{
558 int i = (index == -1) ? 0 : index; 545 int i = (index == -1) ? 0 : index;
559 do { 546 do {
560 writel(paddr->y, dev->regs + S5P_CIOYSA(i)); 547 writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
561 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i)); 548 writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
562 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i)); 549 writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
563 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", 550 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
564 i, paddr->y, paddr->cb, paddr->cr); 551 i, paddr->y, paddr->cb, paddr->cr);
565 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS); 552 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
@@ -568,32 +555,45 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev,
568int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, 555int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
569 struct s5p_fimc_isp_info *cam) 556 struct s5p_fimc_isp_info *cam)
570{ 557{
571 u32 cfg = readl(fimc->regs + S5P_CIGCTRL); 558 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
572 559
573 cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC | 560 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
574 S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC | 561 FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC |
575 S5P_CIGCTRL_INVPOLFIELD); 562 FIMC_REG_CIGCTRL_INVPOLFIELD);
576 563
577 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) 564 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
578 cfg |= S5P_CIGCTRL_INVPOLPCLK; 565 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
579 566
580 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) 567 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
581 cfg |= S5P_CIGCTRL_INVPOLVSYNC; 568 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
582 569
583 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 570 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
584 cfg |= S5P_CIGCTRL_INVPOLHREF; 571 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
585 572
586 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 573 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
587 cfg |= S5P_CIGCTRL_INVPOLHSYNC; 574 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
588 575
589 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) 576 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
590 cfg |= S5P_CIGCTRL_INVPOLFIELD; 577 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
591 578
592 writel(cfg, fimc->regs + S5P_CIGCTRL); 579 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
593 580
594 return 0; 581 return 0;
595} 582}
596 583
584struct mbus_pixfmt_desc {
585 u32 pixelcode;
586 u32 cisrcfmt;
587 u16 bus_width;
588};
589
590static const struct mbus_pixfmt_desc pix_desc[] = {
591 { V4L2_MBUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 },
592 { V4L2_MBUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 },
593 { V4L2_MBUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 },
594 { V4L2_MBUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 },
595};
596
597int fimc_hw_set_camera_source(struct fimc_dev *fimc, 597int fimc_hw_set_camera_source(struct fimc_dev *fimc,
598 struct s5p_fimc_isp_info *cam) 598 struct s5p_fimc_isp_info *cam)
599{ 599{
@@ -602,18 +602,6 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
602 u32 bus_width; 602 u32 bus_width;
603 int i; 603 int i;
604 604
605 static const struct {
606 u32 pixelcode;
607 u32 cisrcfmt;
608 u16 bus_width;
609 } pix_desc[] = {
610 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
611 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
612 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
613 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
614 /* TODO: Add pixel codes for 16-bit bus width */
615 };
616
617 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) { 605 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
618 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) { 606 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
619 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) { 607 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
@@ -632,41 +620,37 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
632 620
633 if (cam->bus_type == FIMC_ITU_601) { 621 if (cam->bus_type == FIMC_ITU_601) {
634 if (bus_width == 8) 622 if (bus_width == 8)
635 cfg |= S5P_CISRCFMT_ITU601_8BIT; 623 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
636 else if (bus_width == 16) 624 else if (bus_width == 16)
637 cfg |= S5P_CISRCFMT_ITU601_16BIT; 625 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
638 } /* else defaults to ITU-R BT.656 8-bit */ 626 } /* else defaults to ITU-R BT.656 8-bit */
639 } else if (cam->bus_type == FIMC_MIPI_CSI2) { 627 } else if (cam->bus_type == FIMC_MIPI_CSI2) {
640 if (fimc_fmt_is_jpeg(f->fmt->color)) 628 if (fimc_fmt_is_jpeg(f->fmt->color))
641 cfg |= S5P_CISRCFMT_ITU601_8BIT; 629 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
642 } 630 }
643 631
644 cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height); 632 cfg |= (f->o_width << 16) | f->o_height;
645 writel(cfg, fimc->regs + S5P_CISRCFMT); 633 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
646 return 0; 634 return 0;
647} 635}
648 636
649 637void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
650int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
651{ 638{
652 u32 hoff2, voff2; 639 u32 hoff2, voff2;
653 640
654 u32 cfg = readl(fimc->regs + S5P_CIWDOFST); 641 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
655 642
656 cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK); 643 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
657 cfg |= S5P_CIWDOFST_OFF_EN | 644 cfg |= FIMC_REG_CIWDOFST_OFF_EN |
658 S5P_CIWDOFST_HOROFF(f->offs_h) | 645 (f->offs_h << 16) | f->offs_v;
659 S5P_CIWDOFST_VEROFF(f->offs_v);
660 646
661 writel(cfg, fimc->regs + S5P_CIWDOFST); 647 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
662 648
663 /* See CIWDOFSTn register description in the datasheet for details. */ 649 /* See CIWDOFSTn register description in the datasheet for details. */
664 hoff2 = f->o_width - f->width - f->offs_h; 650 hoff2 = f->o_width - f->width - f->offs_h;
665 voff2 = f->o_height - f->height - f->offs_v; 651 voff2 = f->o_height - f->height - f->offs_v;
666 cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2); 652 cfg = (hoff2 << 16) | voff2;
667 653 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
668 writel(cfg, fimc->regs + S5P_CIWDOFST2);
669 return 0;
670} 654}
671 655
672int fimc_hw_set_camera_type(struct fimc_dev *fimc, 656int fimc_hw_set_camera_type(struct fimc_dev *fimc,
@@ -674,28 +658,29 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
674{ 658{
675 u32 cfg, tmp; 659 u32 cfg, tmp;
676 struct fimc_vid_cap *vid_cap = &fimc->vid_cap; 660 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
661 u32 csis_data_alignment = 32;
677 662
678 cfg = readl(fimc->regs + S5P_CIGCTRL); 663 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
679 664
680 /* Select ITU B interface, disable Writeback path and test pattern. */ 665 /* Select ITU B interface, disable Writeback path and test pattern. */
681 cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A | 666 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
682 S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB | 667 FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB |
683 S5P_CIGCTRL_SELCAM_MIPI_A | S5P_CIGCTRL_CAM_JPEG); 668 FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG);
684 669
685 if (cam->bus_type == FIMC_MIPI_CSI2) { 670 if (cam->bus_type == FIMC_MIPI_CSI2) {
686 cfg |= S5P_CIGCTRL_SELCAM_MIPI; 671 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
687 672
688 if (cam->mux_id == 0) 673 if (cam->mux_id == 0)
689 cfg |= S5P_CIGCTRL_SELCAM_MIPI_A; 674 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
690 675
691 /* TODO: add remaining supported formats. */ 676 /* TODO: add remaining supported formats. */
692 switch (vid_cap->mf.code) { 677 switch (vid_cap->mf.code) {
693 case V4L2_MBUS_FMT_VYUY8_2X8: 678 case V4L2_MBUS_FMT_VYUY8_2X8:
694 tmp = S5P_CSIIMGFMT_YCBCR422_8BIT; 679 tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
695 break; 680 break;
696 case V4L2_MBUS_FMT_JPEG_1X8: 681 case V4L2_MBUS_FMT_JPEG_1X8:
697 tmp = S5P_CSIIMGFMT_USER(1); 682 tmp = FIMC_REG_CSIIMGFMT_USER(1);
698 cfg |= S5P_CIGCTRL_CAM_JPEG; 683 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
699 break; 684 break;
700 default: 685 default:
701 v4l2_err(fimc->vid_cap.vfd, 686 v4l2_err(fimc->vid_cap.vfd,
@@ -703,21 +688,86 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
703 vid_cap->mf.code); 688 vid_cap->mf.code);
704 return -EINVAL; 689 return -EINVAL;
705 } 690 }
706 tmp |= (cam->csi_data_align == 32) << 8; 691 tmp |= (csis_data_alignment == 32) << 8;
707 692
708 writel(tmp, fimc->regs + S5P_CSIIMGFMT); 693 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
709 694
710 } else if (cam->bus_type == FIMC_ITU_601 || 695 } else if (cam->bus_type == FIMC_ITU_601 ||
711 cam->bus_type == FIMC_ITU_656) { 696 cam->bus_type == FIMC_ITU_656) {
712 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */ 697 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
713 cfg |= S5P_CIGCTRL_SELCAM_ITU_A; 698 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
714 } else if (cam->bus_type == FIMC_LCD_WB) { 699 } else if (cam->bus_type == FIMC_LCD_WB) {
715 cfg |= S5P_CIGCTRL_CAMIF_SELWB; 700 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
716 } else { 701 } else {
717 err("invalid camera bus type selected\n"); 702 err("invalid camera bus type selected\n");
718 return -EINVAL; 703 return -EINVAL;
719 } 704 }
720 writel(cfg, fimc->regs + S5P_CIGCTRL); 705 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
721 706
722 return 0; 707 return 0;
723} 708}
709
710void fimc_hw_clear_irq(struct fimc_dev *dev)
711{
712 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
713 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
714 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
715}
716
717void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
718{
719 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
720 if (on)
721 cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
722 else
723 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
724 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
725}
726
727void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
728{
729 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
730 if (on)
731 cfg |= FIMC_REG_MSCTRL_ENVID;
732 else
733 cfg &= ~FIMC_REG_MSCTRL_ENVID;
734 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
735}
736
737void fimc_hw_dis_capture(struct fimc_dev *dev)
738{
739 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
740 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN | FIMC_REG_CIIMGCPT_IMGCPTEN_SC);
741 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
742}
743
744/* Return an index to the buffer actually being written. */
745u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
746{
747 u32 reg;
748
749 if (dev->variant->has_cistatus2) {
750 reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3F;
751 return reg > 0 ? --reg : reg;
752 }
753
754 reg = readl(dev->regs + FIMC_REG_CISTATUS);
755
756 return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >>
757 FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
758}
759
760/* Locking: the caller holds fimc->slock */
761void fimc_activate_capture(struct fimc_ctx *ctx)
762{
763 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
764 fimc_hw_en_capture(ctx);
765}
766
767void fimc_deactivate_capture(struct fimc_dev *fimc)
768{
769 fimc_hw_en_lastirq(fimc, true);
770 fimc_hw_dis_capture(fimc);
771 fimc_hw_enable_scaler(fimc, false);
772 fimc_hw_en_lastirq(fimc, false);
773}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 13:35:46 -0500