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path: root/drivers/media/video/s5p-fimc/fimc-reg.c
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Diffstat (limited to 'drivers/media/video/s5p-fimc/fimc-reg.c')
-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.c205
1 files changed, 111 insertions, 94 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
index 511631a2e5c3..4d929a394521 100644
--- a/drivers/media/video/s5p-fimc/fimc-reg.c
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/delay.h> 14#include <linux/delay.h>
15#include <mach/map.h> 15#include <mach/map.h>
16#include <media/s3c_fimc.h> 16#include <media/s5p_fimc.h>
17 17
18#include "fimc-core.h" 18#include "fimc-core.h"
19 19
@@ -37,11 +37,11 @@ void fimc_hw_reset(struct fimc_dev *dev)
37 writel(cfg, dev->regs + S5P_CIGCTRL); 37 writel(cfg, dev->regs + S5P_CIGCTRL);
38} 38}
39 39
40static u32 fimc_hw_get_in_flip(u32 ctx_flip) 40static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
41{ 41{
42 u32 flip = S5P_MSCTRL_FLIP_NORMAL; 42 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
43 43
44 switch (ctx_flip) { 44 switch (ctx->flip) {
45 case FLIP_X_AXIS: 45 case FLIP_X_AXIS:
46 flip = S5P_MSCTRL_FLIP_X_MIRROR; 46 flip = S5P_MSCTRL_FLIP_X_MIRROR;
47 break; 47 break;
@@ -51,16 +51,20 @@ static u32 fimc_hw_get_in_flip(u32 ctx_flip)
51 case FLIP_XY_AXIS: 51 case FLIP_XY_AXIS:
52 flip = S5P_MSCTRL_FLIP_180; 52 flip = S5P_MSCTRL_FLIP_180;
53 break; 53 break;
54 default:
55 break;
54 } 56 }
57 if (ctx->rotation <= 90)
58 return flip;
55 59
56 return flip; 60 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180;
57} 61}
58 62
59static u32 fimc_hw_get_target_flip(u32 ctx_flip) 63static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
60{ 64{
61 u32 flip = S5P_CITRGFMT_FLIP_NORMAL; 65 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
62 66
63 switch (ctx_flip) { 67 switch (ctx->flip) {
64 case FLIP_X_AXIS: 68 case FLIP_X_AXIS:
65 flip = S5P_CITRGFMT_FLIP_X_MIRROR; 69 flip = S5P_CITRGFMT_FLIP_X_MIRROR;
66 break; 70 break;
@@ -70,11 +74,13 @@ static u32 fimc_hw_get_target_flip(u32 ctx_flip)
70 case FLIP_XY_AXIS: 74 case FLIP_XY_AXIS:
71 flip = S5P_CITRGFMT_FLIP_180; 75 flip = S5P_CITRGFMT_FLIP_180;
72 break; 76 break;
73 case FLIP_NONE: 77 default:
74 break; 78 break;
75
76 } 79 }
77 return flip; 80 if (ctx->rotation <= 90)
81 return flip;
82
83 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180;
78} 84}
79 85
80void fimc_hw_set_rotation(struct fimc_ctx *ctx) 86void fimc_hw_set_rotation(struct fimc_ctx *ctx)
@@ -84,10 +90,7 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
84 90
85 cfg = readl(dev->regs + S5P_CITRGFMT); 91 cfg = readl(dev->regs + S5P_CITRGFMT);
86 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 | 92 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
87 S5P_CITRGFMT_FLIP_180); 93 S5P_CITRGFMT_FLIP_180);
88
89 flip = readl(dev->regs + S5P_MSCTRL);
90 flip &= ~S5P_MSCTRL_FLIP_MASK;
91 94
92 /* 95 /*
93 * The input and output rotator cannot work simultaneously. 96 * The input and output rotator cannot work simultaneously.
@@ -95,26 +98,22 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
95 * in direct fifo output mode. 98 * in direct fifo output mode.
96 */ 99 */
97 if (ctx->rotation == 90 || ctx->rotation == 270) { 100 if (ctx->rotation == 90 || ctx->rotation == 270) {
98 if (ctx->out_path == FIMC_LCDFIFO) {
99 cfg |= S5P_CITRGFMT_INROT90;
100 if (ctx->rotation == 270)
101 flip |= S5P_MSCTRL_FLIP_180;
102 } else {
103 cfg |= S5P_CITRGFMT_OUTROT90;
104 if (ctx->rotation == 270)
105 cfg |= S5P_CITRGFMT_FLIP_180;
106 }
107 } else if (ctx->rotation == 180) {
108 if (ctx->out_path == FIMC_LCDFIFO) 101 if (ctx->out_path == FIMC_LCDFIFO)
109 flip |= S5P_MSCTRL_FLIP_180; 102 cfg |= S5P_CITRGFMT_INROT90;
110 else 103 else
111 cfg |= S5P_CITRGFMT_FLIP_180; 104 cfg |= S5P_CITRGFMT_OUTROT90;
112 } 105 }
113 if (ctx->rotation == 180 || ctx->rotation == 270)
114 writel(flip, dev->regs + S5P_MSCTRL);
115 106
116 cfg |= fimc_hw_get_target_flip(ctx->flip); 107 if (ctx->out_path == FIMC_DMA) {
117 writel(cfg, dev->regs + S5P_CITRGFMT); 108 cfg |= fimc_hw_get_target_flip(ctx);
109 writel(cfg, dev->regs + S5P_CITRGFMT);
110 } else {
111 /* LCD FIFO path */
112 flip = readl(dev->regs + S5P_MSCTRL);
113 flip &= ~S5P_MSCTRL_FLIP_MASK;
114 flip |= fimc_hw_get_in_flip(ctx);
115 writel(flip, dev->regs + S5P_MSCTRL);
116 }
118} 117}
119 118
120void fimc_hw_set_target_format(struct fimc_ctx *ctx) 119void fimc_hw_set_target_format(struct fimc_ctx *ctx)
@@ -131,19 +130,14 @@ void fimc_hw_set_target_format(struct fimc_ctx *ctx)
131 S5P_CITRGFMT_VSIZE_MASK); 130 S5P_CITRGFMT_VSIZE_MASK);
132 131
133 switch (frame->fmt->color) { 132 switch (frame->fmt->color) {
134 case S5P_FIMC_RGB565: 133 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
135 case S5P_FIMC_RGB666:
136 case S5P_FIMC_RGB888:
137 cfg |= S5P_CITRGFMT_RGB; 134 cfg |= S5P_CITRGFMT_RGB;
138 break; 135 break;
139 case S5P_FIMC_YCBCR420: 136 case S5P_FIMC_YCBCR420:
140 cfg |= S5P_CITRGFMT_YCBCR420; 137 cfg |= S5P_CITRGFMT_YCBCR420;
141 break; 138 break;
142 case S5P_FIMC_YCBYCR422: 139 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
143 case S5P_FIMC_YCRYCB422: 140 if (frame->fmt->colplanes == 1)
144 case S5P_FIMC_CBYCRY422:
145 case S5P_FIMC_CRYCBY422:
146 if (frame->fmt->planes_cnt == 1)
147 cfg |= S5P_CITRGFMT_YCBCR422_1P; 141 cfg |= S5P_CITRGFMT_YCBCR422_1P;
148 else 142 else
149 cfg |= S5P_CITRGFMT_YCBCR422; 143 cfg |= S5P_CITRGFMT_YCBCR422;
@@ -219,11 +213,11 @@ void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
219 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK | 213 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
220 S5P_CIOCTRL_YCBCR_PLANE_MASK); 214 S5P_CIOCTRL_YCBCR_PLANE_MASK);
221 215
222 if (frame->fmt->planes_cnt == 1) 216 if (frame->fmt->colplanes == 1)
223 cfg |= ctx->out_order_1p; 217 cfg |= ctx->out_order_1p;
224 else if (frame->fmt->planes_cnt == 2) 218 else if (frame->fmt->colplanes == 2)
225 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE; 219 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
226 else if (frame->fmt->planes_cnt == 3) 220 else if (frame->fmt->colplanes == 3)
227 cfg |= S5P_CIOCTRL_YCBCR_3PLANE; 221 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
228 222
229 writel(cfg, dev->regs + S5P_CIOCTRL); 223 writel(cfg, dev->regs + S5P_CIOCTRL);
@@ -249,7 +243,7 @@ void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
249 writel(cfg, dev->regs + S5P_CIOCTRL); 243 writel(cfg, dev->regs + S5P_CIOCTRL);
250} 244}
251 245
252static void fimc_hw_set_prescaler(struct fimc_ctx *ctx) 246void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
253{ 247{
254 struct fimc_dev *dev = ctx->fimc_dev; 248 struct fimc_dev *dev = ctx->fimc_dev;
255 struct fimc_scaler *sc = &ctx->scaler; 249 struct fimc_scaler *sc = &ctx->scaler;
@@ -267,7 +261,7 @@ static void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
267 writel(cfg, dev->regs + S5P_CISCPREDST); 261 writel(cfg, dev->regs + S5P_CISCPREDST);
268} 262}
269 263
270void fimc_hw_set_scaler(struct fimc_ctx *ctx) 264static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
271{ 265{
272 struct fimc_dev *dev = ctx->fimc_dev; 266 struct fimc_dev *dev = ctx->fimc_dev;
273 struct fimc_scaler *sc = &ctx->scaler; 267 struct fimc_scaler *sc = &ctx->scaler;
@@ -275,8 +269,6 @@ void fimc_hw_set_scaler(struct fimc_ctx *ctx)
275 struct fimc_frame *dst_frame = &ctx->d_frame; 269 struct fimc_frame *dst_frame = &ctx->d_frame;
276 u32 cfg = 0; 270 u32 cfg = 0;
277 271
278 fimc_hw_set_prescaler(ctx);
279
280 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW)) 272 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
281 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE); 273 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
282 274
@@ -316,13 +308,42 @@ void fimc_hw_set_scaler(struct fimc_ctx *ctx)
316 cfg |= S5P_CISCCTRL_INTERLACE; 308 cfg |= S5P_CISCCTRL_INTERLACE;
317 } 309 }
318 310
311 writel(cfg, dev->regs + S5P_CISCCTRL);
312}
313
314void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
315{
316 struct fimc_dev *dev = ctx->fimc_dev;
317 struct samsung_fimc_variant *variant = dev->variant;
318 struct fimc_scaler *sc = &ctx->scaler;
319 u32 cfg;
320
319 dbg("main_hratio= 0x%X main_vratio= 0x%X", 321 dbg("main_hratio= 0x%X main_vratio= 0x%X",
320 sc->main_hratio, sc->main_vratio); 322 sc->main_hratio, sc->main_vratio);
321 323
322 cfg |= S5P_CISCCTRL_SC_HORRATIO(sc->main_hratio); 324 fimc_hw_set_scaler(ctx);
323 cfg |= S5P_CISCCTRL_SC_VERRATIO(sc->main_vratio);
324 325
325 writel(cfg, dev->regs + S5P_CISCCTRL); 326 cfg = readl(dev->regs + S5P_CISCCTRL);
327
328 if (variant->has_mainscaler_ext) {
329 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
330 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
331 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
332 writel(cfg, dev->regs + S5P_CISCCTRL);
333
334 cfg = readl(dev->regs + S5P_CIEXTEN);
335
336 cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK |
337 S5P_CIEXTEN_MHRATIO_EXT_MASK);
338 cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
339 cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
340 writel(cfg, dev->regs + S5P_CIEXTEN);
341 } else {
342 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
343 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio);
344 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio);
345 writel(cfg, dev->regs + S5P_CISCCTRL);
346 }
326} 347}
327 348
328void fimc_hw_en_capture(struct fimc_ctx *ctx) 349void fimc_hw_en_capture(struct fimc_ctx *ctx)
@@ -410,41 +431,37 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
410 431
411 /* Set the input DMA to process single frame only. */ 432 /* Set the input DMA to process single frame only. */
412 cfg = readl(dev->regs + S5P_MSCTRL); 433 cfg = readl(dev->regs + S5P_MSCTRL);
413 cfg &= ~(S5P_MSCTRL_FLIP_MASK 434 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK
414 | S5P_MSCTRL_INFORMAT_MASK
415 | S5P_MSCTRL_IN_BURST_COUNT_MASK 435 | S5P_MSCTRL_IN_BURST_COUNT_MASK
416 | S5P_MSCTRL_INPUT_MASK 436 | S5P_MSCTRL_INPUT_MASK
417 | S5P_MSCTRL_C_INT_IN_MASK 437 | S5P_MSCTRL_C_INT_IN_MASK
418 | S5P_MSCTRL_2P_IN_ORDER_MASK); 438 | S5P_MSCTRL_2P_IN_ORDER_MASK);
419 439
420 cfg |= (S5P_MSCTRL_FRAME_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY); 440 cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4)
441 | S5P_MSCTRL_INPUT_MEMORY
442 | S5P_MSCTRL_FIFO_CTRL_FULL);
421 443
422 switch (frame->fmt->color) { 444 switch (frame->fmt->color) {
423 case S5P_FIMC_RGB565: 445 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
424 case S5P_FIMC_RGB666:
425 case S5P_FIMC_RGB888:
426 cfg |= S5P_MSCTRL_INFORMAT_RGB; 446 cfg |= S5P_MSCTRL_INFORMAT_RGB;
427 break; 447 break;
428 case S5P_FIMC_YCBCR420: 448 case S5P_FIMC_YCBCR420:
429 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420; 449 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
430 450
431 if (frame->fmt->planes_cnt == 2) 451 if (frame->fmt->colplanes == 2)
432 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE; 452 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
433 else 453 else
434 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE; 454 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
435 455
436 break; 456 break;
437 case S5P_FIMC_YCBYCR422: 457 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
438 case S5P_FIMC_YCRYCB422: 458 if (frame->fmt->colplanes == 1) {
439 case S5P_FIMC_CBYCRY422:
440 case S5P_FIMC_CRYCBY422:
441 if (frame->fmt->planes_cnt == 1) {
442 cfg |= ctx->in_order_1p 459 cfg |= ctx->in_order_1p
443 | S5P_MSCTRL_INFORMAT_YCBCR422_1P; 460 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
444 } else { 461 } else {
445 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422; 462 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
446 463
447 if (frame->fmt->planes_cnt == 2) 464 if (frame->fmt->colplanes == 2)
448 cfg |= ctx->in_order_2p 465 cfg |= ctx->in_order_2p
449 | S5P_MSCTRL_C_INT_IN_2PLANE; 466 | S5P_MSCTRL_C_INT_IN_2PLANE;
450 else 467 else
@@ -455,13 +472,6 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
455 break; 472 break;
456 } 473 }
457 474
458 /*
459 * Input DMA flip mode (and rotation).
460 * Do not allow simultaneous rotation and flipping.
461 */
462 if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
463 cfg |= fimc_hw_get_in_flip(ctx->flip);
464
465 writel(cfg, dev->regs + S5P_MSCTRL); 475 writel(cfg, dev->regs + S5P_MSCTRL);
466 476
467 /* Input/output DMA linear/tiled mode. */ 477 /* Input/output DMA linear/tiled mode. */
@@ -532,7 +542,7 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev,
532} 542}
533 543
534int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, 544int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
535 struct s3c_fimc_isp_info *cam) 545 struct s5p_fimc_isp_info *cam)
536{ 546{
537 u32 cfg = readl(fimc->regs + S5P_CIGCTRL); 547 u32 cfg = readl(fimc->regs + S5P_CIGCTRL);
538 548
@@ -557,41 +567,46 @@ int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
557} 567}
558 568
559int fimc_hw_set_camera_source(struct fimc_dev *fimc, 569int fimc_hw_set_camera_source(struct fimc_dev *fimc,
560 struct s3c_fimc_isp_info *cam) 570 struct s5p_fimc_isp_info *cam)
561{ 571{
562 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame; 572 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
563 u32 cfg = 0; 573 u32 cfg = 0;
574 u32 bus_width;
575 int i;
576
577 static const struct {
578 u32 pixelcode;
579 u32 cisrcfmt;
580 u16 bus_width;
581 } pix_desc[] = {
582 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
583 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
584 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
585 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
586 /* TODO: Add pixel codes for 16-bit bus width */
587 };
564 588
565 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) { 589 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
590 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
591 if (fimc->vid_cap.fmt.code == pix_desc[i].pixelcode) {
592 cfg = pix_desc[i].cisrcfmt;
593 bus_width = pix_desc[i].bus_width;
594 break;
595 }
596 }
566 597
567 switch (fimc->vid_cap.fmt.code) { 598 if (i == ARRAY_SIZE(pix_desc)) {
568 case V4L2_MBUS_FMT_YUYV8_2X8: 599 v4l2_err(&fimc->vid_cap.v4l2_dev,
569 cfg = S5P_CISRCFMT_ORDER422_YCBYCR; 600 "Camera color format not supported: %d\n",
570 break; 601 fimc->vid_cap.fmt.code);
571 case V4L2_MBUS_FMT_YVYU8_2X8:
572 cfg = S5P_CISRCFMT_ORDER422_YCRYCB;
573 break;
574 case V4L2_MBUS_FMT_VYUY8_2X8:
575 cfg = S5P_CISRCFMT_ORDER422_CRYCBY;
576 break;
577 case V4L2_MBUS_FMT_UYVY8_2X8:
578 cfg = S5P_CISRCFMT_ORDER422_CBYCRY;
579 break;
580 default:
581 err("camera image format not supported: %d",
582 fimc->vid_cap.fmt.code);
583 return -EINVAL; 602 return -EINVAL;
584 } 603 }
585 604
586 if (cam->bus_type == FIMC_ITU_601) { 605 if (cam->bus_type == FIMC_ITU_601) {
587 if (cam->bus_width == 8) { 606 if (bus_width == 8)
588 cfg |= S5P_CISRCFMT_ITU601_8BIT; 607 cfg |= S5P_CISRCFMT_ITU601_8BIT;
589 } else if (cam->bus_width == 16) { 608 else if (bus_width == 16)
590 cfg |= S5P_CISRCFMT_ITU601_16BIT; 609 cfg |= S5P_CISRCFMT_ITU601_16BIT;
591 } else {
592 err("invalid bus width: %d", cam->bus_width);
593 return -EINVAL;
594 }
595 } /* else defaults to ITU-R BT.656 8-bit */ 610 } /* else defaults to ITU-R BT.656 8-bit */
596 } 611 }
597 612
@@ -624,7 +639,7 @@ int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
624} 639}
625 640
626int fimc_hw_set_camera_type(struct fimc_dev *fimc, 641int fimc_hw_set_camera_type(struct fimc_dev *fimc,
627 struct s3c_fimc_isp_info *cam) 642 struct s5p_fimc_isp_info *cam)
628{ 643{
629 u32 cfg, tmp; 644 u32 cfg, tmp;
630 struct fimc_vid_cap *vid_cap = &fimc->vid_cap; 645 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
@@ -650,10 +665,12 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
650 vid_cap->fmt.code); 665 vid_cap->fmt.code);
651 return -EINVAL; 666 return -EINVAL;
652 } 667 }
653 writel(tmp | (0x1 << 8), fimc->regs + S5P_CSIIMGFMT); 668 tmp |= (cam->csi_data_align == 32) << 8;
669
670 writel(tmp, fimc->regs + S5P_CSIIMGFMT);
654 671
655 } else if (cam->bus_type == FIMC_ITU_601 || 672 } else if (cam->bus_type == FIMC_ITU_601 ||
656 cam->bus_type == FIMC_ITU_656) { 673 cam->bus_type == FIMC_ITU_656) {
657 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */ 674 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
658 cfg |= S5P_CIGCTRL_SELCAM_ITU_A; 675 cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
659 } else if (cam->bus_type == FIMC_LCD_WB) { 676 } else if (cam->bus_type == FIMC_LCD_WB) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 13:19:30 -0500