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path: root/drivers/media/video/mx2_camera.c
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Diffstat (limited to 'drivers/media/video/mx2_camera.c')
-rw-r--r--drivers/media/video/mx2_camera.c1214
1 files changed, 668 insertions, 546 deletions
diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
index 04aab0c538aa..18afaeeadb7b 100644
--- a/drivers/media/video/mx2_camera.c
+++ b/drivers/media/video/mx2_camera.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -18,6 +19,7 @@
18#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
19#include <linux/errno.h> 20#include <linux/errno.h>
20#include <linux/fs.h> 21#include <linux/fs.h>
22#include <linux/gcd.h>
21#include <linux/interrupt.h> 23#include <linux/interrupt.h>
22#include <linux/kernel.h> 24#include <linux/kernel.h>
23#include <linux/mm.h> 25#include <linux/mm.h>
@@ -30,17 +32,14 @@
30 32
31#include <media/v4l2-common.h> 33#include <media/v4l2-common.h>
32#include <media/v4l2-dev.h> 34#include <media/v4l2-dev.h>
33#include <media/videobuf-core.h> 35#include <media/videobuf2-core.h>
34#include <media/videobuf-dma-contig.h> 36#include <media/videobuf2-dma-contig.h>
35#include <media/soc_camera.h> 37#include <media/soc_camera.h>
36#include <media/soc_mediabus.h> 38#include <media/soc_mediabus.h>
37 39
38#include <linux/videodev2.h> 40#include <linux/videodev2.h>
39 41
40#include <mach/mx2_cam.h> 42#include <mach/mx2_cam.h>
41#ifdef CONFIG_MACH_MX27
42#include <mach/dma-mx1-mx2.h>
43#endif
44#include <mach/hardware.h> 43#include <mach/hardware.h>
45 44
46#include <asm/dma.h> 45#include <asm/dma.h>
@@ -206,10 +205,23 @@
206#define PRP_INTR_LBOVF (1 << 7) 205#define PRP_INTR_LBOVF (1 << 7)
207#define PRP_INTR_CH2OVF (1 << 8) 206#define PRP_INTR_CH2OVF (1 << 8)
208 207
209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) 208/* Resizing registers */
209#define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
210#define PRP_RZ_VALID_BILINEAR (1 << 31)
210 211
211#define MAX_VIDEO_MEM 16 212#define MAX_VIDEO_MEM 16
212 213
214#define RESIZE_NUM_MIN 1
215#define RESIZE_NUM_MAX 20
216#define BC_COEF 3
217#define SZ_COEF (1 << BC_COEF)
218
219#define RESIZE_DIR_H 0
220#define RESIZE_DIR_V 1
221
222#define RESIZE_ALGO_BILINEAR 0
223#define RESIZE_ALGO_AVERAGING 1
224
213struct mx2_prp_cfg { 225struct mx2_prp_cfg {
214 int channel; 226 int channel;
215 u32 in_fmt; 227 u32 in_fmt;
@@ -219,6 +231,13 @@ struct mx2_prp_cfg {
219 u32 irq_flags; 231 u32 irq_flags;
220}; 232};
221 233
234/* prp resizing parameters */
235struct emma_prp_resize {
236 int algo; /* type of algorithm used */
237 int len; /* number of coefficients */
238 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
239};
240
222/* prp configuration for a client-host fmt pair */ 241/* prp configuration for a client-host fmt pair */
223struct mx2_fmt_cfg { 242struct mx2_fmt_cfg {
224 enum v4l2_mbus_pixelcode in_fmt; 243 enum v4l2_mbus_pixelcode in_fmt;
@@ -226,6 +245,26 @@ struct mx2_fmt_cfg {
226 struct mx2_prp_cfg cfg; 245 struct mx2_prp_cfg cfg;
227}; 246};
228 247
248enum mx2_buffer_state {
249 MX2_STATE_QUEUED,
250 MX2_STATE_ACTIVE,
251 MX2_STATE_DONE,
252};
253
254struct mx2_buf_internal {
255 struct list_head queue;
256 int bufnum;
257 bool discard;
258};
259
260/* buffer for one video frame */
261struct mx2_buffer {
262 /* common v4l buffer stuff -- must be first */
263 struct vb2_buffer vb;
264 enum mx2_buffer_state state;
265 struct mx2_buf_internal internal;
266};
267
229struct mx2_camera_dev { 268struct mx2_camera_dev {
230 struct device *dev; 269 struct device *dev;
231 struct soc_camera_host soc_host; 270 struct soc_camera_host soc_host;
@@ -242,6 +281,7 @@ struct mx2_camera_dev {
242 281
243 struct list_head capture; 282 struct list_head capture;
244 struct list_head active_bufs; 283 struct list_head active_bufs;
284 struct list_head discard;
245 285
246 spinlock_t lock; 286 spinlock_t lock;
247 287
@@ -250,26 +290,23 @@ struct mx2_camera_dev {
250 struct mx2_buffer *fb1_active; 290 struct mx2_buffer *fb1_active;
251 struct mx2_buffer *fb2_active; 291 struct mx2_buffer *fb2_active;
252 292
253 int use_emma;
254
255 u32 csicr1; 293 u32 csicr1;
256 294
295 struct mx2_buf_internal buf_discard[2];
257 void *discard_buffer; 296 void *discard_buffer;
258 dma_addr_t discard_buffer_dma; 297 dma_addr_t discard_buffer_dma;
259 size_t discard_size; 298 size_t discard_size;
260 struct mx2_fmt_cfg *emma_prp; 299 struct mx2_fmt_cfg *emma_prp;
300 struct emma_prp_resize resizing[2];
301 unsigned int s_width, s_height;
261 u32 frame_count; 302 u32 frame_count;
303 struct vb2_alloc_ctx *alloc_ctx;
262}; 304};
263 305
264/* buffer for one video frame */ 306static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
265struct mx2_buffer { 307{
266 /* common v4l buffer stuff -- must be first */ 308 return container_of(int_buf, struct mx2_buffer, internal);
267 struct videobuf_buffer vb; 309}
268
269 enum v4l2_mbus_pixelcode code;
270
271 int bufnum;
272};
273 310
274static struct mx2_fmt_cfg mx27_emma_prp_table[] = { 311static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
275 /* 312 /*
@@ -324,13 +361,36 @@ static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
324 return &mx27_emma_prp_table[0]; 361 return &mx27_emma_prp_table[0];
325}; 362};
326 363
364static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
365 unsigned long phys, int bufnum)
366{
367 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
368
369 if (prp->cfg.channel == 1) {
370 writel(phys, pcdev->base_emma +
371 PRP_DEST_RGB1_PTR + 4 * bufnum);
372 } else {
373 writel(phys, pcdev->base_emma +
374 PRP_DEST_Y_PTR - 0x14 * bufnum);
375 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
376 u32 imgsize = pcdev->icd->user_height *
377 pcdev->icd->user_width;
378
379 writel(phys + imgsize, pcdev->base_emma +
380 PRP_DEST_CB_PTR - 0x14 * bufnum);
381 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
382 PRP_DEST_CR_PTR - 0x14 * bufnum);
383 }
384 }
385}
386
327static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 387static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
328{ 388{
329 unsigned long flags; 389 unsigned long flags;
330 390
331 clk_disable(pcdev->clk_csi); 391 clk_disable(pcdev->clk_csi);
332 writel(0, pcdev->base_csi + CSICR1); 392 writel(0, pcdev->base_csi + CSICR1);
333 if (mx27_camera_emma(pcdev)) { 393 if (cpu_is_mx27()) {
334 writel(0, pcdev->base_emma + PRP_CNTL); 394 writel(0, pcdev->base_emma + PRP_CNTL);
335 } else if (cpu_is_mx25()) { 395 } else if (cpu_is_mx25()) {
336 spin_lock_irqsave(&pcdev->lock, flags); 396 spin_lock_irqsave(&pcdev->lock, flags);
@@ -362,7 +422,7 @@ static int mx2_camera_add_device(struct soc_camera_device *icd)
362 422
363 csicr1 = CSICR1_MCLKEN; 423 csicr1 = CSICR1_MCLKEN;
364 424
365 if (mx27_camera_emma(pcdev)) { 425 if (cpu_is_mx27()) {
366 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 426 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
367 CSICR1_RXFF_LEVEL(0); 427 CSICR1_RXFF_LEVEL(0);
368 } else if (cpu_is_mx27()) 428 } else if (cpu_is_mx27())
@@ -392,56 +452,13 @@ static void mx2_camera_remove_device(struct soc_camera_device *icd)
392 452
393 mx2_camera_deactivate(pcdev); 453 mx2_camera_deactivate(pcdev);
394 454
395 if (pcdev->discard_buffer) {
396 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
397 pcdev->discard_buffer,
398 pcdev->discard_buffer_dma);
399 pcdev->discard_buffer = NULL;
400 }
401
402 pcdev->icd = NULL; 455 pcdev->icd = NULL;
403} 456}
404 457
405#ifdef CONFIG_MACH_MX27
406static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
407{
408 u32 tmp;
409
410 imx_dma_enable(pcdev->dma);
411
412 tmp = readl(pcdev->base_csi + CSICR1);
413 tmp |= CSICR1_RF_OR_INTEN;
414 writel(tmp, pcdev->base_csi + CSICR1);
415}
416
417static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
418{
419 struct mx2_camera_dev *pcdev = data;
420 u32 status = readl(pcdev->base_csi + CSISR);
421
422 if (status & CSISR_SOF_INT && pcdev->active) {
423 u32 tmp;
424
425 tmp = readl(pcdev->base_csi + CSICR1);
426 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
427 mx27_camera_dma_enable(pcdev);
428 }
429
430 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
431
432 return IRQ_HANDLED;
433}
434#else
435static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
436{
437 return IRQ_NONE;
438}
439#endif /* CONFIG_MACH_MX27 */
440
441static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 458static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
442 int state) 459 int state)
443{ 460{
444 struct videobuf_buffer *vb; 461 struct vb2_buffer *vb;
445 struct mx2_buffer *buf; 462 struct mx2_buffer *buf;
446 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 463 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
447 &pcdev->fb2_active; 464 &pcdev->fb2_active;
@@ -454,25 +471,24 @@ static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
454 goto out; 471 goto out;
455 472
456 vb = &(*fb_active)->vb; 473 vb = &(*fb_active)->vb;
457 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 474 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
458 vb, vb->baddr, vb->bsize); 475 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
459 476
460 vb->state = state; 477 do_gettimeofday(&vb->v4l2_buf.timestamp);
461 do_gettimeofday(&vb->ts); 478 vb->v4l2_buf.sequence++;
462 vb->field_count++; 479 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
463
464 wake_up(&vb->done);
465 480
466 if (list_empty(&pcdev->capture)) { 481 if (list_empty(&pcdev->capture)) {
467 buf = NULL; 482 buf = NULL;
468 writel(0, pcdev->base_csi + fb_reg); 483 writel(0, pcdev->base_csi + fb_reg);
469 } else { 484 } else {
470 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 485 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
471 vb.queue); 486 internal.queue);
472 vb = &buf->vb; 487 vb = &buf->vb;
473 list_del(&vb->queue); 488 list_del(&buf->internal.queue);
474 vb->state = VIDEOBUF_ACTIVE; 489 buf->state = MX2_STATE_ACTIVE;
475 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); 490 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
491 pcdev->base_csi + fb_reg);
476 } 492 }
477 493
478 *fb_active = buf; 494 *fb_active = buf;
@@ -487,9 +503,9 @@ static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
487 u32 status = readl(pcdev->base_csi + CSISR); 503 u32 status = readl(pcdev->base_csi + CSISR);
488 504
489 if (status & CSISR_DMA_TSF_FB1_INT) 505 if (status & CSISR_DMA_TSF_FB1_INT)
490 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); 506 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
491 else if (status & CSISR_DMA_TSF_FB2_INT) 507 else if (status & CSISR_DMA_TSF_FB2_INT)
492 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); 508 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
493 509
494 /* FIXME: handle CSISR_RFF_OR_INT */ 510 /* FIXME: handle CSISR_RFF_OR_INT */
495 511
@@ -501,59 +517,50 @@ static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
501/* 517/*
502 * Videobuf operations 518 * Videobuf operations
503 */ 519 */
504static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 520static int mx2_videobuf_setup(struct vb2_queue *vq,
505 unsigned int *size) 521 const struct v4l2_format *fmt,
522 unsigned int *count, unsigned int *num_planes,
523 unsigned int sizes[], void *alloc_ctxs[])
506{ 524{
507 struct soc_camera_device *icd = vq->priv_data; 525 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
526 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
527 struct mx2_camera_dev *pcdev = ici->priv;
508 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 528 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
509 icd->current_fmt->host_fmt); 529 icd->current_fmt->host_fmt);
510 530
511 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); 531 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
532
533 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
534 if (fmt != NULL)
535 return -ENOTTY;
512 536
513 if (bytes_per_line < 0) 537 if (bytes_per_line < 0)
514 return bytes_per_line; 538 return bytes_per_line;
515 539
516 *size = bytes_per_line * icd->user_height; 540 alloc_ctxs[0] = pcdev->alloc_ctx;
541
542 sizes[0] = bytes_per_line * icd->user_height;
517 543
518 if (0 == *count) 544 if (0 == *count)
519 *count = 32; 545 *count = 32;
520 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) 546 if (!*num_planes &&
521 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; 547 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
548 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
522 549
523 return 0; 550 *num_planes = 1;
524}
525 551
526static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) 552 return 0;
527{
528 struct soc_camera_device *icd = vq->priv_data;
529 struct videobuf_buffer *vb = &buf->vb;
530
531 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
532 vb, vb->baddr, vb->bsize);
533
534 /*
535 * This waits until this buffer is out of danger, i.e., until it is no
536 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
537 */
538 videobuf_waiton(vq, vb, 0, 0);
539
540 videobuf_dma_contig_free(vq, vb);
541 dev_dbg(icd->parent, "%s freed\n", __func__);
542
543 vb->state = VIDEOBUF_NEEDS_INIT;
544} 553}
545 554
546static int mx2_videobuf_prepare(struct videobuf_queue *vq, 555static int mx2_videobuf_prepare(struct vb2_buffer *vb)
547 struct videobuf_buffer *vb, enum v4l2_field field)
548{ 556{
549 struct soc_camera_device *icd = vq->priv_data; 557 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
550 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
551 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 558 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
552 icd->current_fmt->host_fmt); 559 icd->current_fmt->host_fmt);
553 int ret = 0; 560 int ret = 0;
554 561
555 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 562 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
556 vb, vb->baddr, vb->bsize); 563 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
557 564
558 if (bytes_per_line < 0) 565 if (bytes_per_line < 0)
559 return bytes_per_line; 566 return bytes_per_line;
@@ -563,99 +570,58 @@ static int mx2_videobuf_prepare(struct videobuf_queue *vq,
563 * This can be useful if you want to see if we actually fill 570 * This can be useful if you want to see if we actually fill
564 * the buffer with something 571 * the buffer with something
565 */ 572 */
566 memset((void *)vb->baddr, 0xaa, vb->bsize); 573 memset((void *)vb2_plane_vaddr(vb, 0),
574 0xaa, vb2_get_plane_payload(vb, 0));
567#endif 575#endif
568 576
569 if (buf->code != icd->current_fmt->code || 577 vb2_set_plane_payload(vb, 0, bytes_per_line * icd->user_height);
570 vb->width != icd->user_width || 578 if (vb2_plane_vaddr(vb, 0) &&
571 vb->height != icd->user_height || 579 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
572 vb->field != field) {
573 buf->code = icd->current_fmt->code;
574 vb->width = icd->user_width;
575 vb->height = icd->user_height;
576 vb->field = field;
577 vb->state = VIDEOBUF_NEEDS_INIT;
578 }
579
580 vb->size = bytes_per_line * vb->height;
581 if (vb->baddr && vb->bsize < vb->size) {
582 ret = -EINVAL; 580 ret = -EINVAL;
583 goto out; 581 goto out;
584 } 582 }
585 583
586 if (vb->state == VIDEOBUF_NEEDS_INIT) {
587 ret = videobuf_iolock(vq, vb, NULL);
588 if (ret)
589 goto fail;
590
591 vb->state = VIDEOBUF_PREPARED;
592 }
593
594 return 0; 584 return 0;
595 585
596fail:
597 free_buffer(vq, buf);
598out: 586out:
599 return ret; 587 return ret;
600} 588}
601 589
602static void mx2_videobuf_queue(struct videobuf_queue *vq, 590static void mx2_videobuf_queue(struct vb2_buffer *vb)
603 struct videobuf_buffer *vb)
604{ 591{
605 struct soc_camera_device *icd = vq->priv_data; 592 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
606 struct soc_camera_host *ici = 593 struct soc_camera_host *ici =
607 to_soc_camera_host(icd->parent); 594 to_soc_camera_host(icd->parent);
608 struct mx2_camera_dev *pcdev = ici->priv; 595 struct mx2_camera_dev *pcdev = ici->priv;
609 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 596 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
610 unsigned long flags; 597 unsigned long flags;
611 598
612 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 599 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
613 vb, vb->baddr, vb->bsize); 600 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
614 601
615 spin_lock_irqsave(&pcdev->lock, flags); 602 spin_lock_irqsave(&pcdev->lock, flags);
616 603
617 vb->state = VIDEOBUF_QUEUED; 604 buf->state = MX2_STATE_QUEUED;
618 list_add_tail(&vb->queue, &pcdev->capture); 605 list_add_tail(&buf->internal.queue, &pcdev->capture);
619 606
620 if (mx27_camera_emma(pcdev)) { 607 if (cpu_is_mx25()) {
621 goto out;
622#ifdef CONFIG_MACH_MX27
623 } else if (cpu_is_mx27()) {
624 int ret;
625
626 if (pcdev->active == NULL) {
627 ret = imx_dma_setup_single(pcdev->dma,
628 videobuf_to_dma_contig(vb), vb->size,
629 (u32)pcdev->base_dma + 0x10,
630 DMA_MODE_READ);
631 if (ret) {
632 vb->state = VIDEOBUF_ERROR;
633 wake_up(&vb->done);
634 goto out;
635 }
636
637 vb->state = VIDEOBUF_ACTIVE;
638 pcdev->active = buf;
639 }
640#endif
641 } else { /* cpu_is_mx25() */
642 u32 csicr3, dma_inten = 0; 608 u32 csicr3, dma_inten = 0;
643 609
644 if (pcdev->fb1_active == NULL) { 610 if (pcdev->fb1_active == NULL) {
645 writel(videobuf_to_dma_contig(vb), 611 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
646 pcdev->base_csi + CSIDMASA_FB1); 612 pcdev->base_csi + CSIDMASA_FB1);
647 pcdev->fb1_active = buf; 613 pcdev->fb1_active = buf;
648 dma_inten = CSICR1_FB1_DMA_INTEN; 614 dma_inten = CSICR1_FB1_DMA_INTEN;
649 } else if (pcdev->fb2_active == NULL) { 615 } else if (pcdev->fb2_active == NULL) {
650 writel(videobuf_to_dma_contig(vb), 616 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
651 pcdev->base_csi + CSIDMASA_FB2); 617 pcdev->base_csi + CSIDMASA_FB2);
652 pcdev->fb2_active = buf; 618 pcdev->fb2_active = buf;
653 dma_inten = CSICR1_FB2_DMA_INTEN; 619 dma_inten = CSICR1_FB2_DMA_INTEN;
654 } 620 }
655 621
656 if (dma_inten) { 622 if (dma_inten) {
657 list_del(&vb->queue); 623 list_del(&buf->internal.queue);
658 vb->state = VIDEOBUF_ACTIVE; 624 buf->state = MX2_STATE_ACTIVE;
659 625
660 csicr3 = readl(pcdev->base_csi + CSICR3); 626 csicr3 = readl(pcdev->base_csi + CSICR3);
661 627
@@ -674,36 +640,31 @@ static void mx2_videobuf_queue(struct videobuf_queue *vq,
674 } 640 }
675 } 641 }
676 642
677out:
678 spin_unlock_irqrestore(&pcdev->lock, flags); 643 spin_unlock_irqrestore(&pcdev->lock, flags);
679} 644}
680 645
681static void mx2_videobuf_release(struct videobuf_queue *vq, 646static void mx2_videobuf_release(struct vb2_buffer *vb)
682 struct videobuf_buffer *vb)
683{ 647{
684 struct soc_camera_device *icd = vq->priv_data; 648 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
685 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 649 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
686 struct mx2_camera_dev *pcdev = ici->priv; 650 struct mx2_camera_dev *pcdev = ici->priv;
687 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 651 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
688 unsigned long flags; 652 unsigned long flags;
689 653
690#ifdef DEBUG 654#ifdef DEBUG
691 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 655 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
692 vb, vb->baddr, vb->bsize); 656 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
693 657
694 switch (vb->state) { 658 switch (buf->state) {
695 case VIDEOBUF_ACTIVE: 659 case MX2_STATE_ACTIVE:
696 dev_info(icd->parent, "%s (active)\n", __func__); 660 dev_info(icd->parent, "%s (active)\n", __func__);
697 break; 661 break;
698 case VIDEOBUF_QUEUED: 662 case MX2_STATE_QUEUED:
699 dev_info(icd->parent, "%s (queued)\n", __func__); 663 dev_info(icd->parent, "%s (queued)\n", __func__);
700 break; 664 break;
701 case VIDEOBUF_PREPARED:
702 dev_info(icd->parent, "%s (prepared)\n", __func__);
703 break;
704 default: 665 default:
705 dev_info(icd->parent, "%s (unknown) %d\n", __func__, 666 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
706 vb->state); 667 buf->state);
707 break; 668 break;
708 } 669 }
709#endif 670#endif
@@ -717,11 +678,9 @@ static void mx2_videobuf_release(struct videobuf_queue *vq,
717 * state. This requires a specific handling for each of the these DMA 678 * state. This requires a specific handling for each of the these DMA
718 * types. 679 * types.
719 */ 680 */
681
720 spin_lock_irqsave(&pcdev->lock, flags); 682 spin_lock_irqsave(&pcdev->lock, flags);
721 if (vb->state == VIDEOBUF_QUEUED) { 683 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
722 list_del(&vb->queue);
723 vb->state = VIDEOBUF_ERROR;
724 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) {
725 if (pcdev->fb1_active == buf) { 684 if (pcdev->fb1_active == buf) {
726 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN; 685 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
727 writel(0, pcdev->base_csi + CSIDMASA_FB1); 686 writel(0, pcdev->base_csi + CSIDMASA_FB1);
@@ -732,75 +691,178 @@ static void mx2_videobuf_release(struct videobuf_queue *vq,
732 pcdev->fb2_active = NULL; 691 pcdev->fb2_active = NULL;
733 } 692 }
734 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 693 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
735 vb->state = VIDEOBUF_ERROR;
736 } 694 }
737 spin_unlock_irqrestore(&pcdev->lock, flags); 695 spin_unlock_irqrestore(&pcdev->lock, flags);
738
739 free_buffer(vq, buf);
740} 696}
741 697
742static struct videobuf_queue_ops mx2_videobuf_ops = { 698static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
743 .buf_setup = mx2_videobuf_setup, 699 int bytesperline)
744 .buf_prepare = mx2_videobuf_prepare,
745 .buf_queue = mx2_videobuf_queue,
746 .buf_release = mx2_videobuf_release,
747};
748
749static void mx2_camera_init_videobuf(struct videobuf_queue *q,
750 struct soc_camera_device *icd)
751{ 700{
752 struct soc_camera_host *ici = to_soc_camera_host(icd->parent); 701 struct soc_camera_host *ici =
702 to_soc_camera_host(icd->parent);
753 struct mx2_camera_dev *pcdev = ici->priv; 703 struct mx2_camera_dev *pcdev = ici->priv;
704 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
754 705
755 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, 706 writel((pcdev->s_width << 16) | pcdev->s_height,
756 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, 707 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
757 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), 708 writel(prp->cfg.src_pixel,
758 icd, &icd->video_lock); 709 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
759} 710 if (prp->cfg.channel == 1) {
711 writel((icd->user_width << 16) | icd->user_height,
712 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
713 writel(bytesperline,
714 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
715 writel(prp->cfg.ch1_pixel,
716 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
717 } else { /* channel 2 */
718 writel((icd->user_width << 16) | icd->user_height,
719 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
720 }
760 721
761#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \ 722 /* Enable interrupts */
762 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \ 723 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
763 V4L2_MBUS_VSYNC_ACTIVE_LOW | \ 724}
764 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
765 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
766 V4L2_MBUS_PCLK_SAMPLE_RISING | \
767 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
768 V4L2_MBUS_DATA_ACTIVE_HIGH | \
769 V4L2_MBUS_DATA_ACTIVE_LOW)
770 725
771static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 726static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
772{ 727{
773 u32 cntl; 728 int dir;
774 int count = 0;
775 729
776 cntl = readl(pcdev->base_emma + PRP_CNTL); 730 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
777 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 731 unsigned char *s = pcdev->resizing[dir].s;
778 while (count++ < 100) { 732 int len = pcdev->resizing[dir].len;
779 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 733 unsigned int coeff[2] = {0, 0};
780 return 0; 734 unsigned int valid = 0;
781 barrier(); 735 int i;
782 udelay(1);
783 }
784 736
785 return -ETIMEDOUT; 737 if (len == 0)
738 continue;
739
740 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
741 int j;
742
743 j = i > 9 ? 1 : 0;
744 coeff[j] = (coeff[j] << BC_COEF) |
745 (s[i] & (SZ_COEF - 1));
746
747 if (i == 5 || i == 15)
748 coeff[j] <<= 1;
749
750 valid = (valid << 1) | (s[i] >> BC_COEF);
751 }
752
753 valid |= PRP_RZ_VALID_TBL_LEN(len);
754
755 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
756 valid |= PRP_RZ_VALID_BILINEAR;
757
758 if (pcdev->emma_prp->cfg.channel == 1) {
759 if (dir == RESIZE_DIR_H) {
760 writel(coeff[0], pcdev->base_emma +
761 PRP_CH1_RZ_HORI_COEF1);
762 writel(coeff[1], pcdev->base_emma +
763 PRP_CH1_RZ_HORI_COEF2);
764 writel(valid, pcdev->base_emma +
765 PRP_CH1_RZ_HORI_VALID);
766 } else {
767 writel(coeff[0], pcdev->base_emma +
768 PRP_CH1_RZ_VERT_COEF1);
769 writel(coeff[1], pcdev->base_emma +
770 PRP_CH1_RZ_VERT_COEF2);
771 writel(valid, pcdev->base_emma +
772 PRP_CH1_RZ_VERT_VALID);
773 }
774 } else {
775 if (dir == RESIZE_DIR_H) {
776 writel(coeff[0], pcdev->base_emma +
777 PRP_CH2_RZ_HORI_COEF1);
778 writel(coeff[1], pcdev->base_emma +
779 PRP_CH2_RZ_HORI_COEF2);
780 writel(valid, pcdev->base_emma +
781 PRP_CH2_RZ_HORI_VALID);
782 } else {
783 writel(coeff[0], pcdev->base_emma +
784 PRP_CH2_RZ_VERT_COEF1);
785 writel(coeff[1], pcdev->base_emma +
786 PRP_CH2_RZ_VERT_COEF2);
787 writel(valid, pcdev->base_emma +
788 PRP_CH2_RZ_VERT_VALID);
789 }
790 }
791 }
786} 792}
787 793
788static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 794static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
789 int bytesperline)
790{ 795{
796 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
791 struct soc_camera_host *ici = 797 struct soc_camera_host *ici =
792 to_soc_camera_host(icd->parent); 798 to_soc_camera_host(icd->parent);
793 struct mx2_camera_dev *pcdev = ici->priv; 799 struct mx2_camera_dev *pcdev = ici->priv;
794 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 800 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
795 u32 imgsize = pcdev->icd->user_height * pcdev->icd->user_width; 801 struct vb2_buffer *vb;
802 struct mx2_buffer *buf;
803 unsigned long phys;
804 int bytesperline;
796 805
797 if (prp->cfg.channel == 1) { 806 if (cpu_is_mx27()) {
798 writel(pcdev->discard_buffer_dma, 807 unsigned long flags;
799 pcdev->base_emma + PRP_DEST_RGB1_PTR); 808 if (count < 2)
800 writel(pcdev->discard_buffer_dma, 809 return -EINVAL;
801 pcdev->base_emma + PRP_DEST_RGB2_PTR); 810
811 spin_lock_irqsave(&pcdev->lock, flags);
812
813 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
814 internal.queue);
815 buf->internal.bufnum = 0;
816 vb = &buf->vb;
817 buf->state = MX2_STATE_ACTIVE;
818
819 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
820 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
821 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
822
823 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
824 internal.queue);
825 buf->internal.bufnum = 1;
826 vb = &buf->vb;
827 buf->state = MX2_STATE_ACTIVE;
802 828
803 writel(PRP_CNTL_CH1EN | 829 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
830 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
831 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
832
833 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
834 icd->current_fmt->host_fmt);
835 if (bytesperline < 0)
836 return bytesperline;
837
838 /*
839 * I didn't manage to properly enable/disable the prp
840 * on a per frame basis during running transfers,
841 * thus we allocate a buffer here and use it to
842 * discard frames when no buffer is available.
843 * Feel free to work on this ;)
844 */
845 pcdev->discard_size = icd->user_height * bytesperline;
846 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
847 pcdev->discard_size, &pcdev->discard_buffer_dma,
848 GFP_KERNEL);
849 if (!pcdev->discard_buffer)
850 return -ENOMEM;
851
852 pcdev->buf_discard[0].discard = true;
853 list_add_tail(&pcdev->buf_discard[0].queue,
854 &pcdev->discard);
855
856 pcdev->buf_discard[1].discard = true;
857 list_add_tail(&pcdev->buf_discard[1].queue,
858 &pcdev->discard);
859
860 mx2_prp_resize_commit(pcdev);
861
862 mx27_camera_emma_buf_init(icd, bytesperline);
863
864 if (prp->cfg.channel == 1) {
865 writel(PRP_CNTL_CH1EN |
804 PRP_CNTL_CSIEN | 866 PRP_CNTL_CSIEN |
805 prp->cfg.in_fmt | 867 prp->cfg.in_fmt |
806 prp->cfg.out_fmt | 868 prp->cfg.out_fmt |
@@ -809,56 +871,107 @@ static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
809 PRP_CNTL_CH1_TSKIP(0) | 871 PRP_CNTL_CH1_TSKIP(0) |
810 PRP_CNTL_IN_TSKIP(0), 872 PRP_CNTL_IN_TSKIP(0),
811 pcdev->base_emma + PRP_CNTL); 873 pcdev->base_emma + PRP_CNTL);
874 } else {
875 writel(PRP_CNTL_CH2EN |
876 PRP_CNTL_CSIEN |
877 prp->cfg.in_fmt |
878 prp->cfg.out_fmt |
879 PRP_CNTL_CH2_LEN |
880 PRP_CNTL_CH2_TSKIP(0) |
881 PRP_CNTL_IN_TSKIP(0),
882 pcdev->base_emma + PRP_CNTL);
883 }
884 spin_unlock_irqrestore(&pcdev->lock, flags);
885 }
812 886
813 writel((icd->user_width << 16) | icd->user_height, 887 return 0;
814 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 888}
815 writel((icd->user_width << 16) | icd->user_height, 889
816 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 890static int mx2_stop_streaming(struct vb2_queue *q)
817 writel(bytesperline, 891{
818 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 892 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
819 writel(prp->cfg.src_pixel, 893 struct soc_camera_host *ici =
820 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 894 to_soc_camera_host(icd->parent);
821 writel(prp->cfg.ch1_pixel, 895 struct mx2_camera_dev *pcdev = ici->priv;
822 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 896 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
823 } else { /* channel 2 */ 897 unsigned long flags;
824 writel(pcdev->discard_buffer_dma, 898 void *b;
825 pcdev->base_emma + PRP_DEST_Y_PTR); 899 u32 cntl;
826 writel(pcdev->discard_buffer_dma, 900
827 pcdev->base_emma + PRP_SOURCE_Y_PTR); 901 if (cpu_is_mx27()) {
828 902 spin_lock_irqsave(&pcdev->lock, flags);
829 if (prp->cfg.out_fmt == PRP_CNTL_CH2_OUT_YUV420) { 903
830 writel(pcdev->discard_buffer_dma + imgsize, 904 cntl = readl(pcdev->base_emma + PRP_CNTL);
831 pcdev->base_emma + PRP_DEST_CB_PTR); 905 if (prp->cfg.channel == 1) {
832 writel(pcdev->discard_buffer_dma + ((5 * imgsize) / 4), 906 writel(cntl & ~PRP_CNTL_CH1EN,
833 pcdev->base_emma + PRP_DEST_CR_PTR); 907 pcdev->base_emma + PRP_CNTL);
834 writel(pcdev->discard_buffer_dma + imgsize, 908 } else {
835 pcdev->base_emma + PRP_SOURCE_CB_PTR); 909 writel(cntl & ~PRP_CNTL_CH2EN,
836 writel(pcdev->discard_buffer_dma + ((5 * imgsize) / 4), 910 pcdev->base_emma + PRP_CNTL);
837 pcdev->base_emma + PRP_SOURCE_CR_PTR);
838 } 911 }
912 INIT_LIST_HEAD(&pcdev->capture);
913 INIT_LIST_HEAD(&pcdev->active_bufs);
914 INIT_LIST_HEAD(&pcdev->discard);
839 915
840 writel(PRP_CNTL_CH2EN | 916 b = pcdev->discard_buffer;
841 PRP_CNTL_CSIEN | 917 pcdev->discard_buffer = NULL;
842 prp->cfg.in_fmt |
843 prp->cfg.out_fmt |
844 PRP_CNTL_CH2_LEN |
845 PRP_CNTL_CH2_TSKIP(0) |
846 PRP_CNTL_IN_TSKIP(0),
847 pcdev->base_emma + PRP_CNTL);
848 918
849 writel((icd->user_width << 16) | icd->user_height, 919 spin_unlock_irqrestore(&pcdev->lock, flags);
850 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
851 920
852 writel((icd->user_width << 16) | icd->user_height, 921 dma_free_coherent(ici->v4l2_dev.dev,
853 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE); 922 pcdev->discard_size, b, pcdev->discard_buffer_dma);
923 }
854 924
855 writel(prp->cfg.src_pixel, 925 return 0;
856 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 926}
927
928static struct vb2_ops mx2_videobuf_ops = {
929 .queue_setup = mx2_videobuf_setup,
930 .buf_prepare = mx2_videobuf_prepare,
931 .buf_queue = mx2_videobuf_queue,
932 .buf_cleanup = mx2_videobuf_release,
933 .start_streaming = mx2_start_streaming,
934 .stop_streaming = mx2_stop_streaming,
935};
936
937static int mx2_camera_init_videobuf(struct vb2_queue *q,
938 struct soc_camera_device *icd)
939{
940 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
941 q->io_modes = VB2_MMAP | VB2_USERPTR;
942 q->drv_priv = icd;
943 q->ops = &mx2_videobuf_ops;
944 q->mem_ops = &vb2_dma_contig_memops;
945 q->buf_struct_size = sizeof(struct mx2_buffer);
946
947 return vb2_queue_init(q);
948}
857 949
950#define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
951 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
952 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
953 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
954 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
955 V4L2_MBUS_PCLK_SAMPLE_RISING | \
956 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
957 V4L2_MBUS_DATA_ACTIVE_HIGH | \
958 V4L2_MBUS_DATA_ACTIVE_LOW)
959
960static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
961{
962 u32 cntl;
963 int count = 0;
964
965 cntl = readl(pcdev->base_emma + PRP_CNTL);
966 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
967 while (count++ < 100) {
968 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
969 return 0;
970 barrier();
971 udelay(1);
858 } 972 }
859 973
860 /* Enable interrupts */ 974 return -ETIMEDOUT;
861 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
862} 975}
863 976
864static int mx2_camera_set_bus_param(struct soc_camera_device *icd) 977static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
@@ -939,31 +1052,10 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
939 if (bytesperline < 0) 1052 if (bytesperline < 0)
940 return bytesperline; 1053 return bytesperline;
941 1054
942 if (mx27_camera_emma(pcdev)) { 1055 if (cpu_is_mx27()) {
943 ret = mx27_camera_emma_prp_reset(pcdev); 1056 ret = mx27_camera_emma_prp_reset(pcdev);
944 if (ret) 1057 if (ret)
945 return ret; 1058 return ret;
946
947 if (pcdev->discard_buffer)
948 dma_free_coherent(ici->v4l2_dev.dev,
949 pcdev->discard_size, pcdev->discard_buffer,
950 pcdev->discard_buffer_dma);
951
952 /*
953 * I didn't manage to properly enable/disable the prp
954 * on a per frame basis during running transfers,
955 * thus we allocate a buffer here and use it to
956 * discard frames when no buffer is available.
957 * Feel free to work on this ;)
958 */
959 pcdev->discard_size = icd->user_height * bytesperline;
960 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
961 pcdev->discard_size, &pcdev->discard_buffer_dma,
962 GFP_KERNEL);
963 if (!pcdev->discard_buffer)
964 return -ENOMEM;
965
966 mx27_camera_emma_buf_init(icd, bytesperline);
967 } else if (cpu_is_mx25()) { 1059 } else if (cpu_is_mx25()) {
968 writel((bytesperline * icd->user_height) >> 2, 1060 writel((bytesperline * icd->user_height) >> 2,
969 pcdev->base_csi + CSIRXCNT); 1061 pcdev->base_csi + CSIRXCNT);
@@ -1052,6 +1144,123 @@ static int mx2_camera_get_formats(struct soc_camera_device *icd,
1052 return formats; 1144 return formats;
1053} 1145}
1054 1146
1147static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1148 struct v4l2_mbus_framefmt *mf_in,
1149 struct v4l2_pix_format *pix_out, bool apply)
1150{
1151 int num, den;
1152 unsigned long m;
1153 int i, dir;
1154
1155 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1156 struct emma_prp_resize tmprsz;
1157 unsigned char *s = tmprsz.s;
1158 int len = 0;
1159 int in, out;
1160
1161 if (dir == RESIZE_DIR_H) {
1162 in = mf_in->width;
1163 out = pix_out->width;
1164 } else {
1165 in = mf_in->height;
1166 out = pix_out->height;
1167 }
1168
1169 if (in < out)
1170 return -EINVAL;
1171 else if (in == out)
1172 continue;
1173
1174 /* Calculate ratio */
1175 m = gcd(in, out);
1176 num = in / m;
1177 den = out / m;
1178 if (num > RESIZE_NUM_MAX)
1179 return -EINVAL;
1180
1181 if ((num >= 2 * den) && (den == 1) &&
1182 (num < 9) && (!(num & 0x01))) {
1183 int sum = 0;
1184 int j;
1185
1186 /* Average scaling for >= 2:1 ratios */
1187 /* Support can be added for num >=9 and odd values */
1188
1189 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1190 len = num;
1191
1192 for (i = 0; i < (len / 2); i++)
1193 s[i] = 8;
1194
1195 do {
1196 for (i = 0; i < (len / 2); i++) {
1197 s[i] = s[i] >> 1;
1198 sum = 0;
1199 for (j = 0; j < (len / 2); j++)
1200 sum += s[j];
1201 if (sum == 4)
1202 break;
1203 }
1204 } while (sum != 4);
1205
1206 for (i = (len / 2); i < len; i++)
1207 s[i] = s[len - i - 1];
1208
1209 s[len - 1] |= SZ_COEF;
1210 } else {
1211 /* bilinear scaling for < 2:1 ratios */
1212 int v; /* overflow counter */
1213 int coeff, nxt; /* table output */
1214 int in_pos_inc = 2 * den;
1215 int out_pos = num;
1216 int out_pos_inc = 2 * num;
1217 int init_carry = num - den;
1218 int carry = init_carry;
1219
1220 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1221 v = den + in_pos_inc;
1222 do {
1223 coeff = v - out_pos;
1224 out_pos += out_pos_inc;
1225 carry += out_pos_inc;
1226 for (nxt = 0; v < out_pos; nxt++) {
1227 v += in_pos_inc;
1228 carry -= in_pos_inc;
1229 }
1230
1231 if (len > RESIZE_NUM_MAX)
1232 return -EINVAL;
1233
1234 coeff = ((coeff << BC_COEF) +
1235 (in_pos_inc >> 1)) / in_pos_inc;
1236
1237 if (coeff >= (SZ_COEF - 1))
1238 coeff--;
1239
1240 coeff |= SZ_COEF;
1241 s[len] = (unsigned char)coeff;
1242 len++;
1243
1244 for (i = 1; i < nxt; i++) {
1245 if (len >= RESIZE_NUM_MAX)
1246 return -EINVAL;
1247 s[len] = 0;
1248 len++;
1249 }
1250 } while (carry != init_carry);
1251 }
1252 tmprsz.len = len;
1253 if (dir == RESIZE_DIR_H)
1254 mf_in->width = pix_out->width;
1255 else
1256 mf_in->height = pix_out->height;
1257
1258 if (apply)
1259 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1260 }
1261 return 0;
1262}
1263
1055static int mx2_camera_set_fmt(struct soc_camera_device *icd, 1264static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1056 struct v4l2_format *f) 1265 struct v4l2_format *f)
1057{ 1266{
@@ -1063,6 +1272,9 @@ static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1063 struct v4l2_mbus_framefmt mf; 1272 struct v4l2_mbus_framefmt mf;
1064 int ret; 1273 int ret;
1065 1274
1275 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1276 __func__, pix->width, pix->height);
1277
1066 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 1278 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1067 if (!xlate) { 1279 if (!xlate) {
1068 dev_warn(icd->parent, "Format %x not found\n", 1280 dev_warn(icd->parent, "Format %x not found\n",
@@ -1080,6 +1292,22 @@ static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1080 if (ret < 0 && ret != -ENOIOCTLCMD) 1292 if (ret < 0 && ret != -ENOIOCTLCMD)
1081 return ret; 1293 return ret;
1082 1294
1295 /* Store width and height returned by the sensor for resizing */
1296 pcdev->s_width = mf.width;
1297 pcdev->s_height = mf.height;
1298 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1299 __func__, pcdev->s_width, pcdev->s_height);
1300
1301 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1302 xlate->host_fmt->fourcc);
1303
1304 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1305 if ((mf.width != pix->width || mf.height != pix->height) &&
1306 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1307 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1308 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1309 }
1310
1083 if (mf.code != xlate->code) 1311 if (mf.code != xlate->code)
1084 return -EINVAL; 1312 return -EINVAL;
1085 1313
@@ -1089,9 +1317,8 @@ static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1089 pix->colorspace = mf.colorspace; 1317 pix->colorspace = mf.colorspace;
1090 icd->current_fmt = xlate; 1318 icd->current_fmt = xlate;
1091 1319
1092 if (mx27_camera_emma(pcdev)) 1320 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1093 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code, 1321 __func__, pix->width, pix->height);
1094 xlate->host_fmt->fourcc);
1095 1322
1096 return 0; 1323 return 0;
1097} 1324}
@@ -1104,9 +1331,14 @@ static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1104 struct v4l2_pix_format *pix = &f->fmt.pix; 1331 struct v4l2_pix_format *pix = &f->fmt.pix;
1105 struct v4l2_mbus_framefmt mf; 1332 struct v4l2_mbus_framefmt mf;
1106 __u32 pixfmt = pix->pixelformat; 1333 __u32 pixfmt = pix->pixelformat;
1334 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1335 struct mx2_camera_dev *pcdev = ici->priv;
1107 unsigned int width_limit; 1336 unsigned int width_limit;
1108 int ret; 1337 int ret;
1109 1338
1339 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1340 __func__, pix->width, pix->height);
1341
1110 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 1342 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1111 if (pixfmt && !xlate) { 1343 if (pixfmt && !xlate) {
1112 dev_warn(icd->parent, "Format %x not found\n", pixfmt); 1344 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
@@ -1156,6 +1388,20 @@ static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1156 if (ret < 0) 1388 if (ret < 0)
1157 return ret; 1389 return ret;
1158 1390
1391 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1392 __func__, pcdev->s_width, pcdev->s_height);
1393
1394 /* If the sensor does not support image size try PrP resizing */
1395 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1396 xlate->host_fmt->fourcc);
1397
1398 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1399 if ((mf.width != pix->width || mf.height != pix->height) &&
1400 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1401 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1402 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1403 }
1404
1159 if (mf.field == V4L2_FIELD_ANY) 1405 if (mf.field == V4L2_FIELD_ANY)
1160 mf.field = V4L2_FIELD_NONE; 1406 mf.field = V4L2_FIELD_NONE;
1161 /* 1407 /*
@@ -1174,6 +1420,9 @@ static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1174 pix->field = mf.field; 1420 pix->field = mf.field;
1175 pix->colorspace = mf.colorspace; 1421 pix->colorspace = mf.colorspace;
1176 1422
1423 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1424 __func__, pix->width, pix->height);
1425
1177 return 0; 1426 return 0;
1178} 1427}
1179 1428
@@ -1187,136 +1436,11 @@ static int mx2_camera_querycap(struct soc_camera_host *ici,
1187 return 0; 1436 return 0;
1188} 1437}
1189 1438
1190static int mx2_camera_reqbufs(struct soc_camera_device *icd,
1191 struct v4l2_requestbuffers *p)
1192{
1193 int i;
1194
1195 for (i = 0; i < p->count; i++) {
1196 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1197 struct mx2_buffer, vb);
1198 INIT_LIST_HEAD(&buf->vb.queue);
1199 }
1200
1201 return 0;
1202}
1203
1204#ifdef CONFIG_MACH_MX27
1205static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
1206{
1207 struct videobuf_buffer *vb;
1208 struct mx2_buffer *buf;
1209 unsigned long flags;
1210 int ret;
1211
1212 spin_lock_irqsave(&pcdev->lock, flags);
1213
1214 if (!pcdev->active) {
1215 dev_err(pcdev->dev, "%s called with no active buffer!\n",
1216 __func__);
1217 goto out;
1218 }
1219
1220 vb = &pcdev->active->vb;
1221 buf = container_of(vb, struct mx2_buffer, vb);
1222 WARN_ON(list_empty(&vb->queue));
1223 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
1224 vb, vb->baddr, vb->bsize);
1225
1226 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1227 list_del_init(&vb->queue);
1228 vb->state = state;
1229 do_gettimeofday(&vb->ts);
1230 vb->field_count++;
1231
1232 wake_up(&vb->done);
1233
1234 if (list_empty(&pcdev->capture)) {
1235 pcdev->active = NULL;
1236 goto out;
1237 }
1238
1239 pcdev->active = list_entry(pcdev->capture.next,
1240 struct mx2_buffer, vb.queue);
1241
1242 vb = &pcdev->active->vb;
1243 vb->state = VIDEOBUF_ACTIVE;
1244
1245 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
1246 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
1247
1248 if (ret) {
1249 vb->state = VIDEOBUF_ERROR;
1250 pcdev->active = NULL;
1251 wake_up(&vb->done);
1252 }
1253
1254out:
1255 spin_unlock_irqrestore(&pcdev->lock, flags);
1256}
1257
1258static void mx27_camera_dma_err_callback(int channel, void *data, int err)
1259{
1260 struct mx2_camera_dev *pcdev = data;
1261
1262 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
1263}
1264
1265static void mx27_camera_dma_callback(int channel, void *data)
1266{
1267 struct mx2_camera_dev *pcdev = data;
1268
1269 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
1270}
1271
1272#define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1273
1274static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
1275 struct mx2_camera_dev *pcdev)
1276{
1277 int err;
1278
1279 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
1280 if (pcdev->dma < 0) {
1281 dev_err(&pdev->dev, "%s failed to request DMA channel\n",
1282 __func__);
1283 return pcdev->dma;
1284 }
1285
1286 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
1287 mx27_camera_dma_err_callback, pcdev);
1288 if (err) {
1289 dev_err(&pdev->dev, "%s failed to set DMA callback\n",
1290 __func__);
1291 goto err_out;
1292 }
1293
1294 err = imx_dma_config_channel(pcdev->dma,
1295 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
1296 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
1297 DMA_REQ_CSI_RX, 1);
1298 if (err) {
1299 dev_err(&pdev->dev, "%s failed to config DMA channel\n",
1300 __func__);
1301 goto err_out;
1302 }
1303
1304 imx_dma_config_burstlen(pcdev->dma, 64);
1305
1306 return 0;
1307
1308err_out:
1309 imx_dma_free(pcdev->dma);
1310
1311 return err;
1312}
1313#endif /* CONFIG_MACH_MX27 */
1314
1315static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1439static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1316{ 1440{
1317 struct soc_camera_device *icd = file->private_data; 1441 struct soc_camera_device *icd = file->private_data;
1318 1442
1319 return videobuf_poll_stream(file, &icd->vb_vidq, pt); 1443 return vb2_poll(&icd->vb2_vidq, file, pt);
1320} 1444}
1321 1445
1322static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1446static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
@@ -1327,144 +1451,148 @@ static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1327 .set_crop = mx2_camera_set_crop, 1451 .set_crop = mx2_camera_set_crop,
1328 .get_formats = mx2_camera_get_formats, 1452 .get_formats = mx2_camera_get_formats,
1329 .try_fmt = mx2_camera_try_fmt, 1453 .try_fmt = mx2_camera_try_fmt,
1330 .init_videobuf = mx2_camera_init_videobuf, 1454 .init_videobuf2 = mx2_camera_init_videobuf,
1331 .reqbufs = mx2_camera_reqbufs,
1332 .poll = mx2_camera_poll, 1455 .poll = mx2_camera_poll,
1333 .querycap = mx2_camera_querycap, 1456 .querycap = mx2_camera_querycap,
1334 .set_bus_param = mx2_camera_set_bus_param, 1457 .set_bus_param = mx2_camera_set_bus_param,
1335}; 1458};
1336 1459
1337static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1460static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1338 int bufnum, int state) 1461 int bufnum, bool err)
1339{ 1462{
1340 u32 imgsize = pcdev->icd->user_height * pcdev->icd->user_width; 1463#ifdef DEBUG
1341 struct mx2_fmt_cfg *prp = pcdev->emma_prp; 1464 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1465#endif
1466 struct mx2_buf_internal *ibuf;
1342 struct mx2_buffer *buf; 1467 struct mx2_buffer *buf;
1343 struct videobuf_buffer *vb; 1468 struct vb2_buffer *vb;
1344 unsigned long phys; 1469 unsigned long phys;
1345 1470
1346 if (!list_empty(&pcdev->active_bufs)) { 1471 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1347 buf = list_entry(pcdev->active_bufs.next, 1472 queue);
1348 struct mx2_buffer, vb.queue); 1473
1474 BUG_ON(ibuf->bufnum != bufnum);
1349 1475
1350 BUG_ON(buf->bufnum != bufnum); 1476 if (ibuf->discard) {
1477 /*
1478 * Discard buffer must not be returned to user space.
1479 * Just return it to the discard queue.
1480 */
1481 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1482 } else {
1483 buf = mx2_ibuf_to_buf(ibuf);
1351 1484
1352 vb = &buf->vb; 1485 vb = &buf->vb;
1353#ifdef DEBUG 1486#ifdef DEBUG
1354 phys = videobuf_to_dma_contig(vb); 1487 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1355 if (prp->cfg.channel == 1) { 1488 if (prp->cfg.channel == 1) {
1356 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 1489 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1357 4 * bufnum) != phys) { 1490 4 * bufnum) != phys) {
1358 dev_err(pcdev->dev, "%p != %p\n", phys, 1491 dev_err(pcdev->dev, "%lx != %x\n", phys,
1359 readl(pcdev->base_emma + 1492 readl(pcdev->base_emma +
1360 PRP_DEST_RGB1_PTR + 1493 PRP_DEST_RGB1_PTR + 4 * bufnum));
1361 4 * bufnum));
1362 } 1494 }
1363 } else { 1495 } else {
1364 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR - 1496 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1365 0x14 * bufnum) != phys) { 1497 0x14 * bufnum) != phys) {
1366 dev_err(pcdev->dev, "%p != %p\n", phys, 1498 dev_err(pcdev->dev, "%lx != %x\n", phys,
1367 readl(pcdev->base_emma + 1499 readl(pcdev->base_emma +
1368 PRP_DEST_Y_PTR - 1500 PRP_DEST_Y_PTR - 0x14 * bufnum));
1369 0x14 * bufnum));
1370 } 1501 }
1371 } 1502 }
1372#endif 1503#endif
1373 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, 1504 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1374 vb->baddr, vb->bsize); 1505 vb2_plane_vaddr(vb, 0),
1506 vb2_get_plane_payload(vb, 0));
1375 1507
1376 list_del(&vb->queue); 1508 list_del_init(&buf->internal.queue);
1377 vb->state = state; 1509 do_gettimeofday(&vb->v4l2_buf.timestamp);
1378 do_gettimeofday(&vb->ts); 1510 vb->v4l2_buf.sequence = pcdev->frame_count;
1379 vb->field_count = pcdev->frame_count * 2; 1511 if (err)
1380 pcdev->frame_count++; 1512 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1381 1513 else
1382 wake_up(&vb->done); 1514 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1383 } 1515 }
1384 1516
1517 pcdev->frame_count++;
1518
1385 if (list_empty(&pcdev->capture)) { 1519 if (list_empty(&pcdev->capture)) {
1386 if (prp->cfg.channel == 1) { 1520 if (list_empty(&pcdev->discard)) {
1387 writel(pcdev->discard_buffer_dma, pcdev->base_emma + 1521 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1388 PRP_DEST_RGB1_PTR + 4 * bufnum); 1522 __func__);
1389 } else { 1523 return;
1390 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1391 PRP_DEST_Y_PTR -
1392 0x14 * bufnum);
1393 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
1394 writel(pcdev->discard_buffer_dma + imgsize,
1395 pcdev->base_emma + PRP_DEST_CB_PTR -
1396 0x14 * bufnum);
1397 writel(pcdev->discard_buffer_dma +
1398 ((5 * imgsize) / 4), pcdev->base_emma +
1399 PRP_DEST_CR_PTR - 0x14 * bufnum);
1400 }
1401 } 1524 }
1525
1526 ibuf = list_first_entry(&pcdev->discard,
1527 struct mx2_buf_internal, queue);
1528 ibuf->bufnum = bufnum;
1529
1530 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1531 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1402 return; 1532 return;
1403 } 1533 }
1404 1534
1405 buf = list_entry(pcdev->capture.next, 1535 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1406 struct mx2_buffer, vb.queue); 1536 internal.queue);
1407 1537
1408 buf->bufnum = !bufnum; 1538 buf->internal.bufnum = bufnum;
1409 1539
1410 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1540 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1411 1541
1412 vb = &buf->vb; 1542 vb = &buf->vb;
1413 vb->state = VIDEOBUF_ACTIVE; 1543 buf->state = MX2_STATE_ACTIVE;
1414 1544
1415 phys = videobuf_to_dma_contig(vb); 1545 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1416 if (prp->cfg.channel == 1) { 1546 mx27_update_emma_buf(pcdev, phys, bufnum);
1417 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
1418 } else {
1419 writel(phys, pcdev->base_emma +
1420 PRP_DEST_Y_PTR - 0x14 * bufnum);
1421 if (prp->cfg.out_fmt == PRP_CNTL_CH2_OUT_YUV420) {
1422 writel(phys + imgsize, pcdev->base_emma +
1423 PRP_DEST_CB_PTR - 0x14 * bufnum);
1424 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
1425 PRP_DEST_CR_PTR - 0x14 * bufnum);
1426 }
1427 }
1428} 1547}
1429 1548
1430static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1549static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1431{ 1550{
1432 struct mx2_camera_dev *pcdev = data; 1551 struct mx2_camera_dev *pcdev = data;
1433 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1552 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1434 struct mx2_buffer *buf; 1553 struct mx2_buf_internal *ibuf;
1554
1555 spin_lock(&pcdev->lock);
1556
1557 if (list_empty(&pcdev->active_bufs)) {
1558 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1559 __func__);
1560
1561 if (!status) {
1562 spin_unlock(&pcdev->lock);
1563 return IRQ_NONE;
1564 }
1565 }
1435 1566
1436 if (status & (1 << 7)) { /* overflow */ 1567 if (status & (1 << 7)) { /* overflow */
1437 u32 cntl; 1568 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1438 /*
1439 * We only disable channel 1 here since this is the only
1440 * enabled channel
1441 *
1442 * FIXME: the correct DMA overflow handling should be resetting
1443 * the buffer, returning an error frame, and continuing with
1444 * the next one.
1445 */
1446 cntl = readl(pcdev->base_emma + PRP_CNTL);
1447 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), 1569 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1448 pcdev->base_emma + PRP_CNTL); 1570 pcdev->base_emma + PRP_CNTL);
1449 writel(cntl, pcdev->base_emma + PRP_CNTL); 1571 writel(cntl, pcdev->base_emma + PRP_CNTL);
1450 } 1572
1451 if ((((status & (3 << 5)) == (3 << 5)) || 1573 ibuf = list_first_entry(&pcdev->active_bufs,
1452 ((status & (3 << 3)) == (3 << 3))) 1574 struct mx2_buf_internal, queue);
1453 && !list_empty(&pcdev->active_bufs)) { 1575 mx27_camera_frame_done_emma(pcdev,
1576 ibuf->bufnum, true);
1577
1578 status &= ~(1 << 7);
1579 } else if (((status & (3 << 5)) == (3 << 5)) ||
1580 ((status & (3 << 3)) == (3 << 3))) {
1454 /* 1581 /*
1455 * Both buffers have triggered, process the one we're expecting 1582 * Both buffers have triggered, process the one we're expecting
1456 * to first 1583 * to first
1457 */ 1584 */
1458 buf = list_entry(pcdev->active_bufs.next, 1585 ibuf = list_first_entry(&pcdev->active_bufs,
1459 struct mx2_buffer, vb.queue); 1586 struct mx2_buf_internal, queue);
1460 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); 1587 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1461 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1588 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1589 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1590 mx27_camera_frame_done_emma(pcdev, 0, false);
1591 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1592 mx27_camera_frame_done_emma(pcdev, 1, false);
1462 } 1593 }
1463 if ((status & (1 << 6)) || (status & (1 << 4)))
1464 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
1465 if ((status & (1 << 5)) || (status & (1 << 3)))
1466 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
1467 1594
1595 spin_unlock(&pcdev->lock);
1468 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1596 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1469 1597
1470 return IRQ_HANDLED; 1598 return IRQ_HANDLED;
@@ -1527,8 +1655,6 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1527 struct resource *res_csi, *res_emma; 1655 struct resource *res_csi, *res_emma;
1528 void __iomem *base_csi; 1656 void __iomem *base_csi;
1529 int irq_csi, irq_emma; 1657 int irq_csi, irq_emma;
1530 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
1531 : mx27_camera_irq;
1532 int err = 0; 1658 int err = 0;
1533 1659
1534 dev_dbg(&pdev->dev, "initialising\n"); 1660 dev_dbg(&pdev->dev, "initialising\n");
@@ -1550,22 +1676,11 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1550 1676
1551 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1677 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1552 if (IS_ERR(pcdev->clk_csi)) { 1678 if (IS_ERR(pcdev->clk_csi)) {
1679 dev_err(&pdev->dev, "Could not get csi clock\n");
1553 err = PTR_ERR(pcdev->clk_csi); 1680 err = PTR_ERR(pcdev->clk_csi);
1554 goto exit_kfree; 1681 goto exit_kfree;
1555 } 1682 }
1556 1683
1557 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1558 clk_get_rate(pcdev->clk_csi));
1559
1560 /* Initialize DMA */
1561#ifdef CONFIG_MACH_MX27
1562 if (cpu_is_mx27()) {
1563 err = mx27_camera_dma_init(pdev, pcdev);
1564 if (err)
1565 goto exit_clk_put;
1566 }
1567#endif /* CONFIG_MACH_MX27 */
1568
1569 pcdev->res_csi = res_csi; 1684 pcdev->res_csi = res_csi;
1570 pcdev->pdata = pdev->dev.platform_data; 1685 pcdev->pdata = pdev->dev.platform_data;
1571 if (pcdev->pdata) { 1686 if (pcdev->pdata) {
@@ -1585,6 +1700,7 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1585 1700
1586 INIT_LIST_HEAD(&pcdev->capture); 1701 INIT_LIST_HEAD(&pcdev->capture);
1587 INIT_LIST_HEAD(&pcdev->active_bufs); 1702 INIT_LIST_HEAD(&pcdev->active_bufs);
1703 INIT_LIST_HEAD(&pcdev->discard);
1588 spin_lock_init(&pcdev->lock); 1704 spin_lock_init(&pcdev->lock);
1589 1705
1590 /* 1706 /*
@@ -1606,11 +1722,13 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1606 pcdev->base_dma = res_csi->start; 1722 pcdev->base_dma = res_csi->start;
1607 pcdev->dev = &pdev->dev; 1723 pcdev->dev = &pdev->dev;
1608 1724
1609 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, 1725 if (cpu_is_mx25()) {
1610 MX2_CAM_DRV_NAME, pcdev); 1726 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0,
1611 if (err) { 1727 MX2_CAM_DRV_NAME, pcdev);
1612 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1728 if (err) {
1613 goto exit_iounmap; 1729 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1730 goto exit_iounmap;
1731 }
1614 } 1732 }
1615 1733
1616 if (cpu_is_mx27()) { 1734 if (cpu_is_mx27()) {
@@ -1618,14 +1736,15 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1618 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1736 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1619 irq_emma = platform_get_irq(pdev, 1); 1737 irq_emma = platform_get_irq(pdev, 1);
1620 1738
1621 if (res_emma && irq_emma >= 0) { 1739 if (!res_emma || !irq_emma) {
1622 dev_info(&pdev->dev, "Using EMMA\n"); 1740 dev_err(&pdev->dev, "no EMMA resources\n");
1623 pcdev->use_emma = 1; 1741 goto exit_free_irq;
1624 pcdev->res_emma = res_emma;
1625 pcdev->irq_emma = irq_emma;
1626 if (mx27_camera_emma_init(pcdev))
1627 goto exit_free_irq;
1628 } 1742 }
1743
1744 pcdev->res_emma = res_emma;
1745 pcdev->irq_emma = irq_emma;
1746 if (mx27_camera_emma_init(pcdev))
1747 goto exit_free_irq;
1629 } 1748 }
1630 1749
1631 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1750 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
@@ -1633,6 +1752,12 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1633 pcdev->soc_host.priv = pcdev; 1752 pcdev->soc_host.priv = pcdev;
1634 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1753 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1635 pcdev->soc_host.nr = pdev->id; 1754 pcdev->soc_host.nr = pdev->id;
1755
1756 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1757 if (IS_ERR(pcdev->alloc_ctx)) {
1758 err = PTR_ERR(pcdev->alloc_ctx);
1759 goto eallocctx;
1760 }
1636 err = soc_camera_host_register(&pcdev->soc_host); 1761 err = soc_camera_host_register(&pcdev->soc_host);
1637 if (err) 1762 if (err)
1638 goto exit_free_emma; 1763 goto exit_free_emma;
@@ -1643,26 +1768,24 @@ static int __devinit mx2_camera_probe(struct platform_device *pdev)
1643 return 0; 1768 return 0;
1644 1769
1645exit_free_emma: 1770exit_free_emma:
1646 if (mx27_camera_emma(pcdev)) { 1771 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1772eallocctx:
1773 if (cpu_is_mx27()) {
1647 free_irq(pcdev->irq_emma, pcdev); 1774 free_irq(pcdev->irq_emma, pcdev);
1648 clk_disable(pcdev->clk_emma); 1775 clk_disable(pcdev->clk_emma);
1649 clk_put(pcdev->clk_emma); 1776 clk_put(pcdev->clk_emma);
1650 iounmap(pcdev->base_emma); 1777 iounmap(pcdev->base_emma);
1651 release_mem_region(res_emma->start, resource_size(res_emma)); 1778 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma));
1652 } 1779 }
1653exit_free_irq: 1780exit_free_irq:
1654 free_irq(pcdev->irq_csi, pcdev); 1781 if (cpu_is_mx25())
1782 free_irq(pcdev->irq_csi, pcdev);
1655exit_iounmap: 1783exit_iounmap:
1656 iounmap(base_csi); 1784 iounmap(base_csi);
1657exit_release: 1785exit_release:
1658 release_mem_region(res_csi->start, resource_size(res_csi)); 1786 release_mem_region(res_csi->start, resource_size(res_csi));
1659exit_dma_free: 1787exit_dma_free:
1660#ifdef CONFIG_MACH_MX27
1661 if (cpu_is_mx27())
1662 imx_dma_free(pcdev->dma);
1663exit_clk_put:
1664 clk_put(pcdev->clk_csi); 1788 clk_put(pcdev->clk_csi);
1665#endif /* CONFIG_MACH_MX27 */
1666exit_kfree: 1789exit_kfree:
1667 kfree(pcdev); 1790 kfree(pcdev);
1668exit: 1791exit:
@@ -1677,19 +1800,18 @@ static int __devexit mx2_camera_remove(struct platform_device *pdev)
1677 struct resource *res; 1800 struct resource *res;
1678 1801
1679 clk_put(pcdev->clk_csi); 1802 clk_put(pcdev->clk_csi);
1680#ifdef CONFIG_MACH_MX27 1803 if (cpu_is_mx25())
1804 free_irq(pcdev->irq_csi, pcdev);
1681 if (cpu_is_mx27()) 1805 if (cpu_is_mx27())
1682 imx_dma_free(pcdev->dma);
1683#endif /* CONFIG_MACH_MX27 */
1684 free_irq(pcdev->irq_csi, pcdev);
1685 if (mx27_camera_emma(pcdev))
1686 free_irq(pcdev->irq_emma, pcdev); 1806 free_irq(pcdev->irq_emma, pcdev);
1687 1807
1688 soc_camera_host_unregister(&pcdev->soc_host); 1808 soc_camera_host_unregister(&pcdev->soc_host);
1689 1809
1810 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1811
1690 iounmap(pcdev->base_csi); 1812 iounmap(pcdev->base_csi);
1691 1813
1692 if (mx27_camera_emma(pcdev)) { 1814 if (cpu_is_mx27()) {
1693 clk_disable(pcdev->clk_emma); 1815 clk_disable(pcdev->clk_emma);
1694 clk_put(pcdev->clk_emma); 1816 clk_put(pcdev->clk_emma);
1695 iounmap(pcdev->base_emma); 1817 iounmap(pcdev->base_emma);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 15:58:43 -0500