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path: root/drivers/media/video/mx1_camera.c
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Diffstat (limited to 'drivers/media/video/mx1_camera.c')
-rw-r--r--drivers/media/video/mx1_camera.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index c167cc3de492..34a66019190e 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -29,6 +29,7 @@
29#include <linux/mutex.h> 29#include <linux/mutex.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/sched.h> 31#include <linux/sched.h>
32#include <linux/slab.h>
32#include <linux/time.h> 33#include <linux/time.h>
33#include <linux/version.h> 34#include <linux/version.h>
34#include <linux/videodev2.h> 35#include <linux/videodev2.h>
@@ -48,8 +49,6 @@
48/* 49/*
49 * CSI registers 50 * CSI registers
50 */ 51 */
51#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
52#define DMA_DIMR 0x08 /* Interrupt mask Register */
53#define CSICR1 0x00 /* CSI Control Register 1 */ 52#define CSICR1 0x00 /* CSI Control Register 1 */
54#define CSISR 0x08 /* CSI Status Register */ 53#define CSISR 0x08 /* CSI Status Register */
55#define CSIRXR 0x10 /* CSI RxFIFO Register */ 54#define CSIRXR 0x10 /* CSI RxFIFO Register */
@@ -783,7 +782,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
783 pcdev); 782 pcdev);
784 783
785 imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO, 784 imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO,
786 IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0); 785 IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0);
787 /* burst length : 16 words = 64 bytes */ 786 /* burst length : 16 words = 64 bytes */
788 imx_dma_config_burstlen(pcdev->dma_chan, 0); 787 imx_dma_config_burstlen(pcdev->dma_chan, 0);
789 788
@@ -797,8 +796,8 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
797 set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end - 796 set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end -
798 &mx1_camera_sof_fiq_start); 797 &mx1_camera_sof_fiq_start);
799 798
800 regs.ARM_r8 = DMA_BASE + DMA_DIMR; 799 regs.ARM_r8 = (long)MX1_DMA_DIMR;
801 regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan); 800 regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan);
802 regs.ARM_r10 = (long)pcdev->base + CSICR1; 801 regs.ARM_r10 = (long)pcdev->base + CSICR1;
803 regs.ARM_fp = (long)pcdev->base + CSISR; 802 regs.ARM_fp = (long)pcdev->base + CSISR;
804 regs.ARM_sp = 1 << pcdev->dma_chan; 803 regs.ARM_sp = 1 << pcdev->dma_chan;