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path: root/drivers/media/video/ivtv/ivtv-irq.c
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Diffstat (limited to 'drivers/media/video/ivtv/ivtv-irq.c')
-rw-r--r--drivers/media/video/ivtv/ivtv-irq.c818
1 files changed, 818 insertions, 0 deletions
diff --git a/drivers/media/video/ivtv/ivtv-irq.c b/drivers/media/video/ivtv/ivtv-irq.c
new file mode 100644
index 000000000000..0656e18b7c7e
--- /dev/null
+++ b/drivers/media/video/ivtv/ivtv-irq.c
@@ -0,0 +1,818 @@
1/* interrupt handling
2 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
3 Copyright (C) 2004 Chris Kennedy <c@groovy.org>
4 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include "ivtv-driver.h"
22#include "ivtv-firmware.h"
23#include "ivtv-fileops.h"
24#include "ivtv-queue.h"
25#include "ivtv-udma.h"
26#include "ivtv-irq.h"
27#include "ivtv-ioctl.h"
28#include "ivtv-mailbox.h"
29#include "ivtv-vbi.h"
30
31#define DMA_MAGIC_COOKIE 0x000001fe
32
33#define SLICED_VBI_PIO 1
34
35static void ivtv_dma_dec_start(struct ivtv_stream *s);
36
37static const int ivtv_stream_map[] = {
38 IVTV_ENC_STREAM_TYPE_MPG,
39 IVTV_ENC_STREAM_TYPE_YUV,
40 IVTV_ENC_STREAM_TYPE_PCM,
41 IVTV_ENC_STREAM_TYPE_VBI,
42};
43
44static inline int ivtv_use_pio(struct ivtv_stream *s)
45{
46 struct ivtv *itv = s->itv;
47
48 return s->dma == PCI_DMA_NONE ||
49 (SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI && itv->vbi.sliced_in->service_set);
50}
51
52/* Determine the required DMA size, setup enough buffers in the predma queue and
53 actually copy the data from the card to the buffers in case a PIO transfer is
54 required for this stream.
55 */
56static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MAX_DATA])
57{
58 struct ivtv *itv = s->itv;
59 struct ivtv_buffer *buf;
60 struct list_head *p;
61 u32 bytes_needed = 0;
62 u32 offset, size;
63 u32 UVoffset = 0, UVsize = 0;
64 int skip_bufs = s->q_predma.buffers;
65 int idx = s->SG_length;
66 int rc;
67
68 /* sanity checks */
69 if (s->v4l2dev == NULL) {
70 IVTV_DEBUG_WARN("Stream %s not started\n", s->name);
71 return -1;
72 }
73 if (!test_bit(IVTV_F_S_CLAIMED, &s->s_flags)) {
74 IVTV_DEBUG_WARN("Stream %s not open\n", s->name);
75 return -1;
76 }
77
78 /* determine offset, size and PTS for the various streams */
79 switch (s->type) {
80 case IVTV_ENC_STREAM_TYPE_MPG:
81 offset = data[1];
82 size = data[2];
83 s->dma_pts = 0;
84 break;
85
86 case IVTV_ENC_STREAM_TYPE_YUV:
87 offset = data[1];
88 size = data[2];
89 UVoffset = data[3];
90 UVsize = data[4];
91 s->dma_pts = ((u64) data[5] << 32) | data[6];
92 break;
93
94 case IVTV_ENC_STREAM_TYPE_PCM:
95 offset = data[1] + 12;
96 size = data[2] - 12;
97 s->dma_pts = read_dec(offset - 8) |
98 ((u64)(read_dec(offset - 12)) << 32);
99 if (itv->has_cx23415)
100 offset += IVTV_DECODER_OFFSET;
101 break;
102
103 case IVTV_ENC_STREAM_TYPE_VBI:
104 size = itv->vbi.enc_size * itv->vbi.fpi;
105 offset = read_enc(itv->vbi.enc_start - 4) + 12;
106 if (offset == 12) {
107 IVTV_DEBUG_INFO("VBI offset == 0\n");
108 return -1;
109 }
110 s->dma_pts = read_enc(offset - 4) | ((u64)read_enc(offset - 8) << 32);
111 break;
112
113 case IVTV_DEC_STREAM_TYPE_VBI:
114 size = read_dec(itv->vbi.dec_start + 4) + 8;
115 offset = read_dec(itv->vbi.dec_start) + itv->vbi.dec_start;
116 s->dma_pts = 0;
117 offset += IVTV_DECODER_OFFSET;
118 break;
119 default:
120 /* shouldn't happen */
121 return -1;
122 }
123
124 /* if this is the start of the DMA then fill in the magic cookie */
125 if (s->SG_length == 0) {
126 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
127 s->type == IVTV_DEC_STREAM_TYPE_VBI)) {
128 s->dma_backup = read_dec(offset - IVTV_DECODER_OFFSET);
129 write_dec_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset - IVTV_DECODER_OFFSET);
130 }
131 else {
132 s->dma_backup = read_enc(offset);
133 write_enc_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset);
134 }
135 s->dma_offset = offset;
136 }
137
138 bytes_needed = size;
139 if (s->type == IVTV_ENC_STREAM_TYPE_YUV) {
140 /* The size for the Y samples needs to be rounded upwards to a
141 multiple of the buf_size. The UV samples then start in the
142 next buffer. */
143 bytes_needed = s->buf_size * ((bytes_needed + s->buf_size - 1) / s->buf_size);
144 bytes_needed += UVsize;
145 }
146
147 IVTV_DEBUG_DMA("%s %s: 0x%08x bytes at 0x%08x\n",
148 ivtv_use_pio(s) ? "PIO" : "DMA", s->name, bytes_needed, offset);
149
150 rc = ivtv_queue_move(s, &s->q_free, &s->q_full, &s->q_predma, bytes_needed);
151 if (rc < 0) { /* Insufficient buffers */
152 IVTV_DEBUG_WARN("Cannot obtain %d bytes for %s data transfer\n",
153 bytes_needed, s->name);
154 return -1;
155 }
156 if (rc && !s->buffers_stolen && (s->s_flags & IVTV_F_S_APPL_IO)) {
157 IVTV_WARN("All %s stream buffers are full. Dropping data.\n", s->name);
158 IVTV_WARN("Cause: the application is not reading fast enough.\n");
159 }
160 s->buffers_stolen = rc;
161
162 /* got the buffers, now fill in SGarray (DMA) or copy the data from the card
163 to the buffers (PIO). */
164 buf = list_entry(s->q_predma.list.next, struct ivtv_buffer, list);
165 memset(buf->buf, 0, 128);
166 list_for_each(p, &s->q_predma.list) {
167 struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
168
169 if (skip_bufs-- > 0)
170 continue;
171 if (!ivtv_use_pio(s)) {
172 s->SGarray[idx].dst = cpu_to_le32(buf->dma_handle);
173 s->SGarray[idx].src = cpu_to_le32(offset);
174 s->SGarray[idx].size = cpu_to_le32(s->buf_size);
175 }
176 buf->bytesused = (size < s->buf_size) ? size : s->buf_size;
177
178 /* If PIO, then copy the data from the card to the buffer */
179 if (s->type == IVTV_DEC_STREAM_TYPE_VBI) {
180 memcpy_fromio(buf->buf, itv->dec_mem + offset - IVTV_DECODER_OFFSET, buf->bytesused);
181 }
182 else if (ivtv_use_pio(s)) {
183 memcpy_fromio(buf->buf, itv->enc_mem + offset, buf->bytesused);
184 }
185
186 s->q_predma.bytesused += buf->bytesused;
187 size -= buf->bytesused;
188 offset += s->buf_size;
189
190 /* Sync SG buffers */
191 ivtv_buf_sync_for_device(s, buf);
192
193 if (size == 0) { /* YUV */
194 /* process the UV section */
195 offset = UVoffset;
196 size = UVsize;
197 }
198 idx++;
199 }
200 s->SG_length = idx;
201 return 0;
202}
203
204static void dma_post(struct ivtv_stream *s)
205{
206 struct ivtv *itv = s->itv;
207 struct ivtv_buffer *buf = NULL;
208 struct list_head *p;
209 u32 offset;
210 u32 *u32buf;
211 int x = 0;
212
213 if (ivtv_use_pio(s)) {
214 if (s->q_predma.bytesused)
215 ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
216 s->SG_length = 0;
217 }
218 IVTV_DEBUG_DMA("%s %s completed (%x)\n", ivtv_use_pio(s) ? "PIO" : "DMA",
219 s->name, s->dma_offset);
220 list_for_each(p, &s->q_dma.list) {
221 buf = list_entry(p, struct ivtv_buffer, list);
222 u32buf = (u32 *)buf->buf;
223
224 /* Sync Buffer */
225 ivtv_buf_sync_for_cpu(s, buf);
226
227 if (x == 0) {
228 offset = s->dma_last_offset;
229 if (u32buf[offset / 4] != DMA_MAGIC_COOKIE)
230 {
231 for (offset = 0; offset < 64; offset++) {
232 if (u32buf[offset] == DMA_MAGIC_COOKIE) {
233 break;
234 }
235 }
236 offset *= 4;
237 if (offset == 256) {
238 IVTV_DEBUG_WARN("%s: Couldn't find start of buffer within the first 256 bytes\n", s->name);
239 offset = s->dma_last_offset;
240 }
241 if (s->dma_last_offset != offset)
242 IVTV_DEBUG_WARN("%s: offset %d -> %d\n", s->name, s->dma_last_offset, offset);
243 s->dma_last_offset = offset;
244 }
245 if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
246 s->type == IVTV_DEC_STREAM_TYPE_VBI)) {
247 write_dec_sync(0, s->dma_offset - IVTV_DECODER_OFFSET);
248 }
249 else {
250 write_enc_sync(0, s->dma_offset);
251 }
252 if (offset) {
253 buf->bytesused -= offset;
254 memcpy(buf->buf, buf->buf + offset, buf->bytesused + offset);
255 }
256 *u32buf = cpu_to_le32(s->dma_backup);
257 }
258 x++;
259 /* flag byteswap ABCD -> DCBA for MPG & VBI data outside irq */
260 if (s->type == IVTV_ENC_STREAM_TYPE_MPG ||
261 s->type == IVTV_ENC_STREAM_TYPE_VBI)
262 set_bit(IVTV_F_B_NEED_BUF_SWAP, &buf->b_flags);
263 }
264 if (buf)
265 buf->bytesused += s->dma_last_offset;
266 if (buf && s->type == IVTV_DEC_STREAM_TYPE_VBI) {
267 /* Parse and Groom VBI Data */
268 s->q_dma.bytesused -= buf->bytesused;
269 ivtv_process_vbi_data(itv, buf, 0, s->type);
270 s->q_dma.bytesused += buf->bytesused;
271 if (s->id == -1) {
272 ivtv_queue_move(s, &s->q_dma, NULL, &s->q_free, 0);
273 return;
274 }
275 }
276 ivtv_queue_move(s, &s->q_dma, NULL, &s->q_full, s->q_dma.bytesused);
277 if (s->id != -1)
278 wake_up(&s->waitq);
279}
280
281void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock)
282{
283 struct ivtv *itv = s->itv;
284 struct ivtv_buffer *buf;
285 struct list_head *p;
286 u32 y_size = itv->params.height * itv->params.width;
287 u32 uv_offset = offset + IVTV_YUV_BUFFER_UV_OFFSET;
288 int y_done = 0;
289 int bytes_written = 0;
290 unsigned long flags = 0;
291 int idx = 0;
292
293 IVTV_DEBUG_DMA("DEC PREPARE DMA %s: %08x %08x\n", s->name, s->q_predma.bytesused, offset);
294 buf = list_entry(s->q_predma.list.next, struct ivtv_buffer, list);
295 list_for_each(p, &s->q_predma.list) {
296 struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
297
298 /* YUV UV Offset from Y Buffer */
299 if (s->type == IVTV_DEC_STREAM_TYPE_YUV && !y_done && bytes_written >= y_size) {
300 offset = uv_offset;
301 y_done = 1;
302 }
303 s->SGarray[idx].src = cpu_to_le32(buf->dma_handle);
304 s->SGarray[idx].dst = cpu_to_le32(offset);
305 s->SGarray[idx].size = cpu_to_le32(buf->bytesused);
306
307 offset += buf->bytesused;
308 bytes_written += buf->bytesused;
309
310 /* Sync SG buffers */
311 ivtv_buf_sync_for_device(s, buf);
312 idx++;
313 }
314 s->SG_length = idx;
315
316 /* Mark last buffer size for Interrupt flag */
317 s->SGarray[s->SG_length - 1].size |= cpu_to_le32(0x80000000);
318
319 /* Sync Hardware SG List of buffers */
320 ivtv_stream_sync_for_device(s);
321 if (lock)
322 spin_lock_irqsave(&itv->dma_reg_lock, flags);
323 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
324 ivtv_dma_dec_start(s);
325 }
326 else {
327 set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
328 }
329 if (lock)
330 spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
331}
332
333/* start the encoder DMA */
334static void ivtv_dma_enc_start(struct ivtv_stream *s)
335{
336 struct ivtv *itv = s->itv;
337 struct ivtv_stream *s_vbi = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
338 int i;
339
340 if (s->q_predma.bytesused)
341 ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
342 IVTV_DEBUG_DMA("start DMA for %s\n", s->name);
343 s->SGarray[s->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s->SGarray[s->SG_length - 1].size) + 256);
344
345 /* If this is an MPEG stream, and VBI data is also pending, then append the
346 VBI DMA to the MPEG DMA and transfer both sets of data at once.
347
348 VBI DMA is a second class citizen compared to MPEG and mixing them together
349 will confuse the firmware (the end of a VBI DMA is seen as the end of a
350 MPEG DMA, thus effectively dropping an MPEG frame). So instead we make
351 sure we only use the MPEG DMA to transfer the VBI DMA if both are in
352 use. This way no conflicts occur. */
353 clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
354 if (s->type == IVTV_ENC_STREAM_TYPE_MPG && s_vbi->SG_length &&
355 s->SG_length + s_vbi->SG_length <= s->buffers) {
356 ivtv_queue_move(s_vbi, &s_vbi->q_predma, NULL, &s_vbi->q_dma, s_vbi->q_predma.bytesused);
357 s_vbi->SGarray[s_vbi->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s_vbi->SGarray[s->SG_length - 1].size) + 256);
358 for (i = 0; i < s_vbi->SG_length; i++) {
359 s->SGarray[s->SG_length++] = s_vbi->SGarray[i];
360 }
361 itv->vbi.dma_offset = s_vbi->dma_offset;
362 s_vbi->SG_length = 0;
363 set_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
364 IVTV_DEBUG_DMA("include DMA for %s\n", s->name);
365 }
366
367 /* Mark last buffer size for Interrupt flag */
368 s->SGarray[s->SG_length - 1].size |= cpu_to_le32(0x80000000);
369
370 /* Sync Hardware SG List of buffers */
371 ivtv_stream_sync_for_device(s);
372 write_reg(s->SG_handle, IVTV_REG_ENCDMAADDR);
373 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
374 set_bit(IVTV_F_I_DMA, &itv->i_flags);
375 itv->cur_dma_stream = s->type;
376 itv->dma_timer.expires = jiffies + HZ / 10;
377 add_timer(&itv->dma_timer);
378}
379
380static void ivtv_dma_dec_start(struct ivtv_stream *s)
381{
382 struct ivtv *itv = s->itv;
383
384 if (s->q_predma.bytesused)
385 ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
386 IVTV_DEBUG_DMA("start DMA for %s\n", s->name);
387 /* put SG Handle into register 0x0c */
388 write_reg(s->SG_handle, IVTV_REG_DECDMAADDR);
389 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
390 set_bit(IVTV_F_I_DMA, &itv->i_flags);
391 itv->cur_dma_stream = s->type;
392 itv->dma_timer.expires = jiffies + HZ / 10;
393 add_timer(&itv->dma_timer);
394}
395
396static void ivtv_irq_dma_read(struct ivtv *itv)
397{
398 struct ivtv_stream *s = NULL;
399 struct ivtv_buffer *buf;
400 int hw_stream_type;
401
402 IVTV_DEBUG_IRQ("DEC DMA READ\n");
403 del_timer(&itv->dma_timer);
404 if (read_reg(IVTV_REG_DMASTATUS) & 0x14) {
405 IVTV_DEBUG_WARN("DEC DMA ERROR %x\n", read_reg(IVTV_REG_DMASTATUS));
406 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
407 }
408 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
409 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
410 s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
411 hw_stream_type = 2;
412 }
413 else {
414 s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
415 hw_stream_type = 0;
416 }
417 IVTV_DEBUG_DMA("DEC DATA READ %s: %d\n", s->name, s->q_dma.bytesused);
418
419 ivtv_stream_sync_for_cpu(s);
420
421 /* For some reason must kick the firmware, like PIO mode,
422 I think this tells the firmware we are done and the size
423 of the xfer so it can calculate what we need next.
424 I think we can do this part ourselves but would have to
425 fully calculate xfer info ourselves and not use interrupts
426 */
427 ivtv_vapi(itv, CX2341X_DEC_SCHED_DMA_FROM_HOST, 3, 0, s->q_dma.bytesused,
428 hw_stream_type);
429
430 /* Free last DMA call */
431 while ((buf = ivtv_dequeue(s, &s->q_dma)) != NULL) {
432 ivtv_buf_sync_for_cpu(s, buf);
433 ivtv_enqueue(s, buf, &s->q_free);
434 }
435 wake_up(&s->waitq);
436 }
437 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
438 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
439 itv->cur_dma_stream = -1;
440 wake_up(&itv->dma_waitq);
441}
442
443static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
444{
445 u32 data[CX2341X_MBOX_MAX_DATA];
446 struct ivtv_stream *s;
447
448 del_timer(&itv->dma_timer);
449 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
450 IVTV_DEBUG_IRQ("ENC DMA COMPLETE %x %d\n", data[0], data[1]);
451 if (test_and_clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags))
452 data[1] = 3;
453 else if (data[1] > 2)
454 return;
455 s = &itv->streams[ivtv_stream_map[data[1]]];
456 if (data[0] & 0x18) {
457 IVTV_DEBUG_WARN("ENC DMA ERROR %x\n", data[0]);
458 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
459 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, data[1]);
460 }
461 s->SG_length = 0;
462 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
463 itv->cur_dma_stream = -1;
464 dma_post(s);
465 ivtv_stream_sync_for_cpu(s);
466 if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
467 u32 tmp;
468
469 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
470 tmp = s->dma_offset;
471 s->dma_offset = itv->vbi.dma_offset;
472 dma_post(s);
473 s->dma_offset = tmp;
474 }
475 wake_up(&itv->dma_waitq);
476}
477
478static void ivtv_irq_dma_err(struct ivtv *itv)
479{
480 u32 data[CX2341X_MBOX_MAX_DATA];
481
482 del_timer(&itv->dma_timer);
483 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
484 IVTV_DEBUG_WARN("DMA ERROR %08x %08x %08x %d\n", data[0], data[1],
485 read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
486 if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&
487 itv->cur_dma_stream >= 0 && itv->cur_dma_stream < IVTV_MAX_STREAMS) {
488 struct ivtv_stream *s = &itv->streams[itv->cur_dma_stream];
489
490 /* retry */
491 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
492 if (s->type >= IVTV_DEC_STREAM_TYPE_MPG)
493 ivtv_dma_dec_start(s);
494 else
495 ivtv_dma_enc_start(s);
496 return;
497 }
498 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
499 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
500 itv->cur_dma_stream = -1;
501 wake_up(&itv->dma_waitq);
502}
503
504static void ivtv_irq_enc_start_cap(struct ivtv *itv)
505{
506 u32 data[CX2341X_MBOX_MAX_DATA];
507 struct ivtv_stream *s;
508
509 /* Get DMA destination and size arguments from card */
510 ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA, data);
511 IVTV_DEBUG_IRQ("ENC START CAP %d: %08x %08x\n", data[0], data[1], data[2]);
512
513 if (data[0] > 2 || data[1] == 0 || data[2] == 0) {
514 IVTV_DEBUG_WARN("Unknown input: %08x %08x %08x\n",
515 data[0], data[1], data[2]);
516 return;
517 }
518 clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
519 s = &itv->streams[ivtv_stream_map[data[0]]];
520 if (!stream_enc_dma_append(s, data)) {
521 if (ivtv_use_pio(s)) {
522 dma_post(s);
523 ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, data[0]);
524 }
525 else {
526 set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
527 }
528 }
529}
530
531static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
532{
533 struct ivtv_stream *s_mpg = &itv->streams[IVTV_ENC_STREAM_TYPE_MPG];
534 u32 data[CX2341X_MBOX_MAX_DATA];
535 struct ivtv_stream *s;
536
537 IVTV_DEBUG_IRQ("ENC START VBI CAP\n");
538 s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
539
540 if (ivtv_use_pio(s)) {
541 if (stream_enc_dma_append(s, data))
542 return;
543 if (s->q_predma.bytesused)
544 ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
545 s->SG_length = 0;
546 dma_post(s);
547 return;
548 }
549 /* If more than two VBI buffers are pending, then
550 clear the old ones and start with this new one.
551 This can happen during transition stages when MPEG capturing is
552 started, but the first interrupts haven't arrived yet. During
553 that period VBI requests can accumulate without being able to
554 DMA the data. Since at most four VBI DMA buffers are available,
555 we just drop the old requests when there are already three
556 requests queued. */
557 if (s->SG_length > 2) {
558 struct list_head *p;
559 list_for_each(p, &s->q_predma.list) {
560 struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
561 ivtv_buf_sync_for_cpu(s, buf);
562 }
563 ivtv_queue_move(s, &s->q_predma, NULL, &s->q_free, 0);
564 s->SG_length = 0;
565 }
566 /* if we can append the data, and the MPEG stream isn't capturing,
567 then start a DMA request for just the VBI data. */
568 if (!stream_enc_dma_append(s, data) &&
569 !test_bit(IVTV_F_S_STREAMING, &s_mpg->s_flags)) {
570 set_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
571 set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
572 }
573}
574
575static void ivtv_irq_dev_vbi_reinsert(struct ivtv *itv)
576{
577 u32 data[CX2341X_MBOX_MAX_DATA];
578 struct ivtv_stream *s = &itv->streams[IVTV_DEC_STREAM_TYPE_VBI];
579
580 IVTV_DEBUG_IRQ("DEC VBI REINSERT\n");
581 if (test_bit(IVTV_F_S_CLAIMED, &s->s_flags) &&
582 !stream_enc_dma_append(s, data)) {
583 dma_post(s);
584 }
585}
586
587static void ivtv_irq_dec_data_req(struct ivtv *itv)
588{
589 u32 data[CX2341X_MBOX_MAX_DATA];
590 struct ivtv_stream *s;
591
592 /* YUV or MPG */
593 ivtv_api_get_data(&itv->dec_mbox, IVTV_MBOX_DMA, data);
594
595 if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
596 itv->dma_data_req_size = itv->params.width * itv->params.height * 3 / 2;
597 itv->dma_data_req_offset = data[1] ? data[1] : yuv_offset[0];
598 s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
599 }
600 else {
601 itv->dma_data_req_size = data[2] >= 0x10000 ? 0x10000 : data[2];
602 itv->dma_data_req_offset = data[1];
603 s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
604 }
605 IVTV_DEBUG_IRQ("DEC DATA REQ %s: %d %08x %u\n", s->name, s->q_full.bytesused,
606 itv->dma_data_req_offset, itv->dma_data_req_size);
607 if (itv->dma_data_req_size == 0 || s->q_full.bytesused < itv->dma_data_req_size) {
608 set_bit(IVTV_F_S_NEEDS_DATA, &s->s_flags);
609 }
610 else {
611 clear_bit(IVTV_F_S_NEEDS_DATA, &s->s_flags);
612 ivtv_queue_move(s, &s->q_full, NULL, &s->q_predma, itv->dma_data_req_size);
613 ivtv_dma_stream_dec_prepare(s, itv->dma_data_req_offset + IVTV_DECODER_OFFSET, 0);
614 }
615}
616
617static void ivtv_irq_vsync(struct ivtv *itv)
618{
619 /* The vsync interrupt is unusual in that it won't clear until
620 * the end of the first line for the current field, at which
621 * point it clears itself. This can result in repeated vsync
622 * interrupts, or a missed vsync. Read some of the registers
623 * to determine the line being displayed and ensure we handle
624 * one vsync per frame.
625 */
626 unsigned int frame = read_reg(0x28c0) & 1;
627 int last_dma_frame = atomic_read(&itv->yuv_info.next_dma_frame);
628
629 if (0) IVTV_DEBUG_IRQ("DEC VSYNC\n");
630
631 if (((frame ^ itv->yuv_info.lace_sync_field) == 0 && ((itv->lastVsyncFrame & 1) ^ itv->yuv_info.lace_sync_field)) ||
632 (frame != (itv->lastVsyncFrame & 1) && !itv->yuv_info.frame_interlaced)) {
633 int next_dma_frame = last_dma_frame;
634
635 if (next_dma_frame >= 0 && next_dma_frame != atomic_read(&itv->yuv_info.next_fill_frame)) {
636 write_reg(yuv_offset[next_dma_frame] >> 4, 0x82c);
637 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x830);
638 write_reg(yuv_offset[next_dma_frame] >> 4, 0x834);
639 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x838);
640 next_dma_frame = (next_dma_frame + 1) & 0x3;
641 atomic_set(&itv->yuv_info.next_dma_frame, next_dma_frame);
642 }
643 }
644 if (frame != (itv->lastVsyncFrame & 1)) {
645 struct ivtv_stream *s = ivtv_get_output_stream(itv);
646
647 itv->lastVsyncFrame += 1;
648 if (frame == 0) {
649 clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags);
650 clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
651 }
652 else {
653 set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
654 }
655 if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) {
656 set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags);
657 wake_up(&itv->event_waitq);
658 }
659 wake_up(&itv->vsync_waitq);
660 if (s)
661 wake_up(&s->waitq);
662
663 /* Send VBI to saa7127 */
664 if (frame)
665 vbi_schedule_work(itv);
666
667 /* Check if we need to update the yuv registers */
668 if ((itv->yuv_info.yuv_forced_update || itv->yuv_info.new_frame_info[last_dma_frame].update) && last_dma_frame != -1) {
669 if (!itv->yuv_info.new_frame_info[last_dma_frame].update)
670 last_dma_frame = (last_dma_frame - 1) & 3;
671
672 if (itv->yuv_info.new_frame_info[last_dma_frame].src_w) {
673 itv->yuv_info.update_frame = last_dma_frame;
674 itv->yuv_info.new_frame_info[last_dma_frame].update = 0;
675 itv->yuv_info.yuv_forced_update = 0;
676 queue_work(itv->yuv_info.work_queues, &itv->yuv_info.work_queue);
677 }
678 }
679 }
680}
681
682#define IVTV_IRQ_DMA (IVTV_IRQ_DMA_READ | IVTV_IRQ_ENC_DMA_COMPLETE | IVTV_IRQ_DMA_ERR | IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_VBI_CAP | IVTV_IRQ_DEC_DATA_REQ)
683
684irqreturn_t ivtv_irq_handler(int irq, void *dev_id)
685{
686 struct ivtv *itv = (struct ivtv *)dev_id;
687 u32 combo;
688 u32 stat;
689 int i;
690 u8 vsync_force = 0;
691
692 spin_lock(&itv->dma_reg_lock);
693 /* get contents of irq status register */
694 stat = read_reg(IVTV_REG_IRQSTATUS);
695
696 combo = ~itv->irqmask & stat;
697
698 /* Clear out IRQ */
699 if (combo) write_reg(combo, IVTV_REG_IRQSTATUS);
700
701 if (0 == combo) {
702 /* The vsync interrupt is unusual and clears itself. If we
703 * took too long, we may have missed it. Do some checks
704 */
705 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
706 /* vsync is enabled, see if we're in a new field */
707 if ((itv->lastVsyncFrame & 1) != (read_reg(0x28c0) & 1)) {
708 /* New field, looks like we missed it */
709 IVTV_DEBUG_YUV("VSync interrupt missed %d\n",read_reg(0x28c0)>>16);
710 vsync_force = 1;
711 }
712 }
713
714 if (!vsync_force) {
715 /* No Vsync expected, wasn't for us */
716 spin_unlock(&itv->dma_reg_lock);
717 return IRQ_NONE;
718 }
719 }
720
721 /* Exclude interrupts noted below from the output, otherwise the log is flooded with
722 these messages */
723 if (combo & ~0xff6d0400)
724 IVTV_DEBUG_IRQ("======= valid IRQ bits: 0x%08x ======\n", combo);
725
726 if (combo & IVTV_IRQ_DEC_DMA_COMPLETE) {
727 IVTV_DEBUG_IRQ("DEC DMA COMPLETE\n");
728 }
729
730 if (combo & IVTV_IRQ_DMA_READ) {
731 ivtv_irq_dma_read(itv);
732 }
733
734 if (combo & IVTV_IRQ_ENC_DMA_COMPLETE) {
735 ivtv_irq_enc_dma_complete(itv);
736 }
737
738 if (combo & IVTV_IRQ_DMA_ERR) {
739 ivtv_irq_dma_err(itv);
740 }
741
742 if (combo & IVTV_IRQ_ENC_START_CAP) {
743 ivtv_irq_enc_start_cap(itv);
744 }
745
746 if (combo & IVTV_IRQ_ENC_VBI_CAP) {
747 ivtv_irq_enc_vbi_cap(itv);
748 }
749
750 if (combo & IVTV_IRQ_DEC_VBI_RE_INSERT) {
751 ivtv_irq_dev_vbi_reinsert(itv);
752 }
753
754 if (combo & IVTV_IRQ_ENC_EOS) {
755 IVTV_DEBUG_IRQ("ENC EOS\n");
756 set_bit(IVTV_F_I_EOS, &itv->i_flags);
757 wake_up(&itv->cap_w);
758 }
759
760 if (combo & IVTV_IRQ_DEC_DATA_REQ) {
761 ivtv_irq_dec_data_req(itv);
762 }
763
764 /* Decoder Vertical Sync - We can't rely on 'combo', so check if vsync enabled */
765 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
766 ivtv_irq_vsync(itv);
767 }
768
769 if (combo & IVTV_IRQ_ENC_VIM_RST) {
770 IVTV_DEBUG_IRQ("VIM RST\n");
771 /*ivtv_vapi(itv, CX2341X_ENC_REFRESH_INPUT, 0); */
772 }
773
774 if (combo & IVTV_IRQ_DEC_AUD_MODE_CHG) {
775 IVTV_DEBUG_INFO("Stereo mode changed\n");
776 }
777
778 if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
779 for (i = 0; i < IVTV_MAX_STREAMS; i++) {
780 int idx = (i + itv->irq_rr_idx++) % IVTV_MAX_STREAMS;
781 struct ivtv_stream *s = &itv->streams[idx];
782
783 if (!test_and_clear_bit(IVTV_F_S_DMA_PENDING, &s->s_flags))
784 continue;
785 if (s->type >= IVTV_DEC_STREAM_TYPE_MPG)
786 ivtv_dma_dec_start(s);
787 else
788 ivtv_dma_enc_start(s);
789 break;
790 }
791 if (i == IVTV_MAX_STREAMS && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags)) {
792 ivtv_udma_start(itv);
793 }
794 }
795
796 spin_unlock(&itv->dma_reg_lock);
797
798 /* If we've just handled a 'forced' vsync, it's safest to say it
799 * wasn't ours. Another device may have triggered it at just
800 * the right time.
801 */
802 return vsync_force ? IRQ_NONE : IRQ_HANDLED;
803}
804
805void ivtv_unfinished_dma(unsigned long arg)
806{
807 struct ivtv *itv = (struct ivtv *)arg;
808
809 if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
810 return;
811 IVTV_ERR("DMA TIMEOUT %08x %d\n", read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
812
813 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
814 clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
815 clear_bit(IVTV_F_I_DMA, &itv->i_flags);
816 itv->cur_dma_stream = -1;
817 wake_up(&itv->dma_waitq);
818}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 18:42:55 -0500